PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s FEATURES 1 16 SEL0^ XIN 2 15 SEL1^ XOUT 3 14 GND SEL3^ 4 13 CLKC SEL2^ 5 12 VDD OE 6 11 CLKT GND 7 10 GND GND 8 9 GND VDD / GND* SEL0^ / VDD* SEL1^ • • • • • • VDD 12 11 10 9 DESCRIPTION OE XIN Oscillator Amplifier PLL (Phase Locked Loop) Q ^: *: 14 SEL2^ 15 OE 16 PLL602-3X 1 2 3 4 GND SEL3^ GND SEL 13 GND BLOCK DIAGRAM XOUT GND The PLL602-35 (PECL with inverted OE), PLL602-37 (CMOS), PLL602-38 (PECL), and PLL602-39 (LVDS) are high performance and low phase noise XO IC chips. They provide phase noise performance as low as –125dBc at 1kHz offset (at 155MHz) and a typical RMS jitter of 4pS RMS ( at 155MHz ). They accept fundamental parallel resonant mode crystals from 12 to 25MHz. PLL 602-3X • Selectable 750kHz to 800MHz range. Low phase noise output (@ 10kHz frequency offset, -140dBc/Hz for 19.44MHz, -127dBc/Hz for 106.25MHz, -125dBc/Hz for 155.52MHz, 110dBc/Hz for 622.08MHz). CMOS (PLL602-37), PECL (PLL602-35 and PLL602-38) or LVDS (PLL602-39) output. 12 to 25MHz crystal input. No external load capacitor required. Output Enable selector. Selectable 1/16 to 32x frequency multiplier. 3.3V operation. Available in 16-Pin (TSSOP or 3x3mm QFN). XIN • • PIN CONFIGURATION (Top View) 8 GND 7 CLKC 6 VDD 5 CLKT Internal pull-up On 3x3 package, PLL602-35/-38 do not have SEL0 available: Pin 10 is VDD, pin 11 is GND. However, PLL602-37/-39 have SEL0 (pin 10), and pin 11 is VDD. See pin assignment table for details. Q OUTPUT ENABLE LOGICAL LEVELS XOUT Part # PLL by-pass PLL602-3x PLL602-38 PLL602-35 PLL602-37 PLL602-39 OE 0 (Default) 1 0 State Output enabled Tri-state Tri-state 1 (Default) Output enabled OE input: Logical states defined by PECL levels for PLL602-38 Logical states defined by CMOS levels for PLL602-35/-37/-39 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 1 PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s FREQUENCY SELECTION TABLE SEL3 SEL2 SEL1 SEL0 Selected Multiplier 0 0 1 1 Fin x 32 0 1 1 0 Fin / 8 0 1 1 1 Fin x 2 1 0 0 1 Fin / 2 1 0 1 0 Fin / 16 1 0 1 1 Fin x 4 1 1 0 0 Fin / 4 1 1 0 1 Fin x 8 1 1 1 0 Fin x 16 1 1 1 1 No multiplication Note: SEL0 is not available (always “1”) for PLL602-35 and PLL602-38 in 3x3mm package PIN DESCRIPTIONS PLL602-35 and PLL602-38 (see next page of PLL602-37/-39) Name TSSOP Pin number 3x3mm QFN Pin number Type XIN XOUT OE GND CLKT CLKC SEL0 SEL1 SEL2 SEL3 VDD 2 3 6 7,8,9,10,14 11 13 16 15 5 4 1, 12 12 13 16 1,2,3,4,8,11 5 7 Not available 9 15 14 6,10 I I I P O O I I I I P Description Crystal input. See Crystal Specifications on page 3. Crystal output. See Crystal Specifications on page 3. Output enable pin (see OE logic state table on page 1). Ground. True output PECL Complementary output PECL. Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. Power Supply. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 2 PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s PIN DESCRIPTIONS PLL602-37/-39 (see previous page of PLL602-35/-38) Name TSSOP Pin number 3x3mm QFN Pin number Type XIN XOUT OE GND 2 3 6 7,8,9,10,14 12 13 16 1,2,3,4,8 I I I P CLKT 11 5 O CLKC 13 7 O SEL0 SEL1 SEL2 SEL3 VDD 16 15 5 4 1, 12 10 9 15 14 6,11 I I I I P Description Crystal input. See Crystal Specifications on page 3. Crystal output. See Crystal Specifications on page 3. Output enable pin (see OE logic state table on page 1). Ground. True output LVDS (PLL602-39) (N/C for PLL602-37) Complementary output LVDS (PLL602-39) (CMOS out for PLL602-37). Multiplier selector pins. These pins have an internal pull-up that will default SEL to ‘1’ when not connected to GND. Power Supply. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Recommended ESR SYMBOL CONDITIONS MIN. F XIN C L (xtal) RE Parallel Fundamental Mode 12 TYP. MAX. UNITS 25 MHz pF 30 Ω 20 AT cut 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 3 PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s 3. General Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic (with Loaded Outputs) I DD Operating Voltage V DD CONDITIONS PECL/LVDS/CMOS MIN. TYP. MAX. 50 50 50 25/25/15 65/45/30 100/80/40 3.63 55 55 55 Fout<24MHz 24MHz<Fout<96MHz 96MHz<Fout<800MHz 2.97 @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Output Clock Duty Cycle 45 45 45 Short Circuit Current ±50 UNITS mA V % mA 4. Jitter Specifications PARAMETERS Period jitter RMS 1 Period jitter Peak-toPeak 1 Integrated jitter RMS 2 CONDITIONS FREQUENCY With capacitive decoupling between VDD and GND. Over 10,000 cycles. With capacitive decoupling between VDD and GND. Over 10,000 cycles. Integrated 12 kHz to 20 MHz MIN. TYP. 19.44MHz 77.76MHz 2.2 3.5 155.52MHz 4.3 622.08MHz 5.0 19.44MHz 77.76MHz 17 25 155.52MHz 27 622.08MHz 35 155.52MHz 622.08MHz 2.6 2.5 MAX. UNITS ps ps 4 4 ps 5. Phase Noise Specifications PARAMETERS FREQUENCY @10Hz @100Hz @1kHz @10kHz @100kHz UNITS Phase Noise 2 relative to carrier (typical) 19.44MHz 77.76MHz 155.52MHz 622.08MHz -80 -72 -65 -55 -108 -103 -95 -85 -132 -122 -120 -109 -142 -130 -125 -115 -150 -125 -121 -110 dBc/Hz 6. CMOS Electrical Characteristics PARAMETERS Output drive current Output Clock Rise/Fall Time SYMBOL CONDITIONS MIN. I OH I OL V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V 0.3V ~ 3.0V with 15 pF load 10 10 TYP. 2.4 MAX. UNITS mA mA ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 4 PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change Output High Voltage Output Low Voltage Offset Voltage Offset Magnitude Change ∆V OD V OH V OL V OS Power-off Leakage I OXD Output Short Circuit Current I OSD CONDITIONS V OD R L = 100 Ω (see figure) MIN. TYP. MAX. UNITS 247 -50 355 454 50 1.6 0.9 1.125 0 ∆V OS V out = V DD or GND V DD = 0V 1.4 1.1 1.2 3 1.375 25 mV mV V V V mV ±1 ±10 uA -5.7 -8 mA 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 5 PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. V OH V OL R L = 50 Ω to (V DD – 2V) (see figure) V DD – 1.025 Output High Voltage Output Low Voltage MAX. UNITS V DD – 1.620 V V 10. PECL Switching Characteristics PARAMETERS SYMBOL Clock Rise Time Clock Fall Time Duty Cycle tr tf CONDITIONS MIN. 0.8V ~ 2.0V 2.0V ~ 0.8V Measured @ 1.4V 40 PECL Levels Test Circuit OUT MAX. UNITS 50 1.5 1.5 60 ns ns % PECL Output Skew OUT VDD 50Ω TYP. 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 6 PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s PACKAGE INFORMATION 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e B L 3x3mm QFN 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 7 PLL602-35/-37/-38/-39 750kHz – 800MHz Low Phase Noise Multiplier XO Universal Low Phase Noise IC’s ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL602-3X X C X X NONE= TUBE R= TAPE AND REEL PART NUMBER NONE= NORMAL PACKAGE L= GREEN PACKAGE TEMPERATURE C=COMMERCIAL I= INDUSTRIAL PACKAGE TYPE O=TSSOP Q=QFN Order Number PLL602-35OC-R Marking Package Option Order Number Marking Package Option PLL602-35OC TSSOP - Tape and Reel PLL602-38OC-R PLL602-38OC TSSOP - Tape and Reel PLL602-35OC PLL602-35OC TSSOP – Tube PLL602-38OC PLL602-38OC TSSOP – Tube PLL602-35QC-R PLL602-35QC QFN - Tape and Reel PLL602-38QC-R PLL602-38QC QFN - Tape and Reel PLL602-35QC PLL602-35QC QFN – Tube PLL602-38QC PLL602-38QC QFN – Tube PLL602-35OCL-R PLL602-35OCL TSSOP - Tape and Reel (GREEN) PLL602-38OCL-R PLL602-38OCL TSSOP - Tape and Reel (GREEN) PLL602-35OCL PLL602-35OCL TSSOP – Tube (GREEN) PLL602-38OCL PLL602-38OCL TSSOP – Tube (GREEN) PLL602-35QCL-R PLL602-35QCL QFN - Tape and Reel (GREEN) PLL602-38QCL-R PLL602-38QCL QFN - Tape and Reel (GREEN) PLL602-35QCL PLL602-35QCL QFN – Tube (GREEN) PLL602-38QCL PLL602-38QCL QFN – Tube (GREEN) PLL602-37OC-R PLL602-37OC TSSOP - Tape and Reel PLL602-39OC-R PLL602-39OC TSSOP - Tape and Reel PLL602-37OC PLL602-37OC TSSOP – Tube PLL602-39OC PLL602-39OC TSSOP – Tube PLL602-37QC-R PLL602-37QC QFN - Tape and Reel PLL602-39QC-R PLL602-39QC QFN - Tape and Reel PLL602-37QC PLL602-37QC QFN – Tube PLL602-39QC PLL602-39QC QFN - Tube PLL602-37OCL-R PLL602-37OCL TSSOP - Tape and Reel (GREEN) PLL602-39OCL-R PLL602-39OCL TSSOP - Tape and Reel (GREEN) PLL602-37OCL PLL602-37OCL TSSOP – Tube (GREEN) PLL602-39OCL PLL602-39OCL TSSOP – Tube (GREEN) PLL602-37QCL-R PLL602-37QCL QFN - Tape and Reel (GREEN) PLL602-39QCL-R PLL602-39QCL QFN - Tape and Reel (GREEN) PLL602-37QCL PLL602-37QCL QFN – Tube (GREEN) PLL602-39QCL PLL602-39QCL QFN – Tube (GREEN) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/28/05 Page 8