SAMSUNG S1L9223B01

RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
INTORDUCTION
80−QFP−1420C
The S1L9223B01 is a 1-chip BICMOS integrated circuit to perform the
function of RF amp and servo signal processor for compact disc
player applications.
It consist of blocks for RF signal processing, focus, tracking,
sled and spindle servo. Also this IC has adjustment free function
and embedded OP-AMP for audio post filter.
FEATURES
•
RF amplifier & RF equalizer
•
Focus error amplifier & servo control
•
Tracking error amplifier & servo control
•
Mirror & defect detector circuit
•
Focus OK detector circuit
•
APC (Auto Laser Power Control) circuit for constant laser power
•
FE bias & focus servo offset adjustment free
•
EF balance & tracking error gain adjustment free
•
Embedded audio post filter
•
The circuit for Interruption countermeasure
•
Double speed play available
•
Operating voltage range: S1L9223B01: 5V
ORDERING INFORMATION
Device
Package
Temperature Range
S1L9223B01-Q0R0
80-QFP-1420C
−20 to +70 °C
RELATED PRODUCT
•
S5L9286F01 Data Processor
•
S5L9284D Data Processor
•
KA9258D/KA9259D Motor Driver
1
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
RF-
ISTAT
RESET
MLT
MDATA
MCK
ATSC
TZC
29
31
38
37
36
35
51
52
73
RFO
74
PD1
65
PD2
66
FEBIAS
63
58
26
28
27
3
Focus Phase
Compensation
MICOM Data
Interface Logic
RF Amp
FRSH
LOCK
30
FS3
TRCNT
22
FGD
WDCH
54
FE2
TE1
59
FLB
FE1
BLOCK DIAGRAM
& Offset cancel circuit
Focus Error Amp
FE-BIAS Adjustment
F
67
E
68
EI
79
PD
Tracking Error Amp
E/F Balance & Gain
Control
MICOM TO SERVO CONTROL
AUTO SEQUENCER
69
APC Amp
LD
Tracking Phase
Compensation Block
& Jump Pulse GEN.
LDON
70
Sled Servo Amplifier
ADJUSTMENT-FREE CONTROL
71
EQC
78
EQO
76
IRF
75
ASY
32
EFM
33
2
TM1~ BAL1~ PS1~
TM6 BAL5 PS4
GA1~
GA5
Spindle Servo LPF
( Double Speed )
EFM
Comparator
77
5
15
16
13
14
19
17
12
11
9
10
RRC
CH2O
CH2I
GC2I
GC2O
FOK Detection
Circuit
MUTEI
4
Built-in Post Filter Amp ( L&R )
Defect Detection
Circuit
CH1I
2
Mirror Detection
Circuit
CH1O
DCC2
FS1~
FS4
GC1I
DCB
RF Level AGC
&
Equalizer
& Sled Kick GEN.
GC1O
RFI
Center Voltage Amp.
DCC1
VR
60
FDFCT
47
FE-
48
FEO
57
TDFCT
49
TE-
50
TEO
53
TE2
55
LPFT
62
TG2
61
TGU
43
SLO
44
SL-
42
SL+
46
SPDLO
45
SPDL-
23
SMDP
24
SMON
25
SMEF
6
FSET
39
MIRROR
1
MCP
40
FOK
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
PIN CONFIGURATION
65 PD1
SSTOP
SL+
SL-
SLO
SPDL-
SPDLO
FE-
FEO
TE-
TEO
ATSC
TE2
TZC
TE1
LPFT
DVDD
TDFCT
FE2
FE1
TGU
FDFCT
TG2
FEBIAS
DVEE
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
FOK 40
66 PD2
MIRROR 39
67 F
RESET 38
68 E
MLT 37
69 PD
MDATA 36
70 LD
MCK 35
71 VR
VSSA 34
S1L9223B01
72 VCC
73 RF-
EFM 33
ASY 32
74 RFO
ISTAT 31
75 IRF
TRCNT 30
76 EQO
LOCK 29
77 RFI
FGD 28
78 EQC
FS3 27
79 EI
FLB 26
SMON
SMDP
WDCK
GC2O
VREG
GC2I
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
ISET
VCCP
7
VSSP
VDDA
6
RRC
FSET
5
GC1I
DCC1
4
CH1I
DCC2
3
CH1O
FRSH
2
CH2O
DCB
1
CH2I
MCP
MUTEI
SMEF 25
GC1O
80 GND
3
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
PIN DESCRIPTION
Pin No.
Symbol
1
MCP
Capacitor connection pin for mirror hold
2
DCB
Capacitor connection pin for defect Bottom hold
3
FRSH
Capacitor connection pin for time constant to generate focus search waveform
4
DCC2
The input pin through capacitor of defect bottom hold output
5
DCC1
The output pin of defect bottom hold
6
FSET
The peak frequency setting pin for focus, tracking servo and cut off frequency of CLV
LPF
7
VDDA
Analog VCC for servo part
8
VCCP
VCC for post filter
9
GC2I
Amplifier negative input pin for gain and low pass filtering of DAC output CH2
10
GC2O
Amplifier output pin for gain and low pass filtering of DAC output CH2
11
CH2I
The input pin for post filter channel2
12
CH2O
The output pin for post filter channel2
13
CH1O
The output pin for post filter channel1
14
CH1I
The input pin for post filter channel1
15
GC1O
Amplifier output pin for gain and low pass filtering of DAC output CH1
16
GC1I
Amplifier negative input pin for gain and low pass filtering of DAC output CH1
17
RRC
The pin for noise reduction of post filter bias
18
VSSP
VSS for post filter
19
MUTEI
The input pin for post filter muting control
20
ISET
21
VREG
The output pin of regulator
22
WDCK
The clock input pin for auto sequence
23
SMDP
The input pin of CLV control output pin SMDP of DSP
24
SMON
The input pin for spindle servo ON through SMON of DSP
25
SMEF
The input pin of provide for an external LPF time constant
26
FLB
Capacitor connection pin to perform rising low bandwidth of focus loop
27
FS3
The pin for high frequency gain change of focus loop with internal FS3 switch
28
FGD
Reducing high frequency gain with capacitor between FS3 pin
29
LOCK
30
TRCNT
31
ISTAT
4
Description
The input pin for current setting of focus search, track jump and sled kick voltage
Sled runaway prevention pin
Track count output pin
Internal status output pin
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
PIN DESCRIPTION (Continued)
Pin No.
Symbol
Description
32
ASY
The input pin for asymmetry control
33
EFM
EFM comparator output pin
34
VSSA
Analog VSS for servo part
35
MCK
MICOM clock input pin
36
MDATA
MICOM data input pin
37
MLT
38
RESET
39
MIRROR
40
FOK
41
SSTOP
42
SL+
The noninverting input pin of sled servo amplifier
43
SLO
The output pin of sled servo amplifier
44
SL-
The inverting input pin of sled servo amplifier
45
SPDL-
The noninverting input pin of spindle servo amplifier
46
SPDLO
The output pin of spindle servo amplifier
47
FE-
The inverting input pin of focus servo amplifier
48
FEO
The output pin of focus servo amplifier
49
TE-
The inverting input pin of tracking servo amplifier
50
TEO
The output pin of tracking servo amplifier
51
ATSC
The input pin for Anti-shock detection
52
TZC
The comaparator input pin for tracking zero crossing detection
53
TE2
Tracking servo input pin
54
TE1
Tracking error amplifier output pin
55
LPFT
The input pin of tracking error low pass filtering signal
56
DVDD
The power supply pin for logic circuit
57
TDFCT
The capacitor connection pin for tracking defect compensation
58
FE2
Focus servo input pin
59
FE1
Focus error amplifier output pin
60
FDFCT
61
TGU
The capacitor connection pin for high frequency tracking gain switch
62
TG2
The pin for high frequency gain change of tracking servo loop with internal TG2 switch
MICOM data latch input pin
Reset input pin
The mirror output for test
The output pin of focus OK comparator
The pin for detection whether pick_up position is innermost or not
The capacitor connection pin for focus defect compensation
5
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
PIN DESCRIPTION (Continued)
Pin No.
Symbol
63
FEBIAS
64
DVEE
65
PD1
The negative input pin of RF I/V amplifier1(A+C signal)
66
PD2
The negative input pin of RF I/V amplifier2(B+D signal)
67
F
The negative input pin of F I/V amplifier (F signal)
68
E
The negative input pin of E I/V amplifier (E signal)
69
PD
The input pin for APC
70
LD
The output pin for APC
71
VR
The output pin of (AVEE+AVCC)/2 voltage
72
VCC
VCC for RF part
73
RF-
RF summing amplifier inverting input pin
74
RFO
RF summing amplifier output pin
75
IRF
The input pin for AGC
76
EQO
77
RFI
The input pin for EFM comparison
78
EQC
The capacitor connection pin for AGC
79
EI
80
GND
6
Description
Focus error bias voltage control pin
The DVEE pin for logic circuit
The output pin for AGC
Feedback input pin of E I/V amplifier for EF Balance control
GND for RF part
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Unit
VMAX
6
V
PD
200
mW
Operating Temperature
TOPR
−20 to + 70
o
C
Storage temperature
TSTG
−55 to + 150
o
C
Supply Voltage
Power Dissipation
ELECTRICAL CHARACTERISTICS
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Supply Current High
ICCHI
VCC = 6V, No load
−
20
40
60
mA
Supply Current Typ
ICCTY
VCC = 5V, No Load
−
12
30
48
mA
Supply Current Low
ICCLO
VCC = 3.4V, No Load
−
10
25
40
mA
RF Amp Offset Voltage
Vrfo
Input open
pin 74
−80
0
+80
mV
RF Amp Voltage Gain
Grf
SG3 f = 10kHz,
40mVp-p, sine
pin 74
25.1
28.1
31.1
dB
RF THD
Grfmd
SG3 f =1kHz, 40mVp-p,sine
pin 74
−
−
5
%
RF Amp Max. Output Voltage Vrfpp1
SG3 DC 2.7V
pin 74
3.8
−
−
V
RF Amp Min. Output Voltage Vrfpp2
SG3 DC 2.3V
pin 74
−
−
1.2
V
Focus Error Amp Offset
Voltage
Vfeo1
input open
pin 59
−450
−250
−50
mV
Focus Error Amp Auto Offset
Voltage
Vfeo2
WDCH=88.2kHz Pulse,
$841
pin 59
−35
0
35
mV
Focus Error Amp PD1
Voltage Gain
Gfe1
SG3 f=10kHz, 32mVp-p,
sine
pin 59
27
30
33
dB
Focus Error Amp PD2
Voltage Gain
Gfe2
SG3 f = 10kHz, 32mVp-p,
sine
pin 59
27
30
33
dB
Focus Error Amp Voltage
Difference
Gfe∆
∆Gfe1-∆Gfe1
pin 59
−3
0
+3
dB
Focus Error Amp Max.
Output Voltage
Gfepp1
SG3 DC 2.7V
pin 59
4.4
−
−
V
Focus Error Amp Min. Output
Voltage
Gfepp2
SG3 DC2.3V
pin 59
−
−
0.6
V
7
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
AGC Max Gain
Gagc
SG4 f = 500kHz, 20mVp-p,
sine
pin 76
16
19
22
dB
AGC EQ Gain
Geq
Gain Difference of Gagc at
f =1.5MHz
pin 76
0
1
2
dB
AGC Gain2
Gagc2
SG4 f = 500kHz, 0.5Vp-p,
sine
pin 76
3.5
6
9
dB
AGC Compress Ratio
Cagc
Gain Difference of Gagc2 at
0.1Vp-p
pin 76
0
2.5
5
dB
AGC Frequency
Fagc
Gain Difference
SG4 f=1.5MHz,0.1Vp-p,sine
and f=500kHz,0.1Vp-p,sine
pin 76
−1.5
0
2.5
dB
Tracking Error Offset Voltage Vteo
$800, $820, input open
pin 54
−50
0
+50
mV
Tracking Error Amp Voltage
Gain F
Gtef
$800, $820
SG3 0.3Vp-p, 10kHz, sine
pin 54
2.1
5.1
8.1
dB
Tracking Error Amp Voltage
Gain E
Gtee
SG3 0.3Vp-p, 40kHz, sine
pin 54
−0.75
2.25
5.25
dB
Tracking Error Amp
Voltage Gain Difference
Gte∆
Gtef-Gtee
pin 54
−0.25
2.75
5.75
dB
Tracking Error Amp
Maximum Output Voltage H
Vtepp1
DG3 DC 4.5V
pin 54
3.5
−
−
V
Tracking Error Amp
Minimum Output Voltage L
Vtepp2
SG3 DC 0.5V
pin 54
−
−
1.5
V
Tracking Error Amp Gain up
F
Tguf
$830 SG3 0.3Vp-p, 10kHz,
sine
pin 54
8.0
11.0
14.0
dB
Tracking Error Amp Gain up
E
Tgue
$830 SG3 0.3Vp-p, 10kHz,
sine
pin 54
5.3
8.3
11.3
dB
Tracking Gain Normal
Fgfn
SG3 0.3Vp-p, 10kHz, sine,
$820
pin 54
2.1
5.1
8.1
dB
Tracking F Gain 1
Fgf1
SG3 0.3Vp-p, 10kHz, sine,
$821
pin 54
0.1
3.1
6.1
dB
Tracking F Gain 2
Fgf2
SG3 0.3Vp-p,10kHz, sine,
$822
pin 54
−1.7
1.3
4.3
dB
Tracking F Gain 3
Fgf3
SG3 0.3Vp-p, 10kHz, sine,
$824
pin 54
−5.0
−2.0
1.0
dB
Tracking F Gain 4
Fgf4
SG3 0.3Vp-p, 10kHz, sine,
$824
pin 54
−9.2
−6.2
−3.2
dB
8
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Tracking E Balance Normal
Tben
SG3 0.3Vp-p, 10kHz, sine,
$800
pin 54
−0.27
2.27
5.27
dB
Tracking E Balance 1
Tbe1
SG3 0.3Vp-p, 10kHz, sine,
$801
pin 54
−0.51
2.51
5.51
dB
Tracking E Balance 2
Tbe2
SG3 0.3Vp-p, 10kHz, sine,
$802
pin 54
−0.74
2.74
5.74
dB
Tracking E Balance 3
Tbe3
SG3 0.3Vp-p, 10kHz, sine,
$804
pin 54
0.17
3.17
6.17
dB
Tracking E Balance 4
Tbe4
SG3 0.3Vp-p, 10kHz, sine,
$808
pin 54
1.03
4.03
7.03
dB
Tracking E Balance 5
Tbe5
SG3 0.3Vp-p, 10kHz, sine,
$810
pin 54
2.63
5.63
8.63
dB
FGFN-FGF1
∆FG1
−
−
0
1.5
3
dB
FGFN-FGF2
∆FG2
−
−
0.5
2.0
3.5
dB
FGFN-FGF3
∆FG3
−
−
2.0
3.2
4.5
dB
FGFN-FGF4
∆FG4
−
−
3.0
4.25
5.5
dB
TBE5 − TBE4
∆TB1
−
−
0.6
1.6
2.6
dB
TBE4 − TBE3
∆TB2
−
−
−0.14
0.86
1.86
dB
TBE3 − TBE2
∆TB3
−
−
−0.57
0.43
1.43
dB
TBE2 − TBE1
∆TB4
−
−
−0.77
0.23
1.23
dB
APC PSUB Voltage 1
Vapc1
LDON, $853, PN=open,
SG4 GND+85mV
pin 70
−
−
1.2
V
APC PSUB Voltage 2
Vapc2
LDON, $853, PN=open,
SG4 GND+185mV
pin 70
3.8
−
−
V
APC NSUB Voltage 1
Vapc3
LDON, $857, PN=2.5V,
SG4 GND+95mV
pin 70
3.8
−
−
V
APC NSUB Voltage 2
Vapc4
LDON, $857, PN=2.5V,
SG4 GND+165mV
pin 70
−
−
1.2
V
APC LD Off Voltage 1
Vapc5
LDOFF, $85C, PN=open,
SG4 2.5V
pin 70
4.0
−
−
V
APC LD Off Voltage 2
Vapc6
LDOFF, $858, PN=2.5V.
SG4 2.5V
pin 70
−
−
1.0
V
APC Maximum Output
Current H
Vapc7
LDON, $854, PN=open,
SG4 GND + 185mV
pin 70
2.5
−
−
V
9
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
APC Minimum Output
Current L
Vapc8
LDON, $854, SG4 GND +
85mV
pin 70
−
−
2.5
V
Mirror Maximum Output
Voltage H
Vmirh
SG4 2.1V+0.8Vp-p,
1kHz,sine
pin 39
4.3
−
−
V
Mirror Minimum Output
Voltage L
Vmirl
SG4 2.1V+0.8Vp-p,
1kHz,sine
pin 39
−
−
0.7
V
Mirror Minimum Operating
Frequency
Fmirh
SG4 2.1V + 0.8Vp-p,
900Hz,sine
pin 39
−
550
900
Hz
Mirror Maximum Operating
Frequency
Fmirb
SG4 2.1V+0.8Vp-p,
30kHz,sine
pin 39
30
75
−
KHz
Mirror AM Frequency
Characteristic
Fmir
SG4 2.1V+0.8Vp-p 600Hz,
fc=500kHz 55% modulation
pin 39
−
400
600
Hz
Mirror Minimum Input
Voltage
Vmir
SG4 2.1V + 0.2Vp-p,
10kHz,sine
pin 39
−
0.1
0.2
V
Mirror Maximum Input
Voltage
Vmih
SG4 2.1V+1.8Vp-p,
10kHz,sine
pin 39
1.8
−
−
V
FOK Threshold Voltage
Vfokt
SG4 2.25V~2.0V,DCsweep,
10mV step
pin 40
−420
−360
−300
mV
FOK Output Voltage H
Vfokh
SG4 DC 1.5V
pin 40
4.3
−
−
V
FOK Output Voltage L
Vfokl
SG4 DC 2.5V
pin 40
−
−
0.7
V
Defect Output Voltage H
Vdfcth
$863,SG3 2.520V+0.04Vp-p
f = 1kHz,sine
pin 41
4.3
−
−
V
Output Voltage L
Vdfcth
$863,SG3 2.520V+0.04Vp-p
f = 1kHz,sine
pin 41
−
−
0.7
V
Focus Loop Mute
Fmute
SG2 2.5V+0.1Vp-p
1kHz,sine
pin 48
−100
0
100
mV
Tracking Loop Mute
Tmute
SG2 2.5V+0.1Vp-p
1kHz,sine
pin 50
−100
0
100
mV
Interruption
Imute
SG2 2.5V+0.1Vp-p
1kHz,sine
pin 50
−100
0
120
mV
Defect Bottom Voltage
Fdfct1
SG3 2.520 V+0.04Vp-p,
1kHz,sine
pin 41
−
670
1000
Hz
Defect Max Freq. Voltage
Fdfct2
SG3 2.520V+0.04Vp-p,
2kHz,sine
pin 41
2.0
4.7
−
KHz
10
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Defect Minimum Input
Voltage
Vdfct1
SG 3 2.510V+0.020Vp-p,
1kHz,sine
pin 41
−
0.3
0.5
V
Defect Maximum Input
Voltage
Vdfct2
SG32.535V+0.070Vp-p,
1kHz,sine
pin 41
1.8
−
−
V
EFM Duty Voltage 1
Defm1
SG4 2.5V+0.75Vp-p,
750kHz,sine
pin 32
−50
0
50
mV
EFM Duty Voltage 2
Defm2
SG42.75V+0.75Vp-p,
750kHz,sine
pin 32
0
50
100
mV
EFM Minimum input Voltage
Vefm1
SG4 2.5V+0.12Vp-p,
750kHz,sine
pin 33
−
−
0.12
V
EFM Maximum input Voltage Vefm2
SG4 2.5V+1.8Vp-p
750kHz,sine
pin 33
1.8
−
−
V
EFM Maximum Operating
Frequency
Fefm
SG4 2.5V+0.75Vp-p
4MHz
pin 33
4
−
−
MHz
FZC Threshold Voltage
Vfzc
DC 2.5V+38mV,100mV
pin 31
35
69
100
mV
ATSC Threshold Voltage 1
Vatsc1
$10,SG2 DC 2.5V-6mV
−45mV
pin 31
−67
−32
−7
mV
ATSC Threshold Voltage 2
Vatsc2
SG2 DC 2.5V+6mV,+45mV
pin 33
7
32
67
mV
TZC Threshold Voltage
Vtzc
$20,SG2 DC 2.5V-20mV
+20mV
pin 31
−30
0
30
mV
SSTOP Threshold Voltage
Vsstop
$30,SG2 DC 2.5V-71mV
−30mV
pin 31
−100
−50
−30
mV
Tracking gain window
voltage
VtGW
$840+$830 SG2 2.5V 2.9V
5mV DC
pin 30
200
250
300
mV
Tracking gain window range
VTGW2
$848+$830 SG2 2.5V 5mV
DC sweep
pin 30
100
150
200
mV
Tracking balance window
voltage
VTBW
$844+$810 SG2 2.555V ~
2.475V 5mV DC sweep
pin 31
−25
15
55
mV
Tracking balance window
range
VTBW2
$844+$810 SG2 2.555V ~
2.470V 5mV DC sweep
pin 31
−25
15
55
mV
Vreg Threshold Voltage
Vreg
pin 21
3.2
3.4
3.6
V
−
11
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Center Voltage
VCVO
2.5V Reference
pin 71
−100
0
100
mV
VREF Current Drive Voltage
1
VCVO1
2.5V Reference
pin 71
−100
0
100
mV
VREF Current Drive Voltage
2
VCVO2
2.5V Reference
pin 71
−100
0
100
mV
Post CH1 Freq.
Characteristic
Fpos1
SG1 2.5V+1Vp-p
40kHz,sine
pin 13
−4.5
−3.0
−1.5
dB
Post CH2 Freq.
Characteristic
Fpos2
SG1 2.5V+1Vp-p
40kHz,sine
pin 12
−4.5
−3.0
−1.5
dB
Post CH1 Mute
Mute1
Mute=5V
SG1 2.5V+1Vp-p,1kHz,sine
pin13
−
−
-35
dB
Post CH2 Mute
Mute2
Mute=5V
SG1 2.5V+1Vp-p,1kHz,sine
pin 12
−
−
-35
dB
Focus Loop DC Gain
Gf
$08, SG2 DC 2.6V, 2.4V
average
pin 48
19.0
21.5
24.0
dB
Focus Off Offset
Vosf1
$00
pin 48
−100
0
100
mV
Focus On Offset
Vofs2
$08,DC 2.5V
pn 48
0
250
500
mV
Focus Auto Offset
Vaof
$842, WDCK, after100ms
pin 48
−65
0
65
mV
Focus Output Voltage H
Vfoh1
$08, DC 3.0V
pin 48
4.40
−
−
V
Focus Output Voltage L
Vfol1
$08, DC 2.0V
pin 48
−
−
0.60
V
Focus Output Drive Voltage
H
Vfoh2
$08, DC 3.0V
pin 48
3.68
−
−
V
Focus Output Drive Voltage
L
Vfol2
$08, DC 2.0V
pin 48
−
−
1.32
V
Focus Oscillation Voltage
Vosc
$08, DC2.5V
pin 48
0
100
200
mV
Focus Feed Through
Gff
Gain Difference at Servo on
and off
pin 48
−
−
−35
dB
Focus AC Gain 1
Gfa1
$08, SG2 2.5V+0.1Vp-p
1.2kHz,sine
pin 48
19.0
23.0
27.0
dB
Focus AC Phase 1
Pfa1
$08, SG2 2.5V + 0.1Vp-p
1.2kHz,sine
pin 48
40
65
90
deg
Focus AC Gain 2
Gfa2
$08, SG2 2.5V + 0.1Vp-p
2.7kHz,sine
pin 48
14.0
18.5
23.0
dB
Focus AC Phase 2
Pfa2
$08, SG2 2.5V+0.1Vp-p
2.7kHz,sine
pin 48
40
65
90
deg
12
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Focus Search Voltage1
Vfs1
$30+$02
pin 48
−0.64
−0.50
−0.36
V
Focus Search Voltage2
Vfs2
$30+$03
pin 48
0.36
0.50
0.64
V
Focus Loop Total Gain
Gftg
Focus PD gain + Focus loop
DC gain
pin 48
49.5
51.5
53.5
dB
Tracking DC Gain
Gto
$25 SG2 DC 2.3V,2.7V
average gain
pin 50
13.5
15.5
17.5
dB
Tracking Off Offset
Vost1
$20
pin 50
−100
0
100
mV
Tracking On Offset
Vost2
SG2, DC 2.5V, $25
pin 50
−100
0
120
mV
Tracking Oscillation Voltage
Vosa1
$25, SG2 DC2.5V
pin 50
0
100
200
mV
Tracking gain boost for ATSC Gatsc
2.5V + 0.1Vp-p, 1kHz, sine
pin 50
17.5
20.5
23.5
dB
Tracking gain boost on
LOCK (L)
Glock
2.5V + 0.1Vp-p,1kHz,sine
pin 50
17.5
20.5
23.5
dB
Tracking Output Voltage H
Vth1
$25,SG2 DC 1.0V
pin 50
4.48
−
−
V
Tracking Output Voltage L
Vtl1
$25, SG2 , DC 4.0V
pin 50
−
−
0.52
V
Tracking Output Drive
Voltage H
Vth2
$25, SG2 DC2.0V
pin 50
3.68
−
−
V
Tracking Output Drive
Voltage L
Vtl2
$25, SG2 DC3.0V
pin 50
−
−
1.32
V
Tracking Jump Voltage 1
Vtj1
$2C
pin 50
−0.64
−0.5
−0.36
V
Tracking Jump Voltage 2
Vtj2
$28
pin 50
0.36
0.5
0.64
V
Tracking Feed Through
Gtf
Gain Difference at Tracking
servo on and off
pin 50
−
−
−39
dB
Tracking AC Gain 1
Gta1
$10,$25,SG2
2.5V + 0.1Vp-p, 1.2kHz,sine
pin 50
9.0
12.5
16.0
dB
Tracking AC Phase 1
Pta1
$10, $25, SG2
2.5V+ 0.1Vp-p, 1.2kHz,sine
pin 50
−140
−115
−90
deg
Tracking AC Gain 2
Gta2
$10, $25, SG2
2.5V+ 0.1Vp-p, 2.7kHz, sine
pin 50
17.5
21.5
25.5
dB
Tracking AC Phase 2
Pta2
$10,$25,SG2
2.5V + 0.1Vp-p, 2.7kHz,sine
pin 50
−195
−150
−100
deg
Tracking Loop Gain
Gtrt
tracking Amp F gain+ servo
DC gain
-
18.5
20.5
22.5
dB
13
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Sled DC Gain
Gsl
SG2 DC 2.6V,2.4V
pin 43
20.5
22.5
24.5
dB
Sled Feed Through
Gslf
Gain Difference at sled
servo on and off
SG2 2.5V + 0.1Vp-p
1.2kHz,sine
pin 43
−
−
−34
dB
Sled Output Voltage H
Vslh1
$25, SG2 DC 2.9V
pin 43
4.48
−
−
V
Sled Output Voltage L
Vsll1
$25, SG2 DC 2.1V
pin 43
−
−
0.52
V
Sled Output Drive Voltage H
Vslh2
$25, SG2 DC 2.9V
pin 43
3.68
−
-
V
Sled Output Drive Voltage L
Vsll2
$25, SG2 DC 2.1V
pin 43
−
−
1.32
V
Sled Forward Kick Voltage
Vsk1
$22
pin 43
0.38
0.60
0.75
V
Sled Reverse Kick Voltage
Vsk2
$23
pin 43
−0.75
−0.6
−0.38
V
Spindle Normal Speed Gain
Gsp
$F0
SG1 DC 2.6V, 2.4V,
average gain
pin 46
14.0
16.5
19.0
dB
Spindle Double Speed Gain
Gsp2
$F3
SG1 DC 2.6V, 2.4V,
average gain
pin 46
19.0
23.0
27.0
dB
Spindle Output Voltage H
Gsph1
$F0, SG1 DC 3.5V
pin 46
4.48
−
−
V
Spindle Output Voltage L
Gspl1
$F0, SG1 DC 1.5V
pin 46
−
−
0.52
V
Spindle Output Drive Voltage
H
Gsph2
$F0,SG1 DC 3.5V
pin 46
3.68
−
−
V
Spindle Output Drive Voltage
L
Gspl2
$F0,SG1 DC 1.5V
pin 46
−
−
1.32
V
Spindle AC Gain
Gspa
$F0,SG1 2.5V + 0.2Vp-p,
2kHz,sine
pin 46
−7.0
−3.5
0
dB
Spindle AC Phase
Pspa
$F0,SG1 2.5V + 0.2Vp-p,
2kHz,sine
pin 46
−120
−90
−60
deg
14
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Post Filter Output Voltage
max. 1
Vpom1
SG1 2.5V + 3.2Vp-p, 1kHz,
within THD 1%
pin 13
1.1
1.3
−
Vrms
Post Filter Output Voltage
max. 2
Vpom2
SG1 2.5V + 3.2Vp-p, 1kHz,
within THD 1%
pin 12
1.1
1.3
−
Vrms
Total Harmonic Distoration 1
THD11
SG1 f = 100Hz, 0dBm
pin 13
−
0.01
0.05
%
Total Harmonic Distoration 1
THD12
SG1 f=1kHz,0dBm
pin 13
−
0.01
0.05
%
Total Harmonic Distoration 1
THD13
SG1 f = 10kHz, 0dBm
pin 13
−
0.05
0.1
%
Total Harmonic Distoration 1
THD14
SG1 f = 16kHz, 0dBm
pin 13
−
0.1
0.2
%
Total Harmonic Distoration 1
THD15
SG1 f = 20kHz, 0dBm
pin 13
−
0.1
0.2
%
Total Harmonic Distoration 2
THD21
SG1 f = 100Hz, 0dBm
Pin 12
−
0.01
0.05
%
Total Harmonic Distoration 2
THD22
SG1 f = 1kHz, 0dBm
Pin 12
−
0.01
0.05
%
Total Harmonic Distoration 2
THD23
SG1 f = 10kHz, 0dBm
Pin 12
−
0.05
0.1
%
Total Harmonic Distoration 2
THD24
SG1 f = 16kHz, 0dBm
Pin 12
−
0.1
0.2
%
Total Harmonic Distoration 2
THD25
SG1 f = 20kHz, 0dBm
Pin 12
−
0.1
0.2
%
Frequency Characteristics 1
fv11
SG1 f = 100Hz, 0dBm
pin 13
−0.1
0
0.1
dB
Frequency Characteristics 1
fv12
SG1 f = 1kHz, 0dBm
pin 13
−0.25
0
+0.25
dB
Frequency Characteristics 1
fv13
SG1 f = 10kHz, 0dBm
pin 13
−0.5
0
0.5
dB
Frequency Characteristics 1
fv14
SG1 f = 16kHz, 0dBm
pin 13
−1.0
0
1.0
dB
Frequency Characteristics 1
fv15
SG1 f = 20kHz, 0dBm
pin 13
−1.5
0
1.5
dB
Frequency Characteristics 2
fv21
SG1 f = 100Hz, 0dBm
Pin 12
−0.1
0
0.1
dB
Frequency Characteristics 2
fv22
SG1 f = 1kHz, 0dBm
Pin 12
−0.25
0
+0.25
dB
Frequency Characteristics 2
fv23
SG1 f = 10kHz, 0dBm
Pin 12
−0.5
0
0.5
dB
Frequency Characteristics 2
fv24
SG1 f = 16kHz, 0dBm
Pin 12
−1.0
0
1.0
dB
Frequency Characteristics 2
fv25
SG1 f = 20kHz, 0dBm
Pin 12
−1.5
0
1.5
dB
Crosstalk 1
CT11
SG1 100Hz, 0dBm, ratio on
Ch2
pin 13
70
80
−
dB
Crosstalk 1
CT12
SG1 1kHz, 0dBm, ratio on
Ch2
pin 13
65
75
−
dB
Crosstalk 1
CT13
SG1 10kHz, 0dBm, ratio on
Ch2
pin 13
60
65
−
dB
15
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
ELECTRICAL CHARACTERISTICS (Continued)
(Ta=25°C, VDD = DVDD = VCC = +5V, VSS = DVSS = GND = VSSP = 0V)
Characteristic
Symbol
Test Conditions
Output
Min.
Typ.
Max.
Unit
Crosstalk 2
CT21
SG1 100Hz,0dBm,ratio on
Ch1
pin 12
70
80
−
dB
Crosstalk 2
CT22
SG1 1kHz,0dBm,ratio on
Ch1
pin 12
65
75
−
dB
Crosstalk 2
CT23
SG1 10kHz,0dBm, ratio on
Ch1
pin 12
60
65
−
dB
Signal to Noise Ratio 1
S/N 1
DC 2.5V 0dbm, ratio on
Noise
pin 13
73
80
−
dB
Signal to Noise Ratio 2
S/N 2
DC 2.5V 0dbm, ratio on
Noise
pin 12
73
80
−
dB
Channel Balance
CB
Gain Difference Ch1 and
Ch2
−
−0.1
0
+0.1
dB
16
DC
SG3
AC
10K SW30
10K SW31
390K SW32
390K SW33
SW34
3K SW35
3K SW36
0.5K SW37
65 PD1
66 PD2
67 F
68 E
69 PD
70 LD
+
SG2
AC
1 2
1 2
SW17
1
SW16
2
1
2
SW15
SW14
SW13
72 VCC
74 RFO
76 EQO
78 EQC
80 GND
5
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
4
8
3
7
2
27K
S1L9223B01
TE2
+
330PF
5.6K 5.6K
LPFT
10PF
TE1
CH2I
330PF
5.6K 5.6K
+
27K
10PF
+
+
FEVSSP
SPDL-
ISET
+
SG_D12
RESET 38
VECTOR_TEST_IN
VECTOR_TEST_IN
VECTOR_TEST_IN
VECTOR_TEST_IN
VECTOR_TEST_IN
SG-D3
SG-D4
SG-D5
SG-D6
SG-D7
SG-D8
FOK 40
MLT 37
VECTOR_TEST_IN
SW11
SW10
SW8
VECTOR_TEST_IN
SW9
1000PF
SG-D2
MCK 35
11K 0.01UF
+
MDATA 36
SMEF 25
FLB 26
FS3 27
FGD 28
LOCK 29
VECTOR_TEST_OUT
TRCNT 30
ISTAT 31 VECTOR_TEST_OUT
ASY 32
EFM 33
VSSA 34
MIRROR 39
SL+
VECTOR_TEST_IN
SW19
SW18
100K
DC
+
SW20
0.25K
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
13K
6
1
+
3300PF
+
AC
DC
SG1
MUTEI
SSTOP
SMON
SW7
0.5K SW38
0.25K
SLO
SMDP
VECTOR_TEST_IN
GND(0V)
+ 33UF
100K
TEO
GC1O
71 VR
13K
WDCK
SW6
73 RF-
60K
SL-
SG-D1
22K
0.25K
5K
13K
FEO
RRC
4.7UF
SWP2
VREG
SW5
TEGC1I
4.7UF 27K
SW2
240K
ATSC
CH1I
5.6K
10K
SW3
0.1UF
TZC
CH1O
3.3UF
CH2O
3.3UF
2PF
SW22 VERTOR_TEST_IN
SG-_D10
DVDD
10K
0.01UF SW39
SW21
GC2I
GC2O
5.6K
SW-VC
AC
SW23 VERTOR_TEST_IN
SG-_D11
TDFCT
0.001UF
75 IRF
SW24
VCCP
SW1
SW40
SW25
FE2
4.7UF 27K
VC(2.5V)
SG4
VERTOR_TEST_IN
FE1
VDDA
SWP1
VCC(5V)
DC
200K
0.01UF
SW26
FSET
DCC1
0.01PF
77 RFI
SW27
FDFCT
DCC2
SW41
96K
FRSH
+
100K
13K
SPDLO
0.25K
200K
0.01UF
SW28
TG2
TGU
510K
DVEE
DCB
SW4 4.7UF
79 EI
SW29
FEBIAS
MCP
1000PF
1uF
SW42
3300PF
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
TEST CIRCUIT
17
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
FUNCTIONAL DESCRIPTION
RF AMP BLOCK
RF AMPLIFIER
The optical currents input through pins PD1(A+C) and PD2(B+D) are converted into voltages through I-V amp, and
they are added to RF summing amp. The voltage, converted from the photo diode (A+B+C+D) signal, is output
through RFO (pin74) and the eye pattern can be checked at this pin.
58K
PD1
-
65
+
VA
10K
-
RFO
74
I-V amp(1)
+
VC
RF summing amp
VC
58K
PD2
-
66
+
VB
RF-
10K
73
I-V amp(2)
VC
Figure 1. RF Amplifier Circuit
FOCUS ERROR AMP
The output of the focus error amp is the difference between I-V amp(1) output VA and
RF I-V amp(2) output VB. The focus error bias voltage applied to the (+) of focus error amp can be changed by
output voltage of D/A converter as shown in diagram, so that the offset of focus error amp can be adjusted
automatically by controlling 5 bits counter switches. Focus error bias can be adjusted from the range of +100mV —
-100mV by connecting the resistor on pin 63 (FEBIAS).
18
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
164K
32K
VB >
-
VA >
FE1
59
32K
+
sev-stopb
160K
FEBIAS
SW1
63
sev-stop
<5 Bit Counter>
4K
-
3K
X1
X2
X4
X8
X16
FEBIAS
+
1.
2.
fcmpo
+
vc
fe-stopb
VA and VB refer to output signal of PD1 and PD2 I/V amp.
sev-stopb,sev-stop,fe-stopb and fcmpo are internal signals
Figure 2. Focus Error Amplifier Circuit
TRACKING ERROR AMP
The optical currents detected from the side photo diode (E and F) pf pick-up are input to the E and F pin and
converted into voltage signals by E I-V and F I-V amp. The output of tracking error amp generates the difference
between E I-V AMP and F I-V AMP voltage output.
The E-F balance can be adjusted by modifying the gain of E I-V AMP, and the tracking gain can be adjusted
automatically by controlling the peak voltage at pin TE2 by MICOM program.
TE1
F
67
I-V AMP
-
68
I-V AMP
+
TE2
54
55
53
BAL < 4 : 0 >
3.3K
1.5K
16K
7.5K
27K
13K
56K
110K
79
75K
EI
220K
E
13K
-
LPFT
Balance
Window Comp
31
ISTAT
Gain
Window Comp
30
TRCNT
GAIN_UP/DOWN
GAIN < 3 : 0 >
Figure 3. Tracking Error Amplifier Circuit
19
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
FOCUS OK CIRCUIT
The FOK is the output. The focus OK circuit generates a timing window to enable focus servo operation from focus
search status. When the difference of the RFO (pin74) signal and DC coupled signal IRF (pin75) are above the
predefined voltage the Focus OK circuit output (pin40) becomes active (High output). The predefined voltage is 0.39V
40K
40K
RFO
74
-
IRF
75
+
57K
FOK
40
40K
+
90K
VC+0.625V
Figure 4. Focus OK Circuit
MIRROR CIRCUIT
IRF signal is amplified by the mirror amp, and the peak and bottom component of amplified signal are detected by
peak and bottom hold circuit. The peak hold circuit covers traverse signal of up to 100KHz component and bottom
hold circuit capable of covering the envelope frequency of disc rotation. The time constant for the mirror hold must
be sufficiently larger than that of the traverse signal.
38K
IRF
75
17K
+
19K
2.5K
Peak and
Bottom
Hold
1
MCP
39
MIRROR
17K
+
96K
+
-
Figure 5. Mirror Circuit
20
1.5K
+
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
EFM COMPARATOR
The EFM comparator converts a RF signal into a binary signal.
Because the asymmetry generated due to variations in disc manufacturing can not be eliminated by the AC
coupling alone, this circuit uses to control reference voltage of EFM comparator for eliminating asymmetry.
40K
+
77
RFI
33
EFM
32
ASY
100K
+
+
19K
20K
-
100K
85K
Figure 6. EFM Comparator & Asymmetry Circuit
DEFECT CIRCUIT
The RFO signal bottom, after being inverted, is held with two time constants of long and short.
The short time-constant bottom hold is done for a disc mirror defect more than 0.1msec, the long time-constant
bottom hold is done with the mirror level prior to the defect. By differentiating this with a capacitor coupling and
shifting the level, both signals are compared to generate the mirror defect detection signal.
DCC1
DCC2
5
4
75K
RFO
74
37.5K
-
BOTTOM
+
HOLD
28K
75K
-
BOTTOM
VC+0.6254V
HOLD
DFCT
41
43K
SSTOP/DFCT
+
2
DCB
Figure 7. Defect Circuit
21
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
APC (AUTO POWER CONTROL) CIRCUIT
The laser diode has large negative temperature characteristic in its optical output when driven with a constant
current on laser diode. Therefore, the output on processing monitor photo diode, must be a controlled current for
getting regular output power, thus the APC (Auto Power Control) circuit is composed.
PN (From MICOM command)
150K
+
PD 69
43.5K
+
0.75K
70
-
150K
LD
300K
150K
5.5K
1.25V
LDON (From MICOM command)
Figure 8. APC Circuit
AGC STABILITY CIRCUIT
The AGC block is the function used to maintain the constant level of RF peak to peak voltage. After the operation of
RF envelop detection and comparing with reference voltage, RFO level is kept stable in 1Vp-p, and input to EFM
Slice.
IRF
75
VCA
EQUALIZE
78
EQC
76 EQO
Figure 9. AGC Block
22
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
POST FILTER
The adjustment of audio output gain and the integration of possible de-emphasis output are executed by this circuit.
This block has amps of 2 channel for gain and filter setting and mute pin for audio signal muting.
CH2I
VCC
12 CH2O
+
GC2I
25K
-
10 GC2O
+
+
+
GC1I
25K
CH1I
15 GC1O
+
13 CH1O
-
19
MUTEI
Figure 10. Post Filter Circuit
CENTER VOLTAGE GENERATION CIRCUIT
The center voltage is generated by voltage divide using resistor.
VCC
30K
71 VR
+
30K
Figure 11. Center Voltage Generation Circuit
23
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
SERVO BLOCK
FOCUS SERVO BLOCK
When defect is "H" (the defect signal is detected), the focus servo loop is muting in case of focus phase
compensation. At this time, the focus error signal is output through the low pass filter formed by connecting a
capacitor (0.1µF) and a built-in 470KΩ resistor to the FDFCT pin (pin 60). Accordingly, the focus error output is held
at the error value just before defect error during defect occurring. The peak frequency of focus loop phase
compensation is at about 1.2KHz when the resistor connected to FSET pin (pin 6) is 510KΩ, and it is inversely
proportional to the resistor connected to the FSET pin. While the focus search is operating, the FS4 switch is on
and then the focus error signal is isolated, accordingly the focus search signal is output by FEO pin (pin 48). When
the FS2 switch is on (focus on), the focus servo loop is on and the focus error signal from FE2 pin (pin 58) is output
through the focus servo loop.
3.6K
60K
VC
-
FZCI
-
48
+
20K
58
48K
X4
92K
Focus Phase
Compensation
470K
FDFCT
FSCMPO
+
+
FE2
-
X3
X2
X1
-
60
+
40K
FS4B
FS2B
130K
FE-
47
DFCTI
10K
470K
FGD
28
40K
50K
3.6K
PS
FS3
27
FS1
46K
580K
+
FS3
26
3
6
FLB
FSET
Figure 12. Focus Servo Block
24
FEO
FRCH
4
3
X1
0
0
X2
0
1
X3
1
0
X4
1
1
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
TRACKING SERVO BLOCK
During detection of defect, the tracking error signal is output through the tracking servo loop after passing the low
pass filter formed by connecting a capacitor (0.1µF) and a built-in 470KΩ resistor to the TDFCT pin (pin57) in case
of tracking phase compensation. The value of tracking gain up/down can be controlled by TGU and TG2 pin. The
peak frequency of tracking loop phase compensation, the dynamic range and offset of OP AMP can be adjusted by
changing the value of resistor connected to FSET pin same as focus loop. In case of unstable status of actuator
after jumping, the ON/OFF of tracking loop is controlled by TM7 switch of break circuit.
After 10-track jumping, servo circuit gets out of the liner range and actuator's tracking becomes occasionally
unstable. Hence unnecessary jumping with many tracking error should be prevented.
TM4
TE2
53
470K
680K
57
TDFCT
49
680K
TG1
TE-
TM3
TG1
DFCTI
10K
66PF
TM1
110K
TGU
61
20K
TG2
TRACKING
PHASE
COMPENSATION
10K
90K
50
TEO
+
82K
TM7
62
TG2
470K
6
FSET
Figure 13. Tracking Servo Block
25
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
SLED SERVO BLOCK
The moving of pick-up is controlled by tracking servo output through a low pass filter.
The sled kick voltage is output for track jump operation.
SLO
43
TM6
TM7
X1
X2
X3
X4
SL-
-
PS
44
SL+
4
3
0
0
1
1
0
1
0
1
42
+
TM2
Figure 14. Sled Servo Block
SPINDLE SERVO BLOCK
The 20KΩ resistor and 0.33uF capacitor form the 200Hz low pass filter, and the carrier component of spindle servo
error signals is eliminated. In CLV-S mode, SMEF becomes "L" and pin 25 low pass filter fc lowers, strengthening
the filter further. The characteristics of high frequency phase compensation in focus tracking servo and the
characteristics of cut off frequency in CLV low pass filter are tested by FSET pin.
SMON 24
22K
22K
220K
15K
220K
SMDP
23
20K
-
+
220K
25
Double
speed
6
SMEF
FSET
Figure 15. Spindle Servo Block
26
46
SPDLO
50K
220K
15K
+
100K
-
45 SPDL-
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
DIGITAL BLOCK
DESCRIPTION
Digital block is transferred serial data by MICOM and 8-bit serial data is converted to parallel data by serial to
parallel register. This data is decoded by latch signal. The status output of focus servo, tracking servo and sled
servo system,etc. It is determined by each data. The auto-sequence function process 2 — 4 MICOM command by
one auto-sequence command.
MDATA
D0
D1
D2
D4
D3
D5
D6
D7
tsu
twck
twck
tsn
MCK
MLT
td
twl
Figure 16. CPU Serial Interface Timing Chart
Item
Symbol
Min
Typ
Max
Unit
−
−
1
MHz
Clock Frequency
fck
Clock Pulse Width
fwck
500
−
−
ns
Hold Time
tsu
500
−
−
ns
Setup Time
tn
500
−
−
ns
Delay Time
td
500
−
−
ns
Latch Pulse Width
twl
1000
−
−
ns
27
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
MICOM COMMAND SET
Item
Hexa
Address
Data
ISTAT Out
D7
D6
D5
D4
D3
D2
D1
D0
Focus
Control
$0X
0
0
0
0
FS4
Focus On
FS3
Gain Down
FS2
Search On
FS1
Search Up
FZC
Tracking
Control
$1X
0
0
0
1
Anti Shock
Brake On
TG2
Gain Set
TG1
Gain Set
A.S
Tracking
Mode
$2X
0
0
1
0
Select
$3X
0
0
1
1
PS4
Focus
Search+2
PS3
Focus
Search+2
Auto
Sequence
$4X
0
1
0
0
AS3
AS2
AS1
AS0
R Blind/
A overflow
M
Break
0.18ms
0.09ms
0.045ms
0.022ms
$5X
0
1
0
1
0.36ms
0.18ms
0.09ms
0.045ms
Kick
$6X
11.6ms
5.80ms
0.09ms
0.045ms
64
32
16
8
128
64
32
16
S
E
T
0
1
1
0
2N
jump
move
(M)
Auto Adj.
Speed
Tracking Mode
Sled Mode
TZC
PS2
PS1
Sled Kick+2 Sled Kick+1
STOP
/BUSY
Hi-Z
$7X
0
1
1
1
$8XX
1
0
0
0
Offset, Balance, Gain, APC Control
−
$FX
1
1
1
1
$F0: Normal Speed
$F3: Double Speed
−
Focus Control ($0X)
This command consists of 8 bits data and expressed by two hexa $0X.
D7
D6
D5
D4
D3
D2
D1
D0
ISTAT
0
0
0
0
FS4
FS3
FS2
FS1
FZC
FS4, FS3, FS2, FS1: internal switch for focus control
•
Focus Search Operation (FS2,FS1)
$02: FS2 switch become off and the value of servo output pin is as below.
(10µA-5µA)*50k*(feedback Resistor/50k)
$03: If FS1 switch is 1, the current supply is cut off and the discharge is performed.
The waveform is as below and the time constant is determined by internal resistor 50K and external Cap.
28
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
0V
Figure 17. Waveform at Pin 3 When FS1 Is Switched from 0 to 1
The waveform of servo output pin according to FS1 and FS2 switches is as below.
$00
02
03
02
03
02
03
00
Figure 18. Focus Search Waveform at Pin 48 by $02 and $03
FS4 is switch for on/off control of focus servo loop
$00: Focus servo off
$08: Focus servo on
Tracking Control ($1X)
This command is used for tracking loop gain control, break circuit and anti-shock on/off control.
D7
D6
D5
D4
D3
D2
D1
D0
ISTAT
0
0
0
1
Anti shock
on/off
Break circuit
on/off
TG2
TG1
Anti shock
TG2 and TG1 are internal switch for tracking gain set.
Tracking mode ($2X)
This command is used for tracking and sled servo on/off and jump for searching track.
D7
D6
D5
D4
0
0
1
0
D3
D2
Tracking control
D1
D0
Sled control
ISTAT
TZC
29
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
<Tracking control & Sled control>
D3
D2
0
0
0
Tracking mode
D1
D0
Sled mode
Tracking servo off
0
0
Sled servo off
1
servo on
0
1
servo on
1
0
Forward jump
1
0
Forward kick
1
1
Reverse jump
1
1
Reverse kick
Peak value set ($3X)
This command is used for the peak value setting of focus search and sled kick.
D0, D1: Sled kick
D2, D3: Focus search peak value
Auto Sequencer command ($4X)
This command is used for reducing control time and replacing several command by one auto- sequence command.
•
Auto sequencer mode is performed from the first falling edge of WDCK clock after the falling of the latch pulse.
•
Auto sequencer does not carry out tracking gain up, brake, anti-shock and focus gain down.
•
MICOM checks ISTAT pin (/BUSY) and sends to $40 command to reset preceding auto sequencer status
Hexa
AS3
AS2
AS1
AS0
Remark
Cancel
$40
0
0
0
0
Reset
Auto focus
$47
0
1
1
1
−
1 Track jump
$48
$49
1
1
0
0
0
0
0
1
Forward
Reverse
10 Track jump
$4A
$4B
1
1
0
0
1
1
0
1
Forward
Reverse
2N track jump
$4C
$4D
1
1
1
1
0
0
0
1
Forward
Reverse
M track move
$4E
$4F
1
1
1
1
1
1
0
1
Forward
Reverse
RAM Set ($5X — $7X)
The value of RAM set is somewhat different to the actual count and the initial value is like below
Item
Blind
Initial value
$55
overflow, Brake
Actual Count Value
Set value +4 — 5 WDCK clock
Set value +3 WDCK clock
Kick
$67
Set value +5 WDCK clock
2N, M Track jump
$7E
Set value +3 WDCK clock
30
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
AUTO ADJUSTMENT COMMAND
This command is used for auto control of offset, balance, gain adjustment and reference voltage setting. This
command is also in control of on/off and sub type of laser diode and test or set mode.
TRACKING BALANCE ($800 — $81F)
Item
Tracking balance
Hexa
Data (5bits)
Initial value
ISTAT (pin31)
TRCNT (pin30)
$800 — $81F
D4 — D0
$81F
BAL
TRCNT
Hexa
Data 5bits)
Initial value
ISTAT (pin31)
TRCNT (pin30)
$820 — $83F
D4 — D0
$820
GAIN
TGL
TRACKING GAIN ($820 — $83F)
Item
Tracking gain
TRACKING BALANCE & GAIN WINDOW LEVEL SETTING
Item
window level setting
Hexa
D3
D2
D1
D0
Initial value
$84X
gain
balance
0
0
$840
NOTE: The tracking balance and gain window level is set by D2,D3 data and the value has two kinds of window levels set
TRACKING BALANCE WINDOW LEVEL
D2 Data
Tracking balance window level
0
1
−10 to +15 mV
−20 to +20 mV
TRACKING GAIN WINDOW LEVEL
D3 Data
Tracking gain window level
0
1
250 to 400 mV
150 to 300 mV
FOCUS LOOP OFFSET ADJUSTMENT START COMMAND ($841, $842)
This command is used for adjusting focus error bias and removing focus servo offset.
It is executed during laser diode off.
Hexa command
meaning
$841
Focus error bias adjustment start command
$842
Focus servo offset cancel adjustment start command
31
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
APC CIRCUIT OPERATION AND INTERRUPTION ON/OFF SETTING CONDITION ($85X)
This command is used for setting of laser diode on/off, sub type (P_sub or N_sub) of laser diode and interruption
countermeasure circuit on/off.
Item
APC &
Interruption on/off
condition
Hexa
D3
D2
$85X
LD on/off
0: On
1: Off
Sub-type
0: N_sub
1: P_sub
D1
D0
Initial value
Interruption ON/OFF
and time setting
$858
Time setting for Interruption countermeasure circuit on/off
D1
D0
Meaning
0
0
Countermeasure circuit on for all mirror signal
0
1
Countermeasure circuit on up to 20kHz mirror signal
1
0
Countermeasure circuit off
1
1
Countermeasure circuit on up to 10kHz mirror signal
FOCUS SERVO OFFSET RESET COMMAND AND SET MODE COMMAND (86X)
This command is used for set and release before focus servo loop offset adjustment and mode change.
Item
Set mode & Focus servo
offset reset command
Hexa
D3
D2
D1
D0
$86X
0: offset release
1: offset reset
option(Pin41 output)
0: Defect
1: SSTOP
1
1
NOTES:
1. The set mode command is sent by MICOM right after tracking gain is tuned.
2. The ISTAT pin is outputted the internal status of $00 ~ $7X command.
DIRECT COMMAND (DIRC) AND FOCUS BIAS RESET COMMAND ($87X)
This command is used for direct 1 track jump on/off setting and focus bias adjustment set and release
Item
DIRC
& focus bias reset
32
Hexa
D3
D2
D1
D0
$87X
0: DIRC On
1:DIRC Off
0: reset
1: reset release
X
X
RF AMP & SERVO SIGNAL PROCESSOR
S1L9223B01
THE EXAMPLE OF ADJUSTMENT FREE ALGORITHM
FOCUS ERROR BIAS & SERVO OFFSET CANCEL ADJUSTMENT
Focus_RF_Offset Adjustment
[Command:841]
Increment Count
no
5bit Counter 17mV/Bit
Tuning range: + 260mV
ISTAT
Check
L--> H
Time Max
100msec
yes
Finish
[RF CNT value Latch]
Focus_Servo_Offset
Adjustment [Command:842]
Increment Count
4bit Counter
40mV/Bit
tuning range : + 280mV
no
ISTAT
Check
L--> H
Time Max
100msec
yes
Finish
[Servo value Latch]
Figure 19. Focus Error Bias & Servo Offset Cancel Adjustment Flow Chart
33
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
TRACKING BALANCE ADJUSTMENT
Balance adjustment Range window
setting + 20mv, + 15mv setting
ISTAT
Check
L--> H
YES
MICOM Balance
5Bit adjustment $800 ~ $81F
Command Up
NO
ISTAT
Check
L--> H
$844
YES
NO
Finish
[RF CNT value Latch
Figure 20. Tracking Balance Adjustment Flow Chart
TRACKING GAIN ADJUSTMENT
Gain adjustment range
setting Command
ISTAT
Check
L--> H
NO
$848
5-bit Gain Adjustment
$820 ~ $83F
Command
YES
Gain adjustment finish
TOC READ
Figure 21. Tracking Gain Adjustment Flow Chart
34
GND
104p
7
VCC
100K 150K
102p
1K
222p
39K
100K
+
391p
120K
120K
47K
+
683p
103p
56K
to KA9258D
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
S1L9223B01
5.6K
150p
27K
+
SL+
from deck
to MOCOM
from MOCOM
from MOCOM
from MOCOM
from MOCOM
333p
103p
from DSP
to MOCOM
to MOCOM
to DSP
MCK 35
VSSA 34
EFM 33
+
104p
ASY 32 0.47uF +
ISTAT 31
LOCK 29
TRCNT 30
FS3 27
FGD 28
FLB 26
SMEF 25
104p
MDATA 36
MLT 37
100K
RESET 38
MIRROR 39
FOK 40
8
331p
5.6K
SL-
WDCK
SLO
VCC
1K
6
FE2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
5
VDDA
3.3uF
4
331p
5.6K
+
ISET
A
65 PD1
3
5.6K
TZC
+
4.7uF
VSSP
B
66 PD2
68 E
67 F
D
22K
C
E
F
2
+
VC GNDVCC
+
69 PD
70 LD
71 VR
78 EQC
1
150p
27K
+
GC1I
72 VCC
74 RFO
73 RF-
to KA9258D
TEO
GC1O
from pick-up
102
+
4pF
472p
76 EQO
75 IRF
SSTOP
SMON
from DSP(SMON)
VREG
from DSP
SMDP
from DSP(SMDP)
77 RFI
47K
15K
10uF
SPDL180K
103p
1uF
to KA9258D
FEO
RRC
4.7uF
79 EI
0.47uF
TE27K
5.6K
CH1I
12K
333p
ATSC
152p
FEGND (POST)
TE2
CH2O
CH1 out
CH1O
CH2 out
CH2I
5.6K
MUTEI
from MICOM
TE1
152p
333p
27K
LPFT
4.7uF
from DSP(SMEF)
104p
DVDD
+
1M 0.47uF
to KA9258D
SPDLO
103p
TDFCT
VCC(POST)
GC2I
GC2O
from DAC CH1
8.2K
222p
FE1
VCC
from DSP(SMSD)
104p
VCCP
from DAC CH2
100uF
10K
10K
FSET
510K
+
104p
FDFCT
DCC1
103p
VCC
to pick-up
+
33uF
TG2
DCC2
22K
TGU
FRSH
4.7uF
DCB
33uF
+
DVEE
80 GND
152p
FEBIAS
MCP
103p
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
APPLICATION CIRCUIT
35
S1L9223B01
RF AMP & SERVO SIGNAL PROCESSOR
PACKAGE DIMENSION
23.90 + 0.30
0-8
20.00 + 0.20
14.00 + 0.20
+ 0.10
- 0.05
0.10 MAX
80-QFP-1420C
0.80 + 0.20
17.90 + 0.30
0.15
#80
#1
0.80
0.35 + 0.10
0.05 MIN
0.15 MAX
(0.80)
2.65 + 0.10
3.00 MAX
0.80 + 0.20
36