PHILIPS SC87C451CCA68

INTEGRATED CIRCUITS
80C451/83C451/87C451
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
DESCRIPTION
80C451/83C451/87C451
PIN CONFIGURATION
The Philips 8XC451 is an I/O expanded single-chip microcontroller
fabricated with Philips high-density CMOS technology. Philips
epitaxial substrate minimizes latch-up sensitivity.
9
1
61
10
The 8XC451 (includes the 80C451, 87C451 and 83C451) is a
functional extension of the 87C51 microcontroller with three
additional I/O ports and four I/O control lines for a total of 68 pins.
Four control lines associated with port 6 facilitate high-speed
asynchronous I/O functions.
60
LCC
26
The 8XC451 includes a 4k × 8 ROM (83C451) EPROM (87C451), a
128 × 8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two
priority level, nested interrupt structure, a serial I/O port for either a
full duplex UART, I/O expansion, or multi-processor
communications, and on-chip oscillator and clock circuits. The
80C451 ROMless version includes all of the 83C451 features except
the on-board 4k × 8 ROM.
44
27
The 87C451 has 4k of EPROM on-chip as program memory and is
otherwise identical to the 83C451.
The 8XC451 has two software selectable modes of reduced activity
for further power reduction; idle mode and power-down mode. Idle
mode freezes the CPU while allowing the RAM, timers, serial port,
and interrupt system to continue functioning. Power-down mode
freezes the oscillator, causing all other chip functions to be
inoperative while maintaining the RAM contents.
FEATURES
• 80C51 based architecture
• Seven 8-bit I/O ports
• Port 6 features:
– Eight data pins
43
Pin
1
2
3
Function
EA/VPP
P2.0/A8
P2.1/A9
Pin
24
25
26
Function
P4.2
P4.1
P4.0
4
5
6
7
P2.2/A10
P2.3/A11
P2.4/A12
P2.5/A13
27
28
29
30
P1.0
P1.1
P1.2
P1.3
50
51
52
53
P5.6
P5.7
XTAL2
XTAL1
8
9
10
11
P2.6/A14
P2.7/A15
P0.7/AD7
P0.6/AD6
31
32
33
34
P1.4
P1.5
P1.6
P1.7
54
55
56
57
VSS
ODS
IDS
BFLAG
12
13
14
15
P0.5/AD5
P0.4/AD4
P0.3/AD3
P0.2/AD2
35
36
37
38
RST
P3.0/RxD
P3.1/TxD
P3.2/INT0
58
59
60
61
AFLAG
P6.0
P6.1
P6.2
16
17
18
19
P0.1/AD1
P0.0/AD0
VCC
P4.7
39
40
41
42
P3.3/INT1
P3.4/T0
P3.5/T1
P3.6/WR
62
63
64
65
P6.3
P6.4
P6.5
P6.6
20
21
22
23
P4.6
P4.5
P4.4
P4.3
43
44
45
46
P3.7/RD
P5.0
P5.1
P5.2
66
67
68
P6.7
PSEN
ALE/PROG
Pin
47
48
49
Function
P5.3
P5.4
P5.5
SU00084A
– Four control pins
– Direct MPU bus interface
– Parallel printer interface
• On the microcontroller:
– 4k × 8 ROM (83C451)
4k × 8 EPROM (87C451)
ROMless version (80C451)
– 128 × 8 RAM
– Two 16-bit counter/timers
– Two external interrupts
• External memory addressing capability
– 64k ROM and 64k RAM
• Low power consumption:
– Normal operation: less than 24mA at 5V, 12MHz
– Idle mode
– Power-down mode
1998 May 01
2
853-0830 19327
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
BLOCK DIAGRAM
P0.0–P0.7
P2.0–P2.7
P4.0–P4.7
P5.0–5.7
PORT 0
DRIVERS
PORT 2
DRIVERS
PORT 4
DRIVERS
PORT 5
DRIVERS
PORT 2
LATCH
PORT 4
LATCH
PORT 5
LATCH
VCC
VSS
RAM ADDR
REGISTER
PORT 0
LATCH
RAM
B
REGISTER
4K x 8
ROM/EPROM
STACK
POINTER
ACC
PROGRAM
ADDRESS
REGISTER
TMP1
TMP2
BUFFER
PCON
ALU
SCON
TMOD
TCON
TH0
TL0
TH1
SBUF
IE
IP
TL1
PSW
PC
INCREMENTER
INTERRUPT, SERIAL
PORT AND TIMER BLOCKS
PSEN
ALE/PROG
EAVPP
TIMING
AND
CONTROL
RST
INSTRUCTION
REGISTER
PROGRAM
COUNTER
PD
DPTR
PORT 1
LATCH
PORT 6
LATCH
PORT 1
DRIVERS
PORT 6
DRIVERS
PORT 6
CONTROL/STATUS
PORT 3
DRIVERS
P1.0–P1.7
P6.0–P6.7
IDS ODS
BFLAG
AFLAG
P3.0–P3.7
PORT 3
LATCH
OSCILLATOR
XTAL1
XTAL2
SU00086
1998 May 01
3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
ORDERING INFORMATION
TEMPERATURE RANGE °C
AND PACKAGE
FREQ
MHz
DRAWING
NUMBER
OTP
0 to +70, Plastic Leaded Chip Carrier,
3.5 to 12
SOT188-3
OTP
0 to +70, Plastic Leaded Chip Carrier
3.5 to 16
SOT188-3
EPROM1
ROMless
ROM
SC80C451CCA68
SC83C451CCA68
SC87C451CCA68
SC80C451CGA68
SC83C451CGA68
SC87C451CGA68
NOTE:
1. OTP = One Time Programmable
LOGIC SYMBOL
VCC
VSS
PORT 0
XTAL1
ADDRESS AND
DATA BUS
PORT 6 CONTROL
ODS
IDS
BFLAG
AFLAG
PORT 1
PORT 2
PORT 4
ADDRESS BUS
PORT 5
RxD
TxD
INT0
INT1
T0
T1
WR
RD
PORT 3
RST
EA/VPP
PSEN
ALE/PROG
PORT 6
SECONDARY FUNCTIONS
XTAL2
SU00085
1998 May 01
4
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
PIN DESCRIPTION
PIN
NO.
TYPE
VSS
54
I
Ground: 0V reference.
VCC
18
I
Power Supply: This is the power supply voltage for normal, idle, and power-down operation.
P0.0–0.7
17-10
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order
address bus during accesses to external memory. External pull-ups are required during program
verification. Port 0 can sink/source eight LS TTL inputs.
P1.0–P1.7
27-34
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order
address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and
drive CMOS inputs without external pull-ups.
P2.0–P2.7
2-9
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address
bytes during access to external memory and receives the high-order address bits and control signals
during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without
external pull-ups.
P3.0–P3.7
36-43
I/O
36
37
38
39
40
41
42
43
I
O
I
I
I
I
O
O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS
TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions
listed below:
RxD (P3.0): Serial input port
TxD (P3.1): Serial output port
INT0 (P3.2): External interrupt
INT1 (P3.3): External interrupt
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
P4.0–P4.7
26-19
I/O
Port 4: Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
P5.0–P5.7
44-51
I/O
Port 5: Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups.
P6.0–P6.7
59-66
I/O
Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can
sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in
a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that
serve the functions listed below:
ODS
55
I
ODS: Output data strobe
IDS
56
I
IDS: Input data strobe
BFLAG
57
I/O
BFLAG: Bidirectional I/O pin with internal pull-ups
AFLAG
58
I/O
AFLAG: Bidirectional I/O pin with internal pull-ups
RST
35
I
Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An
internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC.
ALE/PROG
68
I/O
Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during
an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except
during an external data memory access, at which time one ALE is skipped. ALE can sink/source three
LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse
during EPROM programming.
PSEN
67
O
Program Store Enable: The read strobe to external program memory. PSEN is activated twice each
machine cycle during fetches from external program memory. However, when executing out of external
program memory, two activations of PSEN are skipped during each access to external program
memory. PSEN is not activated during fetches from internal program memory. PSEN can sink/source
eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low
during programming.
EA/VPP
1
I
Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU
executes out of internal program memory, unless the program counter exceeds 0FFFH. When EA is
held low, the CPU executes out of external program memory. EA must never be allowed to float. This
pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming.
XTAL1
53
I
Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the
external oscillator when an external oscillator is used.
XTAL2
52
O
Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when
an external oscillator is used.
MNEMONIC
1998 May 01
NAME AND FUNCTION
5
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
I/O Port Structure
Processor Bus Interface
The 8XC451 has a total of seven parallel I/O ports. The first four
ports, P0 through P3, are identical in function to those present on
the 80C51 family. The added ports 4 and 5 are identical in function
to port 1; that is, they are standard quasi-bidirectional ports with no
alternate functions and the standard output drive characteristics.
Port 6 is a specialized 8-bit bidirectional I/O port with internal
pullups.
Port 6 allows the use of an 8XC451 as an element on a
microprocessor type bus. The host processor could be a general
purpose MPU or the data bus of a microcontroller like the 8XC451
itself. Setting up the 8XC451 as a processor bus interface allows
single or multiple microcontrollers to be used on a bus as flexible
peripheral processing elements. Applications can include: keyboard
scanners, serial I/O controllers, servo controllers, etc.
Ports 4 and 5
On reset, port 6 is programmed correctly (that is, Special Function
registers CSR and P6) for use as a bus interface. This prevents the
interface from disrupting data on the bus of a host processor during
power-up.
Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4
is an 8-bit port. Port 4 and port 5 pins with ones written to them, are
pulled high by the internal pull-ups, and in that state can be used as
inputs. Port 4 and 5 are addressed at the special function register
addresses shown in Table 1.
Standard Quasi-bidirectional I/O Port
To use port 6 as a common I/O port, all of the control pins should be
tied to ground. On hardware reset, bits 2-7 of the CSR are set to
one. With the control pins grounded, the port’s operation and
electrical characteristics will be identical to port 1 on the 80C51. No
further software initialization is required.
Port 6
Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups
(see Figure 1). This special port can sink/source three LS TTL
inputs and drive CMOS inputs without external pullups. The flexibility
of this port facilitates high-speed parallel data communications. This
port can be used as a standard I/O port, or in strobed modes of
operation in conjunction with four special control lines: ODS, IDS,
AFLAG, and BFLAG. Port 6 operating modes are controlled by the
port 6 control status register (CSR). Port 6 and the CSR are
addressed at the special function register addresses shown in Table
1. The following four control pins are used in conjunction with port 6:
Parallel Printer Port
The 8XC451 has the capacity to permit all of the intelligent features
of a common printer to be handled by a single chip. The features of
port 6 allow a parallel port to be designed with only line driving and
receiving chips required as additional hardware. The onboard UART
allows RS232 interfacing with only level shifting chips added. The
8-bit parallel ports 0 to 6 are ample to drive onboard control
functions, even when ports are used for external memory access,
interrupts, and other functions. The RAM addressing ability of ports
0 to 2 can be used to address up to 64k bytes of a hardware
buffer/spooler.
ODS – Output data strobe (Active Low) for port 6. ODS can be
programmed to control the port 6 output drivers and the output
buffer full flag (OBF), or to clear only the OBF flag bit in the CSR
(output-always mode). ODS is active low for output driver control.
the OBF flag can be programmed to be cleared on the negative or
positive edge of ODS.
In addition, either end of a parallel interface can be implemented
using port 6, and the interfaces can be interrupt driven or polled in
either case. For more detailed information on port 6 usage, refer to
the application notes entitled “80C451 Operation of Port 6” and
“256k Centronics Printer Buffer Using the SC87C451
Microcontroller.”
IDS – Input data strobe (Active Low) for port 6. IDS is used to
control the port 6 input latch and input buffer full flag (IBF) bit in the
CSR. The input data latch can be programmed to be transparent
when IDS is low and latched on the positive transition of IDS, or to
latch only on the positive transition of IDS. Correspondingly, the IBF
flag is set on the negative or positive transition of IDS.
CONTROL STATUS REGISTER
The control status register (CSR) establishes the mode of operation
for port 6 and indicates the current status of port 6 I/O registers. All
control status register bits can be read and written by the CPU,
except bits 0 and 1, which are read only. Reset writes ones to bits 2
through 7, and writes zeros to bits 0 and 1 (see Table 3).
BFLAG – BFLAG is a bidirectional I/O pin which can be
programmed to be an output, set high or low under program control,
or to output the state of the input buffer full flag. BFLAG can also be
programmed to input an enable signal for port 6. When BFLAG is
used as an enable input, port 6 output drivers are in the
high-impedance state, and the input latch does not respond to the
IDS strobe when BFLAG is high. Both features are enabled when
BFLAG is low. This feature facilitates the use of the SC8XC451 in
bused multiprocessor systems.
CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is
set to a logic 1 when port 6 data is loaded into the input buffer under
control of IDS. This can occur on the negative or positive edge of
IDS, as determined by CSR.2 IBF is cleared when the CPU reads
the input buffer register.
AFLAG – AFLAG is a bidirectional I/O pin which can be
programmed to be an output set high or low under program control,
or to output the state of the output buffer full flag. AFLAG can also
be programmed to be an input which selects whether the contents of
the output buffer, or the contents of the port 6 control status register
will output on port 6. This feature grants complete port 6 status to
external devices.
CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag
is set to a logic 1 when the CPU writes to the port 6 output data
buffer. OBF is cleared by the positive or negative edge of ODS, as
determined by CSR.3.
CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high
transition on the IDS pin sets the IBF flag. The Port 6 input buffer is
loaded on the IDS positive edge. When CSR.2 = 1, a high-to-low
transition on the IDS pin sets the IBF flag. Port 6 input buffer is
transparent when IDS is low, and latched when IDS is high.
Port 6 can be used in a number of different ways to facilitate data
communication. It can be used as a processor bus interface, as a
standard quasi-bidirectional I/O port, or as a parallel printer port
(either polled or interrupt driven).
1998 May 01
6
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When
CSR.3 = 1, the positive edge of the ODS input clears the OBF flag.
When CSR.3 = 0, the negative edge of the ODS input clears the
OBF flag.
CSR.6, CSR.7 BFLAG Mode Select
(MB0, MB1) – Bits 6 and 7 select the mode operation as follows:
MB1 MB0
0
0
0
1
1
0
1
1
CSR.4, CSR.5 AFLAG Mode Select
(MA0, MA1) – Bits 4 and 5 select the mode of operation for the
AFLAG pin as follows:
MA1
0
0
1
1
MA0
0
1
0
1
80C451/83C451/87C451
BFLAG Function
Logic 0 output
Logic 1 output
IBF flag output (CSR.0)
Port enable (PE)
In the port enable mode, IDS and ODS inputs are disabled when
BFLAG input is high. When the BFLAG input is low, the port is
enabled for I/O.
AFLAG Function
Logic 0 output
Logic 1 output
OBF flag output (CSR.1)
Select (SEL) input mode
SPECIAL FUNCTION REGISTER ADDRESSES
The SFRs are identical to those of the standard 80C51 with the
exception of four registers that have been added to allow control of
the three additional I/O ports P4, P5, and P6. The additional
registers are P4, P5, P6, and CSR. Registers P4, P5, and P6
function as port latches for ports 4, 5, and 6, respectively. These
registers operate identically to those for ports 0 through 3 of the
80C51.
The select (SEL) input mode is used to determine whether the port 6
data register or the control status register is output on port 6. When
the select feature is enabled, the AFLAG input controls the source of
port 6 output data. A logic 0 on AFLAG input selects the port 6 data
register, and a logic 1 on AFLAG input selects the control status
register.
Table 1. Special Function Register Addresses
REGISTER ADDRESS
NAME
Port 4
Port 5
Port 6 data
Port 6 control status
AFLAG
ADDRESS
P4
P5
P6
CSR
C0
C8
D8
E8
MSB
C7
CF
DF
EF
PORT 6
BFLAG ODS
BFLAG/ODS
MODE
(CSR.6/.7)
AFLAG
MODE
(CSR.4/.5)
BIT ADDRESS
SYMBOL
LSB
C6
CE
DE
EE
C5
CD
DD
ED
C4
CC
DC
EC
IDS
INPUT
BUFFER
(P6 READ)
OUTPUT
DRIVERS
IDS
MODE
INPUT BUFFER
FULL (CSR.0)
EDGE/LEVEL
SELECT (CSR.2)
MUX
OUTPUT BUFFER
FULL (CSR.1)
CONTROL/STATUS
REGISTER (CSR)
OUTPUT BUFFER
(P6 WRITE)
INTERNAL BUS
SU00087
Figure 1. Port 6 Block Diagram
1998 May 01
7
C3
CB
DB
EB
C2
CA
DA
EA
C1
C9
D9
E9
C0
C8
D8
E8
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
Table 2.
SYMBOL
80C451/83C451/87C451
8XC451 Special Function Registers
DESCRIPTION
DIRECT
ADDRESS
BIT NAMES AND ADDRESSES
MSB
LSB
RESET
VALUE
ACC*
Accumulator
E0H
E7
E6
E5
E4
E3
E2
E1
E0
00H
B*
B register
F0H
F7
F6
F5
F4
F3
F2
F1
F0
00H
EF
EE
ED
EC
EB
EA
E9
E8
MB1
MB0
MA1
MA0
OBFC
IDSM
OBF
IBF
CSR*#
Port 6 command/status
DPTR
Data pointer (2 bytes)
E8H
DPH
Data pointer high
83H
DPL
Data pointer low
82H
IP*
Interrupt priority
FCH
00H
00H
BF
BE
BD
BC
BB
BA
B9
B8
–
–
–
PS
PT1
PX1
PT0
PX0
AF
AE
AD
AC
AB
AA
A9
A8
B8H
xxx00000B
IE*
Interrupt enable
A8H
EA
–
–
ES
ET1
EX1
ET0
EX0
P0*
Port 0
80H
87
B6
85
84
83
82
81
80
FFH
P1*
Port 1
90H
97
96
95
94
93
92
91
90
FFH
P2*
Port 2
A0H
A7
A6
A5
A4
A3
A2
A1
A0
FFH
P3*
Port 3
B0H
B7
B6
B5
B4
B3
B2
B1
B0
FFH
P4*#
Port 4
C0H
C7
C6
C5
C4
C3
C2
C1
C0
FFH
P5*#
Port 5
C8H
CF
CE
CD
CC
CB
CA
C9
C8
FFH
P6*#
Port 6
D8H
DF
DE
DD
DC
DB
DA
D9
D8
FFH
PCON
Power control
87H
SMOD
–
–
–
GF1
GF0
PD
IDL
0xxx0000B
D7
D6
D5
D4
D3
D2
D1
D0
CY
AC
F0
RS1
RS0
OV
–
P
PSW*
Program status word
D0H
SBUF
Serial data buffer
99H
SCON*
Serial port control
98H
SP
Stack pointer
81H
0xx00000B
00H
xxxxxxxxB
9F
9E
9D
9C
9B
9A
99
98
SM0
SM1
SM2
REN
TB8
RB8
TI
RI
00H
07H
8F
8E
8D
8C
8B
8A
89
88
88H
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
00H
GATE
C/T
M1
M0
GATE
C/T
M1
M0
00H
TCON*
Timer/counter control
TMOD
Timer/counter mode
89H
TH0
Timer 0 high byte
8CH
00H
TH1
Timer 1 high byte
8DH
00H
TL0
Timer 0 low byte
8AH
00H
TL1
Timer 1 low byte
8BH
00H
* SFRs are bit addressable.
# SFRs are modified from or added to the 80C51 SFRs.
1998 May 01
8
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Table 3. Control Status Register (CSR)
Bit 7
Bit 6
Bit 5
Bit 4
MB1
MB0
MA1
MA0
Bit 3
Bit 2
Bit 1
Bit 0
OBFC
IDSM
OBF
IBF
BFLAG Mode Select
AFLAG Mode Select
Output Buffer
Flag Clear
Mode
Input Data
Strobe Mode
Output Buffer
Flag Full
Input Buffer
Flag Full
0/0 = Logic 0 output*
0/1 = Logic 1 output*
1/0 = IBF output
1/1 = PE input
(0 = Select)
(1 = Disable I/O)
0/0 = Logic 0 output*
0/1 = Logic 1 output*
1/0 = OBF output
1/1 = SEL input
(0 = Select)
(1 = Control/status)
0 = Negative
edge of ODS
1 = Positive
edge o ODS
0 = Positive
edge of IDS
1 = Low level
of IDS
0 = Output
data buffer
empty
1 = Output
data buffer full
0 = Input data
buffer empty
1 = Input data
buffer full
NOTE:
* Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS only clears the OBF flag.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
RATING
UNIT
0 to +70
°C
Storage temperature range
–65 to +150
°C
Voltage on any other pin to VSS
–0.5 to +6.5
V
1.5
W
PARAMETER
Operating temperature under bias
Power dissipation (based on package heat transfer limitations, not device power consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.
1998 May 01
9
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
DC ELECTRICAL CHARACTERISTICS1
Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)
TEST
SYMBOL
PARAMETER
VIL
Input low voltage; except EA
VIL1
Input low voltage to EA
VIH
Input high voltage; except XTAL1, RST
VIH1
Input high voltage; XTAL1, RST
VOL
Output low voltage; ports 1, 2, 3, 4, 5, 6
CONDITIONS
IOL =
1.6mA2
3.2mA2
LIMITS
MIN
TYPICAL1
MAX
UNIT
–0.5
0.2VCC–0.1
V
0
0.2VCC–0.3
V
0.2VCC+0.9
VCC+0.5
V
0.7VCC
VCC+0.5
V
0.45
V
0.45
V
VOL1
Output low voltage; port 0, ALE, PSEN
IOL =
VOH
Output high voltage; ports 1, 2, 3, 4, 5, 6
IOH = –60µA,
IOH = –25µA
IOH = –10µA
2.4
0.75VCC
0.9VCC
V
V
V
VOH1
Output high voltage (port 0 in external bus mode, ALE,
PSEN)3
IOH = –800µA,
IOH = –300µA
IOH = –80µA
2.4
0.75VCC
0.9VCC
V
V
V
IIL
Logical 0 input current,; ports 1, 2, 3, 4, 5, 6
VIN = 0.45V
–50
µA
ITL
Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6
See note 4
–650
µA
ILI
Input leakage current; port 0
VIN = VIL or VIH
+10
µA
ICC
Power supply current:
Active mode @ 12MHz5
Idle mode @ 12MHz5
Power down mode
25
4
50
mA
mA
µA
300
kΩ
10
pF
RRST
CIO
See note 6
11.5
1.3
3
Internal reset pull-down resistor
Pin
50
capacitance7
NOTES:
1. Typical ratings are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are
at room temperature, 5V.
2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the
address bits are stabilizing.
4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when VIN is approximately 2V.
5. ICCMAX at other frequencies is given by:
Active mode: ICCMAX = 0.94 X FREQ + 13.71
Idle mode: ICCMAX = 0.14 X FREQ +2.31
where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 13.
6. See Figures 14 through 17 for ICC test conditions.
7. CIO applies to ports 1 through 6, AFLAG, BFLAG, XTAL1, XTAL2.
1998 May 01
10
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
AC ELECTRICAL CHARACTERISTICS1
Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)2
12MHz CLOCK
SYMBOL
FIGURE
1/tCLCL
PARAMETER
Oscillator frequency:
SC8XC451
SC8XC451
MIN
MAX
Speed Versions
C
G
VARIABLE CLOCK
MIN
MAX
UNIT
3.5
3.5
12
16
MHz
MHz
tLHLL
2
ALE pulse width
127
2tCLCL–40
ns
tAVLL
2
Address valid to ALE low
28
tCLCL–55
ns
tLLAX
2
Address hold after ALE low
48
tCLCL–35
ns
tLLIV
2
ALE low to valid instruction in
tLLPL
2
ALE low to PSEN low
43
tCLCL–40
ns
tPLPH
2
PSEN pulse width
205
3tCLCL–45
ns
tPLIV
2
PSEN low to valid instruction in
tPXIX
2
Input instruction hold after PSEN
tPXIZ
2
Input instruction float after PSEN
59
tCLCL–25
ns
tAVIV
2
Address to valid instruction in
312
5tCLCL–105
ns
tPLAZ
2
PSEN low to address float
10
10
ns
234
4tCLCL–100
145
0
3tCLCL–105
0
ns
ns
ns
Data Memory
tRLRH
3, 4
RD pulse width
400
6tCLCL–100
ns
tWLWH
3, 4
WR pulse width
400
6tCLCL–100
ns
tRLDV
3, 4
RD low to valid data in
tRHDX
3, 4
Data hold after RD
tRHDZ
3, 4
Data float after RD
97
2tCLCL–70
ns
tLLDV
3, 4
ALE low to valid data in
517
8tCLCL–150
ns
tAVDV
3, 4
Address to valid data in
585
9tCLCL–165
ns
tLLWL
3, 4
ALE low to RD or WR low
200
3tCLCL+50
ns
tAVWL
3, 4
Address valid to WR low or RD low
203
4tCLCL–130
ns
tQVWX
3, 4
Data valid to WR transition
23
tCLCL–60
ns
tWHQX
3, 4
Data hold after WR
33
tCLCL–50
ns
tRLAZ
3, 4
RD low to address float
tWHLH
3, 4
RD or WR high to ALE high
43
tXLXL
5
Serial port clock cycle time
1.0
12tCLCL
µs
tQVXH
5
Output data setup to clock rising edge
700
10tCLCL–133
ns
tXHQX
5
Output data hold after clock rising edge
50
2tCLCL–117
ns
tXHDX
5
Input data hold after clock rising edge
0
0
ns
tXHDV
5
Clock rising edge to input data valid
252
0
5tCLCL–165
0
300
3tCLCL–50
0
123
tCLCL–40
ns
ns
0
ns
tCLCL+40
ns
Shift Register
700
NOTES: SEE NEXT PAGE
1998 May 01
11
10tCLCL–133
ns
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
AC ELECTRICAL CHARACTERISTICS1 (continued)
Tamb = 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)2
12MHz CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
VARIABLE CLOCK
MAX
MIN
MAX
UNIT
Port 6 input (input rise and fall times = 5ns)
tFLFH
8
PE width
270
3tCLCL+20
ns
tILIH
8
IDS width
270
3tCLCL+20
ns
tDVIH
8
Data setup to IDS high or PE high
0
0
ns
tIHDX
8
Data hold after IDS high or PE high
30
30
ns
tIVFV
9
IDS to BFLAG (IBF) delay
tOLOH
6
ODS width
tFVDV
7
SEL to data out delay
85
85
ns
tOLDV
6
ODS to data out delay
80
80
ns
tOHDZ
6
ODS to data float delay
35
35
ns
tOVFV
6
ODS to AFLAG (OBF) delay
100
100
ns
tFLDV
6
PE to data out delay
120
120
ns
tOHFH
7
ODS to AFLAG (SEL) delay
100
100
ns
tCHCX
10
High time
20
20
ns
tCLCX
10
Low time
20
20
ns
tCLCH
10
Rise time
20
20
ns
tCHCL
10
Fall time
20
20
ns
130
130
ns
Port 6 output
270
3tCLCL+20
ns
External Clock
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
1998 May 01
12
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
EXPLANATION OF THE AC SYMBOLS
P – PSEN
Q – Output data
R – RD signal
t – Time
V – Valid
W – WR signal
X – No longer a valid logic level
Z – Float
Examples: tAVLL = Time for address valid to ALE low.
tLLPL = Time for ALE low to PSEN low.
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
tLHLL
ALE
tAVLL
tLLPL
tPLPH
tLLIV
tPLIV
PSEN
tLLAX
A0–A7
PORT 0
tPXIZ
tPLAZ
tPXIX
A0–A7
INSTR IN
tAVIV
PORT 2
A0–A15
A8–A15
SU00006
Figure 2. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV
tLLWL
tRLRH
RD
tAVLL
tLLAX
tRLAZ
PORT 0
tRHDZ
tRLDV
tRHDX
A0–A7
FROM RI OR DPL
DATA IN
A0–A7 FROM PCL
INSTR IN
tAVWL
tAVDV
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00007
Figure 3. External Data Memory Read Cycle
1998 May 01
13
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
ALE
tWHLH
PSEN
tWLWH
tLLWL
WR
tLLAX
tAVLL
A0–A7
FROM RI OR DPL
PORT 0
tWHQX
tQVWX
DATA OUT
A0–A7 FROM PCL
INSTR IN
tAVWL
PORT 2
P2.0–P2.7 OR A8–A15 FROM DPH
A0–A15 FROM PCH
SU00008
Figure 4. External Data Memory Write Cycle
INSTRUCTION
0
1
2
3
4
5
6
7
8
ALE
tXLXL
CLOCK
tXHQX
tQVXH
OUTPUT DATA
0
1
WRITE TO SBUF
2
3
4
5
6
7
tXHDX
tXHDV
SET TI
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
CLEAR RI
SET RI
SU00027
Figure 5. Shift Register Mode Timing
1998 May 01
14
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
OBF (AFLAG)
tOVFV
tOVFV
PE (BFLAG)
tOLOH
ODS
tOLDV
tOHDZ
PORT 6
tFLDV
SU00088
Figure 6. Port 6 Output
ODS
tOHFH
SEL (AFLAG)
tFVDV
PORT 6
DATA
tFVDV
CSR
DATA
SU00089
Figure 7. Port 6 Select Mode
tFLFH
PE (BFLAG)
tILIH
IDS
tDVIH
tIHDZ
PORT 6
SU00090
Figure 8. Port 6 Input
IBF (BFLAG)
tIVFV
tIVFV
IDS
SU00091A
Figure 9. IBF Flag Output
1998 May 01
15
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
VCC–0.5
80C451/83C451/87C451
0.7VCC
0.2VCC–0.1
0.45V
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 10. External Clock Drive
VCC–0.5
0.2VCC+0.9
0.2VCC–0.1
0.45V
NOTE:
AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.
SU00010
Figure 11. AC Testing Input/Output
VLOAD+0.1V
VOH–0.1V
TIMING
REFERENCE
POINTS
VLOAD
VLOAD–0.1V
VOL+0.1V
NOTE:
For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs,
and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL ≥ ±20mA.
SU00011
Figure 12. Float Waveform
30
MAX ACTIVE MODE
25
20
ICC mA
TYP ACTIVE MODE
15
10
5
MAX IDLE MODE
TYP IDLE MODE
4MHz
8MHz
12MHz
16MHz
FREQ AT XTAL1
VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST.
SU00092
Figure 13. ICC vs. FREQ
1998 May 01
16
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
VCC
VCC
ICC
ICC
VCC
VCC
VCC
VCC
RST
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
VCC
RST
P0
P0
EA
EA
VCC
(NC)
XTAL2
CLOCK SIGNAL
XTAL1
VCC
IDS
VSS
VSS
ODS
IDS
ODS
SU00093
SU00094
Figure 14. ICC Test Condition, Active Mode
All other pins are disconnected
VCC–0.5
0.45V
Figure 15. ICC Test Condition, Idle Mode
All other pins are disconnected
0.7VCC
0.2VCC–0.1
tCHCL
tCHCX
tCLCH
tCLCX
tCLCL
SU00009
Figure 16. Clock Signal Waveform for ICC Tests in Active and Idle Modes
tCLCH = tCHCL = 5ns
VCC
ICC
VCC
RST
VCC
P0
EA
(NC)
XTAL2
VCC
XTAL1
VSS
IDS
ODS
SU00095
Figure 17. ICC Test Condition, Power Down Mode
All other pins are disconnected. VCC = 2V to 5.5V
1998 May 01
17
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
EPROM CHARACTERISTICS
The 87C451 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for VPP (programming supply voltage) and in the width and
number of the ALE/PROG pulses.
Note that the EA/VPP pin must not be allowed to go above the
maximum specified VPP level for any amount of time. Even a narrow
glitch above that voltage can cause permanent damage to the
device. The VPP source should be well regulated and free of glitches
and overshoot.
The 87C451 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C451 manufactured by
Philips Semiconductors.
Program Verification
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be read is applied to ports 1 and 2 as shown in
Figure 20. The other pins are held at the ‘Verify Code Data’ levels
indicated in Table 4. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.
Table 4 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 18 and 19. Figure 20 shows the
circuit configuration for normal program memory verification.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 18. Note that the 87C451 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 18. The code byte to be
programmed into that location is applied to port 0. RST, PSEN and
pins of ports 2 and 3 specified in Table 4 are held at the ‘Program
Code Data’ levels indicated in Table 4. The ALE/PROG is pulsed
low 25 times as shown in Figure 19.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips
(031H) = 90H indicates 87C451
To program the encryption table, repeat the 25 pulse programming
sequence for addresses 0 through 1FH, using the ‘Pgm Encryption
Table’ levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 4, and
which satisfies the timing specifications, is suitable.
To program the lock bits, repeat the 25 pulse programming
sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is
Table 4. EPROM Programming Modes
MODE
RST
PSEN
ALE/PROG
EA/VPP
P2.7
P2.6
P3.7
P3.6
Read signature
1
0
Program code data
1
0
1
1
0
0
0
0
0*
VPP
1
0
1
1
Verify code data
1
0
Pgm encryption table
1
0
1
1
0
0
1
1
0*
VPP
1
0
1
0
Pgm lock bit 1
1
0
0*
VPP
1
1
1
1
Pgm lock bit 2
1
0
0*
VPP
1
1
0
0
NOTES:
1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.
2. VPP = 12.75V ±0.25V.
3. VCC = 5V ±10% during programming and verification.
* ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100µs (±10µs) and high for a
minimum of 10µs.
Trademark phrase of Intel Corporation.
1998 May 01
18
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
+5V
VCC
A0–A7
P0
P1
1
RST
EA/VPP
1
P3.6
ALE/PROG
1
P3.7
87C451
XTAL2
4–6MHz
XTAL1
PGM DATA
+12.75V
25 100µs PULSES TO GROUND
PSEN
0
P2.7
1
P2.6
0
A8–A12
P2.0–P2.4
VSS
SU00096
Figure 18. Programming Configuration
25 PULSES
1
ALE/PROG:
0
10µs MIN
1
ALE/PROG:
100µs+10
0
SU00018
Figure 19. PROG Waveform
+5V
VCC
A0–A7
P0
P1
PGM DATA
1
RST
EA/VPP
1
1
P3.6
ALE/PROG
1
1
P3.7
PSEN
0
87C451
XTAL2
4–6MHz
XTAL1
P2.7
0 ENABLE
P2.6
0
P2.0–P2.4
A8–A12
VSS
SU00097
Figure 20. Program Verification
1998 May 01
19
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 21)
SYMBOL
PARAMETER
MIN
MAX
UNIT
12.5
13.0
V
VPP
Programming supply voltage
IPP
Programming supply current
1/tCLCL
Oscillator frequency
tAVGL
Address setup to PROG low
48tCLCL
tGHAX
Address hold after PROG
48tCLCL
tDVGL
Data setup to PROG low
48tCLCL
tGHDX
Data hold after PROG
48tCLCL
tEHSH
P2.7 (ENABLE) high to VPP
48tCLCL
tSHGL
VPP setup to PROG low
10
µs
tGHSL
VPP hold after PROG
10
µs
tGLGH
PROG width
90
tAVQV
Address to data valid
48tCLCL
tELQZ
ENABLE low to data valid
48tCLCL
tEHQZ
Data float after ENABLE
0
tGHGL
PROG high to PROG low
10
4
mA
6
MHz
110
µs
48tCLCL
µs
PROGRAMMING*
VERIFICATION*
ADDRESS
ADDRESS
P1.0–P1.7
P2.0–P2.4
50
tAVQV
DATA IN
PORT 0
DATA OUT
tDVGL
tAVGL
tGHDX
tGHAX
ALE/PROG
tGLGH
tSHGL
tGHGL
tGHSL
LOGIC 1
LOGIC 1
EA/VPP
LOGIC 0
tEHSH
tELQV
tEHQZ
P2.7
ENABLE
SU00020
NOTE:
* FOR PROGRAMMING VERIFICATION SEE FIGURE 18.
FOR VERIFICATION CONDITIONS SEE FIGURE 20.
Figure 21. EPROM Programming and Verification
1998 May 01
20
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
PLCC68: plastic leaded chip carrier; 68 leads; pedestal
1998 May 01
21
80C451/83C451/87C451
SOT188-3
Philips Semiconductors
Product specification
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
80C451/83C451/87C451
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Date of release: 05-98
Document order number:
1998 May 01
22
9397 75003857