S i 5 3 11 PRELIMINARY DATA SHEET P RECISION H IGH S PEED C LOCK M ULTIPLIER /R EGENERATOR IC Features Complete precision high speed clock multiplier and regenerator device: ! ! ! Performs Clock Multiplication to One of Four Frequency Ranges: 150–167 MHz, 600–668 MHz, 1.2–1.33 GHz, or 2.4–2.67 GHz Jitter Generation as low as 0.5 psRMS for 622 MHz Output ! Accepts Input Clock from 9.4–668 MHz ! ! ! Regenerates a “Clean”, JitterAttenuated Version of Input Clock DSPLL™ Technology Provides Superior Jitter Performance Small Footprint: 4 mm x 4 mm Low Power: 310 mW typical Ordering Information: See page 22. Applications 20 19 18 VDD 2 GND 3 REFCLK+ 4 REFCLK– 5 MULTOUT– MULTOUT+ 17 16 15 PWRDN/CAL 14 VDD GND Pad 13 CLKOUT+ 12 CLKOUT– 11 VDD 6 7 8 9 CLKIN+ 1 GND The Si5311 is a fully integrated high-speed clock multiplier and clock regenerator IC. The clock multiplier generates an output clock that is an integer multiple of the input clock. When the clock multiplier is operating in either the 150–167 MHz range or the 600–668 MHz range, the clock regenerator operates simultaneously. The clock regenerator creates a “clean” version of the input clock by using the clock synthesis phaselocked loop (PLL) to remove unwanted jitter and square up the input clock’s rising and falling edges. The Si5311 uses Silicon Laboratories patented DSPLL™ architecture to achieve superior jitter performance while eliminating the analog loop filter found in traditional PLL designs. REXT Top View 10 CLKIN– Description GND ! Si5311 MULTSEL0 ! Pin Assignments Optical Transceiver Modules Gigabit Ethernet Systems Hybrid VCO Modules MULTSEL1 ! ! VDD ! SONET/SDH Systems Terabit Routers Digital Cross Connects LOL ! The Si5311 represents a new standard in low jitter, small size, low power, and ease-of-use for high speed clock devices. It operates from a single 2.5 V supply over the industrial temperature range (–40°C to 85°C). Functional Block Diagram R e ge ne ratio n BUF 2 C a libra tion C L K IN + C L K IN – 2 BUF D S P L L TM P h a se -L o cke d Loop C L K O U T+ C L K O U T– P W R D N /C A L BUF 2 M U L TO U T+ M U L TO U T – LOL 2 RE FCLK+ RE FCLK– Preliminary Rev. 0.6 6/01 B ia s G en 2 M U L TS E L1–0 REXT Copyright © 2001 by Silicon Laboratories Si5311-DS06 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5311 2 Preliminary Rev. 0.6 Si5311 TA B L E O F C O N T E N T S Section Page Detailed Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLL™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1x Multiplication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock Regeneration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLL Lock Detection (Loss-of-Lock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLL Self-Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si5311 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Preliminary Rev. 0.6 4 5 14 16 16 16 16 16 16 17 18 18 18 18 18 18 20 22 23 24 3 Si5311 Detailed Block Diagram CLKOUT+ Regen Retime CLKOUT– c CLKIN+ CLKIN– Phase Detector A/D VCO DSP CLK Divider n REFCLK+ Lock Detector REFCLK– MULTOUT+ c MULTOUT– LOL 2 MULTSEL 1- 0 / REXT Calibration Bias Generation Figure 1. Detailed Block Diagram 4 Preliminary Rev. 0.6 PWRDN/CAL Si5311 Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Min1 Typ Max1 Unit TA –40 25 85 °C VDD 2.375 2.5 2.625 V Ambient Temperature Si5311 Supply Voltage2 Test Condition Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25°C unless otherwise stated. 2. The Si5311 specifications are guaranteed when using the recommended application circuit (including component tolerance) of Figure 5 on page 13. V SIGNAL + Differential V ICM , V O CM SIGNAL – I/Os V IS (SIGNAL +) – (SIGNAL –) Differential Peak-to-Peak Voltage V ID ,V O D Differential Voltage Swing t Figure 2. Differential Voltage Measurement (CLKIN, REFCLK, CLKOUT, MULTOUT) CLKIN 1/f MULT MULTOUT t CI-M t M-CO CLKOUT Figure 3. CLKIN to CLKOUT, MULTOUT Phase Relationship CLKIN, REFCLK, CLKOUT, MULTOUT 80% 20% tF tR Figure 4. Clock Input and Output Rise/Fall Times Preliminary Rev. 0.6 5 Si5311 Table 2. DC Characteristics, VDD = 2.5 V (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Symbol Supply Current MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 IDD Power Dissipation MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 PD Common Mode Input Voltage (CLKIN, REFCLK) Test Condition Min Typ Max Unit — — — — 108 113 117 124 118 123 127 134 mA — — — — 270 283 293 310 310 323 333 352 mW VICM See Figure 2 — .80 VDD — V Input Voltage Range* (CLKIN+, CLKIN–, REFCLK+, REFCLK–) VIS See Figure 2 — — 750 mV Differential Input Voltage Swing* (CLKIN, REFCLK) VID See Figure 2 200 — 1500 mV (pk-pk) Input Impedance (CLKIN, REFCLK) RIN Line-to-Line 84 100 116 Ω Differential Output Voltage Swing (CLKOUT) VOD 100 Ω Load Line-to-Line TBD 940 TBD mV (pk-pk) Differential Output Voltage Swing (MULTOUT) VOD 100 Ω Load Line-to-Line TBD 900 TBD mV (pk-pk) Output Common Mode Voltage (CLKOUT, MULTOUT) VOCM 100 Ω Load Line-to-Line — VDD – 0.7 — V Output Impedance (CLKOUT, MULTOUT) ROUT Single-ended 84 100 116 Ω Output Short to GND (CLKOUT, MULTOUT) ISC(–) — 25 TBD mA Output Short to VDD (CLKOUT, MULTOUT) ISC(+) TBD –15 — mA Input Voltage Low (LVTTL Inputs) VIL — — .8 V Input Voltage High (LVTTL Inputs) VIH 2.0 — — V Input Low Current (LVTTL Inputs) IIL — 25 TBD µA Input High Current (LVTTL Inputs) IIH — 25 TBD µA " Output Voltage Low (LVTTL Outputs) VOL IO = 2 mA — — 0.4 V Output Voltage High (LVTTL Outputs) VOH IO = 2 mA 2.0 — — V Input Impedance (LVTTL Inputs) RIN 100 — — kΩ TBD 25 TBD µA PWRDN/CAL Internal Pulldown Current IPWRDN VPWRDN ≥ 0.8 V *Note: The CLKIN and REFCLK inputs may be driven differentially or single-endedly. When driving single-endedly, the voltage swing of the signal applied to the active input must exceed the specified minimum Differential Input Voltage Swing (VID min) and the unused input must be ac-coupled to ground. When driving differentially, the difference between the positive and negative input signals must exceed VID min. (Each individual input signal needs to swing only half of this range.) In either case, the voltage applied to any individual pin (CLKIN+, CLKIN–, REFCLK+, or REFCLK–) must not exceed the specified maximum Input Voltage Range (VIS max). 6 Preliminary Rev. 0.6 Si5311 Table 3. AC Characteristics (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter CLKIN Frequency Range Symbol Test Condition * CLKIN Duty Cycle REFCLK Range* Min Typ Max Unit 9.375 — 668 MHz TBD — TBD % 9.375 — 167 MHz REFCLK Duty Cycle CDUTY 40 50 60 % REFCLK Frequency Tolerance CTOL –100 — 100 ppm MULTOUT Clock Rate MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 fMULT 2400 1200 600 150 — — — — 2672 1336 668 167 MHz Output Rise Time (CLKOUT, MULTOUT) tR Figure 4 — 100 TBD ps Output Fall Time (CLKOUT, MULTOUT) tF Figure 4 — 100 TBD ps Input Rise Time (CLKIN, REFCLK) tR Figure 4 — — TBD ps Input Fall Time (CLKIN, REFCLK) tF Figure 4 — — TBD ps CLKIN to MULTOUT Delay MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 tCI-M Figure 3 TBD TBD TBD TBD 0 120 150 3.4 TBD TBD TBD TBD ps ps ps ns MULTOUT to CLKOUT Delay MULTSEL[1:0] = 00 MULTSEL[1:0] = 01 MULTSEL[1:0] = 10 MULTSEL[1:0] = 11 tM-CO Figure 3 — — TBD TBD — — 1/fMULT + 160 960 — — TBD TBD ps ps 18.7 TBD — — — — Input Return Loss 100 kHz–2.5 GHz 2.5 GHz–4.0 GHz dB *Note: See Table 11. Preliminary Rev. 0.6 7 Si5311 Table 4. AC Characteristics (PLL Performance Characteristics) (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Symbol Jitter Tolerance (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz) JTOL(PP) See Table 5 Jitter Tolerance (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz) JTOL(PP) See Table 6 Jitter Tolerance (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz) JTOL(PP) See Table 7 Jitter Tolerance (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz) JTOL(PP) See Table 8 Jitter Generation (MULTOUT) (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz)* JGEN(rms) Clock Input (MHz) = 600.000 to 668.000 — Jitter Generation (MULTOUT) (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz)* JGEN(rms Clock Input (MHz) = 300.000 to 334.000 Jitter Generation (MULTOUT, CLKOUT) (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)* JGEN(rms) Jitter Generation (MULTOUT, CLKOUT) (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz)* Jitter Transfer Bandwidth (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz)* JGEN(rms) JBW Test Condition Max Unit TBD TBD psRMS — TBD TBD psRMS Clock Input (MHz) = 600.000 to 668.000 — TBD TBD psRMS Clock Input (MHz) = 37.500 to 41.750 — 1.9 TBD psRMS Clock Input (MHz) = 75.000 to 83.500 — 1.2 TBD psRMS Clock Input (MHz) = 150.000 to 167.000 — 0.9 TBD psRMS Clock Input (MHz) = 300.000 to 334.000 — 0.5 TBD psRMS Clock Input (MHz) = 600.000 to 668.000 — 0.5 TBD psRMS Clock Input (MHz) = 9.375 to 10.438 — 5.8 TBD psRMS Clock Input (MHz) = 18.750 to 20.875 — 3.2 TBD psRMS Clock Input (MHz) = 37.500 to 41.750 — 2.2 TBD psRMS Clock Input (MHz) = 75.000 to 83.500 — 1.4 TBD psRMS Clock Input (MHz) = 150.000 to 167.000 — 1.3 TBD psRMS Clock Input (MHz) = 600.000 to 668.000 — 1360 TBD kHz *Note: See PLL Performance section of this document for test descriptions. 8 Preliminary Rev. 0.6 Min Typ Si5311 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Symbol Test Condition Min Typ Max Unit Jitter Transfer Bandwidth (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz)* JBW Clock Input (MHz) = 300.000 to 334.000 — 680 TBD kHz Clock Input (MHz) = 600.000 to 668.000 — 1360 TBD kHz Jitter Transfer Bandwidth (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)* JBW Clock Input (MHz) = 37.500 to 41.750 — 85 TBD kHz Clock Input (MHz) = 75.000 to 83.500 — 170 TBD kHz Clock Input (MHz) = 150.000 to 167.000 — 340 TBD kHz Clock Input (MHz) = 300.000 to 334.000 — 680 TBD kHz Clock Input (MHz) = 600.000 to 668.000 — 1360 TBD kHz Clock Input (MHz) = 9.375 to 10.438 — 21 TBD kHz Clock Input (MHz) = 18.750 to 20.875 — 43 TBD kHz Clock Input (MHz) = 37.500 to 41.750 — 85 TBD kHz Clock Input (MHz) = 75.000 to 83.500 — 170 TBD kHz Clock Input (MHz) = 150.000 to 167.000 — 340 TBD kHz Jitter Transfer Bandwidth (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz)* JBW Jitter Transfer Peaking (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz)* JP Clock Input (MHz) = 600.000 to 668.000 — 0.03 TBD dB Jitter Transfer Peaking (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz)* JP Clock Input (MHz) = 300.000 to 334.000 — 0.03 TBD dB Clock Input (MHz) = 600.000 to 668.000 — 0.02 TBD dB Jitter Transfer Peaking (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz)* JP Clock Input (MHz) = 37.500 to 41.750 — 0.12 TBD dB Clock Input (MHz) = 75.000 to 83.500 — 0.06 TBD dB Clock Input (MHz) = 150.000 to 167.000 — 0.03 TBD dB Clock Input (MHz) = 300.000 to 334.000 — 0.02 TBD dB Clock Input (MHz) = 600.000 to 668.000 — 0.01 TBD dB *Note: See PLL Performance section of this document for test descriptions. Preliminary Rev. 0.6 9 Si5311 Table 4. AC Characteristics (PLL Performance Characteristics) (Continued) (VDD = 2.5 V ± 5%, TA = –40°C to 85°C) Parameter Jitter Transfer Peaking (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz)* Acquisition Time Symbol Test Condition Min Typ Max Unit JP Clock Input (MHz) = 9.375 to 10.438 — 0.12 TBD dB Clock Input (MHz) = 18.750 to 20.875 — 0.06 TBD dB Clock Input (MHz) = 37.500 to 41.750 — 0.03 TBD dB Clock Input (MHz) = 75.000 to 83.500 — 0.02 TBD dB Clock Input (MHz) = 150.000 to 167.000 — 0.01 TBD dB After falling edge of PWRDN/CAL 1.45 1.5 1.7 ms From the return of valid CLKIN 40 60 150 µs TAQ Frequency Difference at which PLL goes out of Lock (REFCLK compared to the divided down VCO clock) LOL TBD 600 TBD ppm Frequency Difference at which PLL goes into Lock (REFCLK compared to the divided down VCO clock) LOCK TBD 300 TBD ppm *Note: See PLL Performance section of this document for test descriptions. 10 Preliminary Rev. 0.6 Si5311 Table 5. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 00, MULTOUT = 2400 to 2672 MHz) Frequency (Hz) 600-668 MHz Clock Input < TBD TBD TBD TBD TBD TBD > TBD TBD *Note: Measured using sinusoidal jitter at stated Test Condition frequency. Table 6. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 01, MULTOUT = 1200 to 1336 MHz) Frequency (Hz) 300-334 MHz Clock Input 600-668 MHz Clock Input < TBD TBD TBD TBD TBD TBD TBD TBD TBD > TBD TBD TBD *Note: Measured using sinusoidal jitter at stated Test Condition frequency. Table 7. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 10, MULTOUT = 600 to 668 MHz) Frequency (Hz) 37.5– 41.75 MHz Clock Input 75–83.5 MHz Clock Input 150-167 MHz Clock Input 300–334 MHz Clock Input 600-668 MHz Clock Input < 300 25.0 25.0 25.0 25.0 TBD 25K 2.33 4.67 9.33 16.7 TBD 250K 0.67 0.83 1.17 2.17 TBD > 1M 0.50 0.58 0.67 0.67 TBD *Note: Measured using sinusoidal jitter at stated Test Condition frequency. Preliminary Rev. 0.6 11 Si5311 Table 8. Minimum Jitter Tolerance in Nanoseconds* (MULTSEL[1:0] = 11, MULTOUT = 150 to 167 MHz) Frequency (Hz) 9.375– 10.438 MHz Clock Input 18.75– 20.875 MHz Clock Input 37.5–41.75 MHz Clock Input 75–83.5 MHz Clock Input 150-167 MHz Clock Input < 300 TBD 66.7 66.7 100 TBD 6.5K TBD 18.0 36.7 66.7 TBD 65K TBD 3.33 4.67 8.00 TBD 325K TBD 2.67 2.67 3.33 TBD > 1M TBD 2.00 2.33 2.67 TBD *Note: Measured using sinusoidal jitter at stated Test Condition frequency. Table 9. Absolute Maximum Ratings Parameter Symbol Value Unit DC Supply Voltage VDD –0.5 to 2.8 V LVTTL Input Voltage VDIG –0.3 to 3.6 V Differential Input Voltages VDIF –0.3 to (VDD+ 0.3) V ±50 mA Maximum Current any output PIN Operating Junction Temperature TJCT –55 to 150 °C Storage Temperature Range TSTG –55 to 150 °C 300 °C 1 1.5 kV kV Lead Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 kΩ) CLKIN+, CLKIN–, REFCLK+, REFCLK–, All other pins — — Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 10. Thermal Characteristics Parameter Thermal Resistance Junction to Ambient 12 Symbol Test Condition Value Unit ϕJA Still Air 38 °C/W Preliminary Rev. 0.6 Si5311 Loss-of-Lock Indicator LVTTL Control Inputs Clock Input CLKIN+ LOL PWRDN/CAL MULTSEL1–0 2 CLKOUT+ CLKOUT– CLKIN– Regenerated Clock Si5311 MULTOUT+ REFCLK– MULTOUT– Ω 10 kΩ (1%) VDD VDD Multiplied Clock GND REFCLK+ REXT System Reference Clock 0.1 µF 2200 pF 20 pF Figure 5. Si5311 Typical Application Circuit Preliminary Rev. 0.6 13 Si5311 Functional Description The Si5311 is an integrated high speed clock multiplier and clock regenerator device based on Silicon Laboratories DSPLL™ technology. The DSPLL phase locks to the clock input signal (CLKIN) and generates a phase-locked output clock (MULTOUT) at a multiple of the input clock frequency. The MULTOUT output is configured to operate in the 150–167 MHz, the 600– 668 MHz, the 1.2–1.33 GHz, or the 2.4–2.67 GHz frequency range using the MULTSEL0 and MULTSEL1 control inputs. When the device is configured for a MULTOUT output frequency range of 150–167 MHz or 600–668 MHz, the DSPLL is also employed to regenerate an output clock (CLKOUT) that is a jitter-attenuated version of the input clock with clean rising and falling edges. The CLKOUT output is not characterized for the MULTOUT ranges of 1.2–1.33 GHz or 2.4–2.67 GHz. A reference clock input signal (REFCLK) is used by the DSPLL as a reference for determination of the PLL lock status. For convenience, REFCLK can be provided at any one of five frequencies, each a multiple of the CLKIN frequency. The REFCLK rate is automatically detected, so no control inputs are needed for configuration. The REFCLK input can be synchronous or asynchronous with respect to the CLKIN input. The operating ranges for the CLKIN, CLKOUT, MULTOUT, and REFCLK signals are indicated in Table 11. Values for typical applications are given in Table 12. Table 11. CLKIN, CLKOUT, MULTOUT, REFCLK Operating Ranges CLKOUT MULTOUT MULTSEL [1:0] CLKIN Range (MHz) 00 (MULTOUT = 2.4–2.7 GHz) 600.00–668.00 n = –6, –5, –4, –3, or –2 See Note 1(a) 4xCLKIN 01 (MULTOUT = 1.2–1.33 GHz) 300.00–334.00 n = –5, –4, –3, –2, or –1 See Note 1(a) 4xCLKIN 600.00–668.00 n = –6, –5, –4, –3, or –2 See Note 1(a) 2xCLKIN 10 (MULTOUT = 600–668 MHz) 11 (MULTOUT = 150–167 MHz) REFCLK = 2n x CLKIN ±100 ppm (see Note 2) 37.500–41.750 n = –2, –1, 0, 1, or 2 1xCLKIN 16xCLKIN 75.000–83.500 n = –3, –2, –1, 0, or 1 1xCLKIN 8xCLKIN 150.000–167.000 n = –4, –3, –2, –1, or 0 1xCLKIN 4xCLKIN 300.000–334.000 n = –5, –4, –3, –2, or –1 1xCLKIN 2xCLKIN 600.000–668.000 n = –6, –5, –4, –3, or –2 See Note 1(b) 1xCLKIN 9.375–10.438 n = 0, 1, 2, 3, or 4 1xCLKIN 16xCLKIN 18.750–20.875 n = –1, 0, 1, 2, or 3 1xCLKIN 8xCLKIN 37.500–41.750 n = –2, –1, 0, 1, or 2 1xCLKIN 4xCLKIN 75.000–83.500 n = –3, –2, –1, 0, or 1 1xCLKIN 2xCLKIN 150.000–167.000 n = –4, –3, –2, –1, or 0 See Note 1(b) 1xCLKIN Note: 1. The CLKOUT output is not valid for (a) MULTSEL[1:0] = 00 or MULTOUT[1:0] = 01 (b) MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1 x CLKIN.) 2. The REFCLK input can be set to any one of the five CLKIN multiples indicated. The REFCLK input can be asynchronous to the CLKIN input, but must be within ±100 ppm of the stated CLKIN multiple. 14 Preliminary Rev. 0.6 Si5311 Table 12. Clock Values for Typical Applications SONET/SDH Gigabit Ethernet SONET/SDH FEC (15/14) CLKIN (MHz) REFCLK Input (MHz) 9.72 19.44 38.88 9.72 19.44 38.88 77.76 77.76 155.52 155.52 311.04 9.72, 19.44, 38.88, 77.76, or 155.52 622.08 9.72, 19.44, 38.88, 77.76, or 155.52 9.77 19.53 39.06 9.77 19.53 39.06 78.125 78.125 156.25 156.25 312.5 9.77, 19.53, 39.06, 78.125, or 156.25 625 9.77, 19.53, 39.06, 78.125, or 156.25 10.41 20.83 41.66 10.41 20.83 41.66 83.31 83.31 166.63 166.63 333.26 10.41, 20.83, 41.66, 83.31, or 166.63 666.51 10.41, 20.83, 41.66, 83.31, or 166.63 MULTSEL [1:0] 11 11 10 11 10 11 10 11 01 10 00 01 10 11 11 10 11 10 11 10 11 01 10 00 01 10 11 11 10 11 10 11 10 11 01 10 00 01 10 Preliminary Rev. 0.6 CLKOUT (MHz) 9.72 19.44 38.88 38.88 77.76 77.76 155.52 — — 311.04 — — — 9.77 19.53 39.06 39.06 78.125 78.125 156.25 — — 312.5 — — — 10.41 20.83 41.66 41.66 83.31 83.31 166.63 — — 333.26 — — — MULTOUT output (MHz) 155.52 155.52 622.08 155.52 622.08 155.52 622.08 155.52 1244.16 622.08 2488.32 1244.16 622.08 156.25 156.25 625 156.25 625 156.25 625 156.25 1250 625 2500 1250 625 166.63 166.63 666.51 166.63 666.51 166.63 666.51 166.63 1333.03 666.51 2666.06 1333.03 666.51 15 Si5311 DSPLL™ The PLL structure (shown in Figure 1 on page 4) utilizes Silicon Laboratories' DSPLL technology to produce superior jitter performance while eliminating the need for external loop filter components found in traditional PLL implementations. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). The technology produces clocks with less jitter than is generated using traditional methods. In addition, because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources. Clock Multiplier The DSPLL phase locks to the clock input signal (CLKIN) and generates an output clock (MULTOUT) at a multiple of the input clock frequency. The MULTOUT output is configured to operate in the 150–167 MHz, the 600–668 MHz, the 1.2–1.33 GHz, or the 2.4–2.67 GHz frequency range using the MULTSEL0 and MULTSEL1 control inputs as indicated in Table 11. Values for typical applications are given in Table 12. The amount of jitter present in the MULTOUT output is a function of the DSPLL jitter transfer function and jitter generation characteristic. Details are provided in the PLL Performance section of this document. (See Figures 6, 7, 8, and 9.) The amount of jitter that the DSPLL can tolerate on the CLKIN input is specified in Tables 5, 6, 7, and 8. The DSPLL implementation in the Si5311 is insensitive to the duty cycle of the CLKIN input. The MULTOUT output will continue to exhibit a very good duty cycle characteristic even when the CLKIN input duty cycle is degraded. 1x Multiplication The Si5311 Clock Multiplier function may also be utilized as a 1x multiplier in order to provide jitter attenuation and duty cycle correction without multiplication of the input clock frequency. Note: When the Si5311 is configured as a 1:1 multiplier, the CLKOUT output is not valid. Clock Regeneration When the MULTOUT output is configured to operate in either the 150–167 MHz or the 600–667 MHz range, the Si5311 clock regeneration (CLKOUT output) is also provided. In this case, the DSPLL is used to regenerate 16 a jitter-attenuated version of the CLKIN input, resulting in a “clean” CLKOUT output with sharp rising and falling edges. The CLKOUT output is a resampled version of the CLKIN input with all CLKOUT transitions occurring synchronously with the rising edges of the MULTOUT output. The rising edges of CLKOUT are insensitive to the location of the falling edges of the CLKIN input. Thus the period of CLKOUT, measured rising edge to rising edge, is not affected by the CLKIN duty cycle or by jitter on the falling edge of CLKIN. The falling edges of CLKOUT may be affected by the location of the CLKIN falling edges as follows: If the duty cycle error of CLKIN is significant relative to the period of MULTOUT, then 1. The CLKOUT duty cycle may deviate from 50% (the falling edge of CLKOUT will be time quantized to the nearest rising edge of MULTOUT.) 2. Jitter on the falling edges of CLKIN may result in a CLKOUT duty cycle that alternates between two discrete values. Note: When the Si5310 is configured as a 1:1 multiplier, the CLKOUT output is not valid. Reference Clock The reference clock input (REFCLK) is used to center the DSPLL and also to act as a reference for determination of the PLL lock status. REFCLK is a multiple of the CLKIN frequency, and can be provided in any one of five frequency ranges (9.375–10.438 MHz, 18.78–20.875 MHz, 37.500–41.750 MHz, 75.00– 83.50 MHz, or 150–167.00 MHz). The REFCLK rate is automatically detected by the Si5311, so no control inputs are needed for REFCLK frequency selection. The REFCLK input may be synchronous or asynchronous with respect to the CLKIN input. The frequency relationship between REFCLK and CLKIN is indicated in Table 11. In many applications, it may be desirable to tie REFCLK and CLKIN together and drive them from the same clock source. The Si5311 is insensitive to the phase relationship between CLKIN and REFCLK, so these differential inputs may be driven in phase or 180° out of phase if this simplifies board layout. Values for typical applications are given in Table 12. DSPLL Lock Detection (Loss-of-Lock) The Si5311 provides lock-detect circuitry that indicates whether the DSPLL has frequency locked with the incoming CLKIN signal. The circuit compares the frequency of a divided down version of the multiplier output with the frequency of the supplied reference clock. If the divided multiplier output frequency deviates from that of the reference clock by the amount specified in Table 4 on page 8, the PLL is declared out of lock, and the loss-of-lock (LOL) pin is asserted. While out of lock, the DSPLL will try to reacquire lock Preliminary Rev. 0.6 Si5311 with the input clock. During reacquisition, the multiplier output (MULTOUT) will drift over a range of approximately 1% relative to the supplied reference clock. The LOL output will remain asserted until the divided multiplier output frequency differs from the REFCLK frequency by less than the amount specified in Table 4. the multiplier ratio desired, the larger the jitter generation. Table 4 gives the jitter generation values for specified MULTSEL0/1 settings and input clock rates. PLL Jitter Transfer Functions (MULTSEL[1:0]=00) (dB) 0 CLKIN=622MHz Note: LOL is not asserted during PWRDN/CAL. −1 PLL Performance −2 The Si5311 DSPLL circuitry is designed to provide low jitter generation, high jitter tolerance, and a wellcontrolled jitter transfer function with low peaking. Each of these key performance parameters is described more fully in the following sections. Jitter Tolerance Jitter tolerance for the Si5311 is defined as the maximum peak-to-peak sinusoidal jitter that can be added to the incoming clock before the PLL exceeds its allowable operating range and loses lock. The tolerance is a function of the jitter frequency, the incoming clock rate, and the MULTSEL0/1 settings. The jitter tolerance for specified jitter frequencies and input clock rates is given in Tables 5, 6, 7, and 8. Jitter Transfer Jitter transfer is defined as the ratio of output signal jitter to input signal jitter for a specified jitter frequency. The jitter transfer characteristic determines the amount of input clock jitter that will be passed on to the Si5311 CLKOUT and MULTOUT outputs. The DSPLL technology used in the Si5311 provides a tightly controlled jitter transfer curve because many of the PLL gain parameters are determined by digital signal processing algorithms which do not vary over supply voltage, process, and temperature. In a system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board, providing more consistent system level jitter performance. The jitter transfer characteristic is a function of the MULTSEL0/1 settings and the input clock rate. Higher input clock rates produce higher bandwidth transfer functions with lower jitter peaking. Table 4 gives the 3 dB bandwidth and peaking values for specified input clock rates and MULTSEL0/1 settings. Figures 6, 7, 8, and 9 show a family of jitter transfer curves for different input clock rates. Jitter Generation Jitter generation is defined as the amount of jitter produced at the output of the device with a jitter free input clock. Generated jitter arises from sources within the VCO and other PLL components. Jitter generation is a function of MULTSEL0/1 settings and input clock frequency. For clock multiplier applications, the higher −3 −4 −5 −6 −7 −8 −9 3 10 4 10 5 10 6 10 Figure 6. PLL Jitter Transfer Functions, MULTSEL[1:0] = 00 (MULTOUT = 2400–2672 MHz) PLL Jitter Transfer Functions (MULTSEL[1:0]=01) (dB) 0 CLKIN=622MHz −1 −2 −3 −4 CLKIN=311MHz −5 −6 −7 −8 −9 3 10 4 10 5 10 6 10 Figure 7. PLL Jitter Transfer Functions, MULTSEL[1:0] = 01 (MULTOUT = 1200–1336 MHz) Preliminary Rev. 0.6 17 Si5311 and will begin to lock to the incoming clock. PLL Jitter Transfer Functions (MULTSEL[1:0]=10) (dB) PLL Self-Calibration 0 CLKIN=622MHz Si5311 device provides an internal self-calibration function that optimizes the loop gain parameters within the internal DSPLL. Self-calibration is initiated by a high-to-low transition of the PWRDN/CAL signal while a valid reference clock is supplied to the REFCLK input. −1 −2 −3 −4 CLKIN=39MHz −5 −6 −7 −8 −9 3 4 10 5 10 6 10 10 Figure 8. PLL Jitter Transfer Functions, MULTSEL[1:0] = 10 (MULTOUT = 600–668 MHz) PLL Jitter Transfer Functions (MULTSEL[1:0]=11) (dB) 0 CLKIN=155MHz Device Grounding The Si5311 uses the GND pad on the bottom of the 20pin micro leaded package (MLP) for device ground. This pad should be connected directly to the analog supply ground. See Figures 12 and 13 for the ground (GND) pad location. Bias Generation Circuitry −1 The Si5311 makes use of an external resistor to set internal bias currents. The external resistor allows precise generation of bias currents which significantly reduces power consumption compared with traditional implementations that use an internal resistor. The bias generation circuitry requires a 10 kΩ (1%) resistor connected between REXT and GND. −2 −3 −4 CLKIN=9.7MHz −5 −6 −7 Differential Input Circuitry −8 −9 3 10 4 10 5 10 6 10 Figure 9. PLL Jitter Transfer Functions, MULTSEL[1:0] = 11 (MULTOUT = 150–167 MHz) Device Power-Down The Si5311 PWRDN/CAL input can be used to hold the device in a power-down state when not in use. When the PWRDN/CAL input is asserted (set high), the CLKOUT and MULTOUT output drivers are disabled and the positive and negative terminals of the CLKOUT and MULTOUT outputs are each tied to VDD through 100 Ω on-chip resistors. This feature is useful in reducing power consumption in applications that employ redundant clock sources. When PWRDN/CAL is released (set to low) the digital logic is reset to a known initial condition and the DSPLL circuitry is recalibrated 18 For optimal jitter performance, the supply voltage should be stable at 2.5 V ±10% when calibration is initiated. The PWRDN/CAL signal should be held high for at least 1 µS after the supply has stabilized before transitioning low to initiate self-calibration. See Silicon Laboratories application note AN42 for suggested methods of generating the PWRDN/CAL signal for initiation of self-calibration. The Si5311 provides differential inputs for both the input clock (CLKIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 10. In applications where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The CLKIN and REFCLK input amplifiers require input signals with minimum differential peak-topeak voltages as specified in Table 2 on page 6. Differential Output Circuitry The Si5311 utilizes a current mode logic (CML) architecture to output both the regenerated clock (CLKOUT) and the multiplied clock (MULTOUT). An example of output termination with ac coupling is shown in Figure 11. For applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML is listed in Table 2 on page 6. Preliminary Rev. 0.6 Si5311 Clock source Si5311 VDD 0.1 µ F Zo = 50 Ω C LK IN +, R FC LK + 2.5 k Ω 10 k Ω 0.1 µ F Zo = 50 Ω 2.5 k Ω 102 Ω C LK IN –, R FC LK – 10 k Ω GND Figure 10. Input Termination for CLKIN and REFCLK (AC Coupled) Si5311 VDD VDD 100 Ω 50 Ω CLKOUT+, 0.1 µ F MULTOUT+ Zo = 50 Ω CLKOUT–, MULTOUT– Zo = 50 Ω 0.1 µ F 100 Ω VDD 50 Ω VDD Figure 11. Output Termination for CLKOUT and MULTOUT (AC Coupled) Preliminary Rev. 0.6 19 Si5311 20 19 18 REXT 1 VDD 2 MULTOUT– MULTOUT+ GND MULTSEL0 MULTSEL1 Pin Descriptions: Si5311 17 16 15 PWRDN 14 VDD GND Pad 5 11 VDD 8 9 Top View 10 CLKIN– LOL 7 CLKIN+ 12 CLKOUT– REFCLK– 6 13 CLKOUT+ GND 3 4 VDD GND REFCLK+ Figure 12. Si5311 Pin Configuration Table 13. Si5311 Pin Descriptions Pin # Pin Name 1 REXT 2, 7, 11, 14 VDD 2.5 V Supply Voltage. Nominally 2.5 V. 3, 8, 18, and GND Pad GND GND Supply Ground. Nominally 0.0 V. The GND pad found on the bottom of the 20-pin micro leaded package (see Figure 13) must be connected directly to supply ground. 4, 5 REFCLK+, REFCLK– I See Table 2 Differential Reference Clock. The reference clock sets the initial operating frequency used by the onboard PLL for clock regeneration and multiplication. Additionally, the reference clock is used as a reference in generation of the LOL output and to bound the frequency drift of MULTOUT when CLKIN is not present. 6 LOL O LVTTL Loss of Lock. This output is driven high when a divided version of the clock multiplier output deviates from the reference clock frequency by the amount specified in Table 4 on page 8. 9, 10 CLKIN+, CLKIN– I See Table 2 20 I/O Signal Level Description External Bias Resistor. This resistor is used by onboard circuitry to establish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resistor. Differential Clock Input. Differential input clock from which MULTOUT is derived. Preliminary Rev. 0.6 Si5311 Table 13. Si5311 Pin Descriptions (Continued) Pin # Pin Name I/O Signal Level Description 12, 13 CLKOUT–, CLKOUT+ O CML Differential Clock Output. The clock output signal is a regenerated version of the input clock signal present on CLKIN. It is phase aligned with MULTOUT and is updated on the rising edge of MULTOUT. Notes:The CLKOUT output is not valid for MULTSEL[1:0] = 00 or MULTSEL[1:0] = 01. The CLKOUT output is also not valid for MULTOUT:CLKIN ratios of 1:1 (MULTOUT = 1x CLKIN). Connection of an improperly terminated transmission line to the CLKOUT output can cause reflections that may adversely affect the performance of the MULTOUT output. If the CLKOUT output is not used, these pins should be either tied to VDD (recommended), left unconnected, or connected to a properly terminated transmission line. 15 PWRDN/CAL I LVTTL Power Down. To shut down the high-speed outputs and reduce power consumption, hold this pin high. For normal operation, hold this pin low. Calibration. To initiate an internal self-calibration, force a highto-low transition on this pin. (See "PLL Self-Calibration‚" on page 18.) Note: This input has a weak internal pulldown. 16, 17 MULTOUT–, MULTOUT+ O CML Differential Multiplier Output. The multiplier output is generated from the signal present on CLKIN. In the absence of CLKIN, the REFCLK is used to bound the frequency of MULTOUT according to Table 4 on page 8. Note: Connection of an improperly terminated transmission line to the MULTOUT output can cause reflections that may adversely affect the CLKOUT output. If the MULTOUT output is not used, these pins should be either tied to VDD (recommended), left unconnected, or connected to a properly terminated transmission line. 19 MULTSEL1, MULTSEL0 I LVTTL Multiplier Rate Select. These pins configure the onboard PLL-based clock multiplier for clock generation at one of four user selectable clock rates. Note: These inputs have weak internal pulldowns. 20 NC No Connect. This pin should be tied to ground. Preliminary Rev. 0.6 21 Si5311 Ordering Guide Table 14. Ordering Guide 22 Part Number Package Temperature Si5311-BM 20-pin MLP –40°C to 85°C Preliminary Rev. 0.6 Si5311 Package Outline Figure 13 illustrates the package details for the Si5311. Table 15 lists the values for the dimensions shown in the illustration. TO P VIEW 2X 0 .2 5 BO TTO M VIEW A C D A 10 D /2 0 .0 5 D1 C b 0 .1 0 D 2 /2 A3 0 .2 5 C C A B D2 A2 2X N M R A1 D 1 /2 4 4X P A 8. N B 4X P 5 6 E 1 /2 1 0 .5 0 D IA . 1 E /2 2 2 E1 3 4X Q E 3 C REF. B 2X 0 B 0 .2 0 (N e-1 )X e E 2 /2 L 0 .2 0 E2 C e C A S E A T IN G PLANE 2X C CL A1 b 4 1. SEC TIO N "C -C " SCALE: NONE e REF. 11 NO TES: C CL (N d -1 )X e e 2. DIE THICKNESS ALLO W ABLE IS 0.305mm MA XIMUM(.012 INCHES MAXIMUM ) DIMENSIO NING & TO LERANCES CO NFO RM T O ASME Y14.5M. - 1994. 3. N IS THE NUMB ER O F TERMINALS. Nd IS THE NUM BER O F TERMINALS IN X-DIR ECTIO N & Ne IS THE NUM BER O F TERMINALS IN Y-DIR ECTIO N. 4. DIMENSIO N b A PPLIES TO PLATED TERMINA L AND IS MEASURED BETW EEN 0.20 AND 0.25mm FRO M TERMINA L TIP. T E R M IN A L T IP FO R O D D TER M IN AL/SID E 5. THE PIN #1 IDE NTIFIER MUST BE EXISTED O N THE TO P SURFACE O F THE PACKAG E BY U SING INDENTATIO N MARK O R O THER FEATURE O F PACKA G E BO DY. FO R EVEN TER M IN AL/SID E 6. EXACT SHAPE AND SIZE O F THIS FEATURE IS O PTIO NAL. 7. ALL DIMENSIO N S ARE IN MILLIMETERS. 8. THE SHAPE SH O W N O N FO UR CO RNERS AR E NO T ACTUAL I/O . 9. PACKAG E W AR PAG E MAX 0.05mm. 10. APPLIED FO R E XPO SED PAD AND TERMINAL S. EXCLUDE EMB EDDING PART O F EXPO SED PAD FRO M MEA SURING . 11. APPLIED O NLY FO R TERMINALS. Figure 13. 20-pin Micro Leaded Package (MLP) Table 15. Package Diagram Dimensions Symbol A A1 A2 A3 b D D1 D2 e E Millimeters Min — 0.00 — 0.18 1.95 Nom 0.85 0.01 0.65 0.20 REF — 4.00 BSC 3.75 BSC 2.10 0.50 BSC 4.00 BSC Symbol Max 1.00 0.05 0.80 0.30 2.25 Millimeters Min E1 E2 N Nd Ne L P Q R θ Preliminary Rev. 0.6 1.95 0.50 0.24 0.30 0.13 — Nom 3.75 BSC 2.10 20 5 5 0.60 0.42 0.40 0.17 — Max 2.25 0.75 0.60 0.65 0.23 12° 23 Si5311 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: [email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. 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