KERSEMI SIHFR9220TL

IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
FEATURES
PRODUCT SUMMARY
VDS (V)
- 200
RDS(on) (Ω)
VGS = - 10 V
1.5
Qg (Max.) (nC)
20
Qgs (nC)
3.3
Qgd (nC)
11
Configuration
Single
S
DPAK
(TO-252)
IPAK
(TO-251)
•
•
•
•
•
•
•
•
Dynamic dV/dt Rating
Repetitive Avalanche Rated
Surface Mount (IRFR9220/SiHFR9220)
Straight Lead (IRFUFU9220/SiHFU9220)
Available in Tape and Reel
P-Channel
Fast Switching
Lead (Pb)-free Available
Available
RoHS*
COMPLIANT
DESCRIPTION
G
D
P-Channel MOSFET
Third Power MOSFETs technology is the key to Vishay
advanced line of Power MOSFET transistors. The efficient
geometry and unique processing of the Power MOSFETs
design achieve very low on-state resistance combined with
high transconductance and extreme device ruggedness.
The DPAK is designed for surface mounting using vapor
phase, infrared, or wave soldering techniques. The straight
lead version (IRFU/SiHFU series) is for through-hole
mounting applications. Power dissipation levels up to 1.5 W
are possible in typical surface mount applications.
ORDERING INFORMATION
Package
Lead (Pb)-free
SnPb
DPAK (TO-252)
IRFR9220PbF
SiHFR9220-E3
IRFR9220
SiHFR9220
DPAK (TO-252)
IIRFR9220TRLPbFa
SiHFR9220TL-E3a
IRFR9220TRLa
SiHFR9220TLa
DPAK (TO-252)
IRFR9220TRRPbFa
SiHFR9220TR-E3a
IRFR9220TRRa
SiHFR9220TRa
DPAK (TO-252)
IRFR9220TRPbFa
SiHFR9220T-E3a
IRFR9220TRa
SiHFR9220Ta
IPAK (TO-251)
IRFU9220PbF
SiHFU9220-E3
IRFU9220
SiHFU9220
Note
a. See device orientation.
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current
SYMBOL
VDS
VGS
VGS at - 10 V
TC = 25 °C
TC = 100 °C
ID
Pulsed Drain Currenta
IDM
Linear Derating Factor
Linear Derating Factor (PCB Mount)e
EAS
Single Pulse Avalanche Energyb
Repetitive Avalanche Currenta
IAR
EAR
Repetitive Avalanche Energya
Maximum Power Dissipation
TC = 25 °C
PD
TA = 25 °C
Maximum Power Dissipation (PCB Mount)e
c
dV/dt
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range
TJ, Tstg
Soldering Recommendations (Peak Temperature)
for 10 s
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. VDD = - 50 V, Starting TJ = 25 °C, L = 35 mH, RG = 25 Ω, IAS = - 3.6 A (see fig. 12).
c. ISD ≤ - 3.9 A, dI/dt ≤ 95 A/µs, VDD ≤ VDS, TJ ≤ 150 °C.
d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).
LIMIT
- 200
± 20
- 3.6
- 2.3
- 14
0.33
0.020
310
- 3.6
4.2
42
2.5
- 5.0
- 55 to + 150
260d
UNIT
V
A
W/°C
mJ
A
mJ
W
V/ns
°C
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IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
Maximum Junction-to-Ambient
RthJA
-
-
110
Maximum Junction-to-Ambient
(PCB Mount)a
RthJA
-
-
50
Maximum Junction-to-Case (Drain)
RthJC
-
-
3.0
UNIT
°C/W
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material).
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = - 250 µA
- 200
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = - 1 mA
-
- 0.22
-
V/°C
VGS(th)
VDS = VGS, ID = - 250 µA
- 2.0
-
- 4.0
V
Gate-Source Leakage
IGSS
VGS = ± 20 V
-
-
± 100
nA
Zero Gate Voltage Drain Current
IDSS
VDS = - 200 V, VGS = 0 V
-
-
- 100
VDS = - 160 V, VGS = 0 V, TJ = 125 °C
-
-
- 500
Static
Drain-Source Breakdown Voltage
VDS Temperature Coefficient
Gate-Source Threshold Voltage
Drain-Source On-State Resistance
Forward Transconductance
RDS(on)
gfs
ID = - 2.2 Ab
VGS = - 10 V
VDS = - 50 V, ID = - 2.2 A
µA
-
-
1.5
Ω
1.1
-
-
S
-
340
-
-
110
-
-
33
-
Dynamic
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
Total Gate Charge
Qg
Gate-Source Charge
Qgs
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
VGS = 0 V,
VDS = - 25 V,
f = 1.0 MHz, see fig. 5
pF
-
-
20
-
-
3.3
Qgd
-
-
11
td(on)
-
8.8
-
tr
-
27
-
-
7.3
-
-
19
-
-
4.5
-
-
7.5
-
-
-
- 3.6
-
-
- 14
-
-
- 6.3
V
-
150
300
ns
-
0.97
2.0
µC
td(off)
VGS = - 10 V
ID = - 3.9 A, VDS = - 160 V,
see fig. 6 and 13b
VDD = - 100 V, ID = - 3.9 A,
RG = 18 Ω, RD = 24 Ω, see fig. 10b
tf
Internal Drain Inductance
LD
Internal Source Inductance
LS
Between lead,
6 mm (0.25") from
package and center of
die contact
D
nC
ns
nH
G
S
Drain-Source Body Diode Characteristics
Continuous Source-Drain Diode Current
Pulsed Diode Forward Currenta
Body Diode Voltage
IS
ISM
VSD
Body Diode Reverse Recovery Time
trr
Body Diode Reverse Recovery Charge
Qrr
Forward Turn-On Time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
A
G
TJ = 25 °C, IS = - 3.6 A, VGS = 0
S
Vb
TJ = 25 °C, IF = - 3.9 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %.
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D
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Fig. 1 - Typical Output Characteristics, TC = 25 °C
Fig. 3 - Typical Transfer Characteristics
Fig. 2 - Typical Output Characteristics, TC = 150 °C
Fig. 4 - Normalized On-Resistance vs. Temperature
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IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
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Fig. 7 - Typical Source-Drain Diode Forward Voltage
Fig. 8 - Maximum Safe Operating Area
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
RD
VDS
VGS
D.U.T.
RG
+VDD
- 10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
Fig. 10a - Switching Time Test Circuit
td(on)
tr
td(off) tf
VGS
10 %
90 %
VDS
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
L
VDS
IAS
+ VDD
A
D.U.T.
RG
IAS
- 20 V
tp
Driver
0.01 Ω
tp
15 V
VDS
Fig. 12a - Unclamped Inductive Test Circuit
Fig. 12b - Unclamped Inductive Waveforms
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Current regulator
Same type as D.U.T.
50 kΩ
QG
- 10 V
12 V
0.2 µF
0.3 µF
QGS
-
QGD
D.U.T.
VG
+ VDS
VGS
- 3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
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Fig. 13b - Gate Charge Test Circuit
IRFR9220, IRFU9220, SiHFR9220, SiHFU9220
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
-
-
RG
+
• dV/dt controlled by RG
• ISD controlled by duty factor "D"
• D.U.T. - device under test
+
- VDD
Compliment N-Channel of D.U.T. for driver
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = - 10 V*
D.U.T. ISD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
VDD
Body diode forward drop
Inductor current
Ripple ≤ 5 %
*
ISD
VGS = - 5 V for logic level and - 3 V drive devices
Fig. 14 - For P-Channel
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