SLGSSTU32864E DDR2 Configurable Registered Buffer Applications: • PC3200/4300 DDR2 memory modules • 1:1 25-bit or 1:2 14-bit configurable registered buffer • 1.8V data registers Features: • Compatible with JEDEC standard SSTU32864 • Differential Clock inputs • SSTL_18 Clock and data input signaling • Output circuitry minimizes effects of SSO and unterminated lines • LVCMOS input levels on control and RESET pins • 1.7V-1.9V Supply voltage range. • Max Clock frequency > 300MHz General Description The SLGSSTU32864 is a configurable registered buffer designed for 1.7V to 1.9V VDD operating range. When C1 input pin is low, the SLGSSTU32864 is 1:1 25-bit configuration. When C1 input pin is high, the SLGSSTU32864 is 1:2 14-bit configuration. Additionally, C0 input pin controls the 1:2 pinout as register-A configuration (if low) , and register-B configuration (if high). The C0,C1, and RESET pins are LVCMOS input levels.The C0,C1 input pins are not intended to be switched dynamically during normal operation. They should be tied to logic high or low levels to configure the register. Data propagation from D to Q is controlled by the differential clock (CLK/CLK) and a control signals. The rising edge of CLK (crossing with CLK falling) is used to register the Data. All inputs are SSTL_18 except C0,C1, and RESET pins. The SLGSSTU32864 supports low-power standby operation. Setting RESET pin to a logic “low” disables (CLK/CLK) receivers, and allows floating inputs to all other receivers as well (D, VREF , CLK/CLK). Additionally, all internal registers are reset, and outputs (Q) are set “low”. RESET input pin must always be driven to a valid logic state “high” or “low”. RESET, an LVCMOS asynchronous signal, is also intended for use at the time of power-up. RESET must be held at a logic “low” level during power up. This ensures defined outputs before a stable CLK/CLK is supplied. The SLGSSTU32864 supports low-power active operation as it monitors DCS and CSR inputs. The Qn outputs will be prevented from changing states when both DCS and CSR inputs are high. The Qn outputs will be allowed to change state if either one of DCS or CSR inputs is low. If DCS control is not desired, then CSR input should be held low. In that case, the setup and hold times of DCS is the same as the other D inputs. Ordering Information: Package type Package suffix Topside marking Ordering code LFBGA-96ball 13.5 X 5.5 mm body X SLGSSTU32864EX SLGSSTU32864EX-TR (2,000 pcs/tape and reel) LFBGA-96ball 13.5 X 5.5 mm body X SLGSSTU32864EX SLGSSTU32864EX (2,000 pcs/tray) Silego Technology Inc. (408) 327-8800 1 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 top view pinout, 1:1 (C0=0,C1=0) 1:1 Logic Diagram 1 CLK CLK RESET DCKE VREF DODT DCS CSR . . . . . .. R QCKE CLK D . .. R QODT CLK D . . .. R QCS CLK . 3 4 5 6 A DCKE NC VREF VDD QCKE DNU B D2 D15 GND GND Q2 Q15 C D3 D16 VDD VDD Q3 Q16 D DODT NC GND GND QODT DNU E D5 D17 VDD VDD Q5 Q17 F D6 D18 GND GND Q6 Q18 G NC RESET VDD VDD C1 C0 H CLK DCS GND GND QCS DNU J CLK CSR VDD VDD ZOH ZOL K D8 D19 GND GND Q8 Q19 L D9 D20 VDD VDD Q9 Q20 M D10 D21 GND GND Q10 Q21 N D11 D22 VDD VDD Q11 Q22 P D12 D23 GND GND Q12 Q23 R D13 D24 VDD VDD Q13 Q24 T D14 D25 VREF VDD Q14 Q25 D . . Dn 2 . .. 1 of 22 CE R CLK Qn D To 21 other Dn channels Silego Technology Inc. (408) 327-8800 2 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 top view pinout, 1:2 “A”(C0=0,C1=1) 1:2 “A”- configuration Logic Diagram CLK CLK RESET DCKE VREF DODT DCS CSR . . . . . .. QCKEA R . CLK QCKEB D . .. R . CLK QODTB D . . .. QCSA R . CLK . 2 3 4 5 6 A DCKE NC VREF VDD QCKEA QCKEB B D2 DNU GND GND Q2A Q2B C D3 DNU VDD VDD Q3A Q3B D DODT NC GND GND QODTA QODTB E D5 DNU VDD VDD Q5A Q5B F D6 DNU GND GND Q6A Q6B G NC RESET VDD VDD C1 C0 H CLK DCS GND GND QCSA QCSB J CLK CSR VDD VDD ZOH ZOL K D8 DNU GND GND Q8A Q8B L D9 DNU VDD VDD Q9A Q9B M D10 DNU GND GND Q10A Q10B N D11 DNU VDD VDD Q11A Q11B P D12 DNU GND GND Q12A Q12B R D13 DNU VDD VDD Q13A Q13B T D14 DNU VREF VDD Q14A Q14B QCSB D . . Dn QODTA 1 . .. 1 of 11 CE R CLK QnA . QnB D To 10 other Dn channels Silego Technology Inc. (408) 327-8800 3 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 top view pinout, 1:2 “B”(C0=1,C1=1) 1:2 “B”- configuration Logic Diagram CLK CLK RESET DCKE VREF DODT DCS CSR . . . . . .. QCKEA R . CLK QCKEB D . .. R . CLK QODTB D . . .. QCSA R . CLK . 2 3 4 5 6 A D1 NC VREF VDD Q1A Q1B B D2 DNU GND GND Q2A Q2B C D3 DNU VDD VDD Q3A Q3B D D4 NC GND GND Q4A Q4B E D5 DNU VDD VDD Q5A Q5B F D6 DNU GND GND Q6A Q6B G NC RESET VDD VDD C1 C0 H CLK DCS GND GND QCSA QCSB J CLK CSR VDD VDD ZOH ZOL K D8 DNU GND GND Q8A Q8B L D9 DNU VDD VDD Q9A Q9B M D10 DNU GND GND Q10A Q10B N DODT DNU VDD VDD QODTA QODTB P D12 DNU GND GND Q12A Q12B R D13 DNU VDD VDD Q13A Q13B T DCKE DNU VREF VDD QCKEA QCKEB QCSB D . . Dn QODTA 1 . .. 1 of 11 CE R CLK QnA . QnB D To 10 other Dn channels Silego Technology Inc. (408) 327-8800 4 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 Terminal Description: TERMINAL NAME TYPE Q (1:25) OUTPUT Q-Outputs that are stopped by CSR & DCS control. GND GROUND Ground VDD POWER Supply voltage D (1:25) INPUT D-Inputs latched in on the rising edge of CLK crossing falling edge of CLK CLK INPUT Positive clock input CLK INPUT Negative clock input C0,C1 INPUT Control inputs for register configurations: 1:1 , 1:2 A , 1:2 B RESET INPUT Asynchronous reset (active low) VREF INPUT Input reference voltage. Both inputs are internally connected together by 200Ω CSR, DCS INPUT Chip select control pins. Q1-Q25 outputs stopped when CSR & DCS=high DODT INPUT D-input. This register not stopped by CSR & DCS control. DCKE INPUT D-input. This register not stopped by CSR & DCS control. QCS OUTPUT Q-Output. Not stopped by CSR & DCS control. QODT OUTPUT Q-Output. Not stopped by CSR & DCS control. QCKE OUTPUT Q-Output. Not stopped by CSR & DCS control. NC NC No-connect. Ball present, but no internal connection to the die. DNU DNU Do-not-use. Ball internally connected to the die and should be left open-circuit. ZOL,ZOH NC Reserved for future use. Ball present, not electrically connected to the die. DESCRIPTION Function Table Inputs Outputs Dn,DODT , DCKE Qn QCS L L L L L L L H H L H H L L X Q0 Q0 Q0 H L H L L L L H L H H H L H H L H X Q0 Q0 Q0 H H L L L H L H H L H H H H H H L X Q0 Q0 Q0 H H H L Q0 H L H H H H Q0 H H H H H X Q0 Q0 Q0 L L L RESET DCS CSR H L H L X, or Floating X, or Floating Silego Technology Inc. (408) 327-8800 CLK L or H L or H L or H CLK L or H L or H L or H L or H L or H X, or Floating X, or Floating X, or Floating 5 QODT, QCKE PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E Absolute Maximum Ratings Storage Temperature. . . . . . . . . . . . . . -65oC to +150oC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V Input Voltage1,2. . . . . . . . . . . . . . . . . . . . . . -0.5 to 2.5V Output Voltage1,2 . . . . . . . . . . . . . . . . -0.5 to VDD +0.5 Input Clamp Current. . . . . . . . . . . . . . . . . . . . . . -50 mA Output Clamp Current . . . . . . . . . . . . . . . . . . . +50 mA Continuous VDD or GND Current/Pin. . . . . . . +100 mA BGA Package Thermal Impedance3 . . . . . . . . 37oC/W Notes: 1. The input and output negative voltage ratings may be exceded if the input and output clamp currents are within limits. 2. Limited to 2.5V Max. 3. The package thermal impedance is calculated according to JESD 51-7 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to this device. These ratings are stress specifications only and functional operation of the device at these or other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Recommended Operating Conditions: PARAMETER MIN TYP MAX VDD Supply Voltage VREF Reference Voltage 0.49 X VDD VTT Termination Voltage VREF - 0.04 VI Input Voltage VIH (DC) DC Input High Voltage VIH (AC) AC Input High Voltage VIL (DC) DC Input Low Voltage VIL (AC) AC Input Low Voltage VIH Input High Voltage Level VIL Input Low Voltage Level VICR Common mode Input Range VID Differential Input Voltage IOH High-Level Output Current -8 IOL Low-Level Output Current 8 TA Operating Free-Air Temperature Silego Technology Inc. (408) 327-8800 1.7 0 UNITS 1.9 .5 X VDD 0.51 X VDD VREF VREF + 0.04 VDD VREF +0.125 Data Inputs VREF + 0.25 VREF -0.125 VREF - 0.25 RESET, Cn V 0.65 X VDD 0.35 X VDD 0.675 CLK, CLK 1.125 0.6 0 6 mA oC 70 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E SLGSSTU32864 DC Electrical Characteristics VDD = 1.8 +/-0.1V (unless otherwise stated) PARAMETER IOH = -100µA VOH VOL All Inputs II MIN VDD CONDITIONS TYP IOH = -6mA 1.7V IOL = 100µA 1.7V -1.9V 0.2 IOL = 6mA 1.7V 0.5 VI = VDD or GND 1.9V +5 µA 1.2 100 µA 40 mA VI = VIH(AC) or VIL(AC), RESET = VDD Dynamic operating (clock only) RESET = VDD, VI = VIH(AC) or VIL(AC), I = 0 O CLK & CLK switching 50% duty cycle Dynamic Operating 1:2 (each data input) Data Inputs Ci 1.9V Operating (Static) Dynamic IDDD Operating 1:1 (each data input) UNITS 1.7V -1.9V VDD - 0.2 Standby (Static) RESET = GND IDD MAX VICR=0.9V, VI(PP) = 600mV RESET VI = VDD or GND µA/ clock MHZ/ data 18 1.8V µA/ clock MHZ/ data 36 VI = VREF + 250 mV CLK and CLK µA/ MHz 28 RESET = VDD, VI = VIH(AC) or VIL(AC), CLK & CLK switching 50% duty cycle. One data input switching at half clock frequency, 50%duty cycle 1.8V V 2.5 3.8 5 4.4 4.8 5.2 4.2 4.6 5 pF Timing Requirements: (over operating free-air temperature range, unless otherwise noted) Input slew rates are 1V/ns + 20%. PARAMETER MIN fclock Clock frequency tW Pulse duration. CLK,CLK high or low tACT Differential active time4 Setup time tH Hold time UNITS 300 MHz 1 tINACT Differential inactive time5 tS MAX ns 10 ns 15 ns , CLK , CSR high DCS before CLK , CLK , CSR low 0.7 ns 0.5 ns , CLK DCS, CSR, ODT, CKE, Data before CLK , CLK 0.5 ns 0.5 ns DCS before CLK CSR, ODT, CKE, and Data before CLK Notes: 4. Data and VREF inputs must be held low for a minimum time (tACT max) after RESET driven high 5. Data, VREF, and CLK,CLK inputs must be held at valid logic (high or low) levels for a minimum time (tINACT max) after RESET driven low Silego Technology Inc. (408) 327-8800 7 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E AC Specifications Switching Characteristics: (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL From (Input) To (Output) VDD = 1.8V + 0.1V MIN fMAX TYP UNITS MAX 300 tPDM6,7 CLK, CLK Q tRPHL RESET Q MHz 1.41 2.5 ns 3 ns Notes: 6. Includes 350pS trace delay of the test load 7. Guaranteed by design and may not be 100% production tested. Output Buffer Characteristics: (over recommended operating free-air temperature range, unless otherwise noted) VDD = 1.8V + 0.1V SYMBOL From To MIN TYP MAX dV/dt_r dV/dt_f 20% 80% 80% 20% 1 1 dV/dt_∆8 Notes: 8. Difference between rising and falling edge rates. UNITS 4 4 V/ns V/ns 1 V/ns VDD DUT 50 Ω Q . . VOH Output 80% test point dv_f 20% 10pF VOL dt_f Output load test circuit: high to low slew rate Voltage waveform: high to low slew rate dt_r DUT Q Output . . test point 80% dv_r 20% 10pF VOL 50 Ω Output load test circuit: low to high slew rate Silego Technology Inc. (408) 327-8800 VOH Voltage waveform: low to high slew rate 8 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E VDD test point . CLK DUT 1k Ω Z=50 Ω 100Ω . . . Q test point 350ps trace CLK 30pF 1k Ω test point Output load test circuit VDD RESET LVCMOS input Timing Input VDD/2 VDD/2 0V tINACT tACT IDD(2) 10% VID VICR tPLH IDDH 90% VICR Output tPHL VOH VDD/2 VDD/2 IDDL VOL Voltage and Current Waveforms Inputs Active and Inactive Times Voltage Waveforms - Propagation Delay Times tw Input VIH VREF VREF VIL RESET LVCMOS input VIH VDD/2 VIL Voltage Waveforms - Pulse Duration tPHL Output VOH VDD/2 VOL Voltage Waveforms - Propagation Delay Times Timing Input tS Input VID VICR tH VIH VREF VREF VIL Voltage Waveforms - Setup and Hold Times Notes: 1. CL includes measurement probe and jig capacitance. 2. Conditions for IDD testing are with clock and data inputs at VDD or GND, and IO = 0mA 3. All input pulses are supplied by generators having: Zo=50Ω, input slew rate = 1 V/ns + 20% ( unless otherwise specified). 4. The outputs are measured individually with one transition per measurement. 5. VIH = VREF + 250mV (AC levels) for differential inputs. VIH = VDD for LVCMOS input. 6. VIL = VREF - 250mV (AC levels) for differential inputs. VIL = GND for LVCMOS input. 7. tPLH = tPHL = tPD Silego Technology Inc. (408) 327-8800 9 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E Package dimensions: SLGSSTU32864EX 96-LFBGA Silego Technology Inc. (408) 327-8800 10 PRELIMINARY Data is subject to change. Mar 5, 2004 SLGSSTU32864E Silego Technology Inc. reserves the right at any time to change specifications and circuitry without notice. Silego Technology Inc. does not assume responsibility for use of circuitry described. Circuit patent licenses are not implied. Silego Technology Inc. products are not authorized for use as critical components in life support devices or systems without obtaining express written approval from the president of Silego Technology Inc. A component is a critical component if failure to perform affects safety, effectiveness, or causes failure of the life support system. These systems are intended for surgical implant into the body, or support or sustain life, or whose failure to perform when properly used can be reasonably expected to result in injury to the user. Silego Technology Inc. (408) 327-8800 11 PRELIMINARY Data is subject to change. Mar 5, 2004