MICREL SM802117

SM802117
ClockWorks™ GbE (125MHz)
Ultra-Low Jitter, LVPECL
Frequency Synthesizer
General Description
Features
The SM802117 is a member of the ClockWorks™ family of
devices from Micrel and provides an extremely low-noise
timing solution for GbE Ethernet clock signals. It is based
upon a unique patented RotaryWave® architecture that
provides very low phase noise.
The device operates from a 3.3V or 2.5V power supply
and synthesizes LVPECL output clocks at 125MHz. There
are two differential clock outputs each with it’s own OE pin
allowing them to be disabled independently. The
SM802117 accepts a 25 MHz crystal or LVCMOS
reference clock.
Data sheets and support documentation can be found on
Micrel’s web site at: www.micrel.com.
• Generates one or two LVPECL clock outputs at 125MHz
• 2.5V or 3.3V operating range
• Typical phase jitter @ 125MHz
(1.875MHz to 20MHz): 115fs
• Industrial temperature range (–40°C to +85°C)
• Green, RoHS, and PFOS compliant
• Available in 24-pin 4mm × 4mm QFN package
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Applications
• Gigabit Ethernet - PHY
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Block Diagram
ClockWorks is a trademark of Micrel, Inc
RotaryWave is a registered trademark of Multigig, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
October 2011
M9999-101311-B
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Micrel, Inc.
SM802117
Ordering Information
Marking
Shipping
Temperature Range
Package
SM802117UMG
Part Number
802117
Tube
–40°C to +85°C
24-Pin QFN
SM802117UMGTR
802117
Tape and Reel
–40°C to +85°C
24-Pin QFN
Note:
1. Devices are Green, RoHS, and PFOS compliant.
Pin Configuration
24-Pin QFN
(Top View)
Pin Description
Pin Number
Pin Name
Pin Type
Pin Level
Pin Function
19, 20
/Q1, Q1
O, (DIF)
LVPECL
22, 23
/Q2, Q2
O, (DIF)
LVPECL
24
VDDO2
PWR
Power Supply for Output Bank 2
2
VSSO2
PWR
Power Supply Ground for Output Bank 2
Differential Clock Output from Bank 1
125MHz
Differential Clock Output from Bank 2
125MHz
PLL Bypass, Selects Output Source
3
PLL_BYPASS
I, (SE)
0 = Normal PLL Operation
LVCMOS
1 = Output from Input Reference Clock or Crystal
45KΩ pull-down
4
October 2011
XTAL_SEL
I, (SE)
Selects PLL Input Reference Source
LVCMOS
0 = REF_IN, 1 = XTAL, 45KΩ pull-up
2
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SM802117
Pin Description (Continued)
Pin Number
Pin Name
5, 6 11, 16,18
TEST
1
VDD
Pin Type
Pin Level
Pin Function
Factory Test pins, Do not connect anything to these pins.
PWR
Core Power Supply
13, 14, 15
VSS
PWR
Core Power Supply Ground
17
VDDO1
PWR
Power Supply for Output Bank 1
21
VSSO1
PWR
Power Supply Ground for Output Bank 1
8
REF_IN
I, (SE)
LVCMOS
9
XTAL_IN
I, (SE)
crystal
10
XTAL_OUT
O, (SE)
crystal
7
OE1
I, (SE)
LVCMOS
12
OE2
I, (SE)
LVCMOS
Reference Clock Input
Crystal Reference Input, no load caps needed.
See Fig. 5.
Crystal Reference Output, no load caps needed.
See Fig. 5.
Output Enable, Q1 disables to tri-state,
0 = Disabled, 1 = Enabled, 45KΩ pull-up
Output Enable, Q2 disables to tri-state,
0 = Disabled, 1 = Enabled, 45KΩ pull-up
Application Information
Input Reference
When operating with a crystal input reference, do not
apply a switching signal to REF_IN.
Crystal Layout
Keep the layers under the crystal as open as possible
and do not place switching signals or noisy supplies
under the crystal.
Crystal load capacitance is built inside the die so no
external capacitance is needed. See the Selecting a
Quartz crystal for the Clockworks Flex I Family of
Precision Synthesizers application note for further
details.
Contact Micrel’s HBW applications group if you need
assistance on selecting a suitable crystal for your
application at [email protected].
HU
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Truth Table
PLL_BYPASS
XTAL_SEL
INPUT
0
−
−
PLL
1
−
−
XTAL/REF_IN
−
0
REF_IN
−
−
1
XTAL
−
October 2011
OUTPUT
3
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SM802117
Absolute Maximum Ratings(1)
Operating Ratings(2)
Supply Voltage (VDD, VDDO1/2) ......................................+4.6V
Input Voltage (VIN). ............................. –0.50V to VDD + 0.5V
Lead Temperature (soldering, 20sec.)....................... 260°C
Case Temperature ..................................................... 115°C
Storage Temperature (Ts) .........................–65°C to +150°C
Supply Voltage (VDD, VDDO1/2)............... +2.375V to +3.465V
Ambient Temperature (TA) .......................... –40°C to +85°C
Junction Thermal Resistance(3)
QFN (θJA)
Still-Air.........................................................50°C/W
QFN (ψJB)
Junction-to-Board .......................................30°C/W
DC Electrical Characteristics(4)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 2.5V ±5%
TA = −40°C to +85°C.
Symbol
Parameter
Condition
VDD, VDDO1/2
2.5V Operating Voltage
VDD, VDDO1/2
3.3V Operating Voltage
IDD
REF_IN
Supply current VDD + VDDO
XTAL_SEL = 0
Outputs open
IDD
XTAL
Supply current VDD + VDDO
XTAL_SEL = 1
Outputs open
Min.
Typ.
Max.
Units
2.375
2.5
2.625
V
3.135
3.3
3.465
V
125MHz - 1 output
97
125
mA
125MHz - 2 outputs
114
148
mA
125MHz - 1 output
87
113
mA
125MHz - 2 outputs
104
135
mA
LVPECL OUTPUT DC Electrical Characteristics(4)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 2.5V ±5%
TA = −40°C to +85°C. RL = 50Ω to VDDO − 2V
Symbol
Parameter
Min.
Typ.
Max.
Units
VOH
Output High Voltage
Condition
VDDO – 1.145
VDDO – 0.97
VDDO – 0.845
V
VOL
Output Low Voltage
VDDO – 1.945
VDDO – 1.77
VDDO – 1.645
V
VSWING
Output Voltage Swing
0.6
0.8
1.0
V
Note:
1.
Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied
at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
2.
The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.
3.
Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB.
4.
The circuit is designed to meet the AC and DC specifications shown in the above table(s) after thermal equilibrium has been established.
October 2011
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SM802117
LVCMOS (PLL_BYPASS, XTAL_SEL, OE1/2) DC Electrical Characteristics(4)
VDD = 3.3V ±5%, or 2.5V ±5%, TA = −40°C to +85°C.
Symbol
Parameter
VIH
Input High Voltage
Condition
VIN
Input Low Voltage
IIH
Input High Current
VDD = VIN = 3.465V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
Min.
Typ.
Max.
Units
2
VDD + 0.3
V
−0.3
0.8
V
150
μA
−150
μA
REF_IN DC Electrical Characteristics(4)
VDD = 3.3V ±5%, or 2.5V ±5%, TA = −40°C to +85°C.
Symbol
Parameter
VIH
Input High Voltage
VIL
Input Low Voltage
IIN
Input Current
Condition
Min.
XTAL_SEL = VIL, VIN = 0V to VDD
Max.
Units
1.1
VDD + 0.3
V
−0.3
0.6
V
−5
5
μA
XTAL_SEL = VIH, VIN = VDD
Typ.
20
µA
Crystal Characteristics
Parameter
Condition
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitor, C0
Correlation Drive Level
10 to 12pF Load
October 2011
Min.
Typ.
Max.
Fundamental, Parallel Resonant
25
50
1
5
10
100
5
Units
MHz
Ω
pF
uW
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SM802117
AC Electrical Characteristics(4, 5)
VDD = VDDO1/2 = 3.3V ±5% or 2.5V ±5%
VDD = 3.3V ±5%, VDDO1/2 = 2.5V ±5%
TA = −40°C to +85°C. RL = 50Ω to VDDO − 2V
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
FOUT
Output Frequency
125
MHz
FREF
Reference Input Frequency
25
MHz
TR/TF
LVPECL Output Rise/Fall Time
ODC
Output Duty Cycle
TSKEW
Output-to-Output Skew
TLOCK
PLL Lock Time
Tjit(∅)
RMS Phase Jitter
(7)
Spurious Noise Components
20% – 80%
Within bank. Note
80
175
350
ps
48
50
52
%
45
ps
20
ms
6
125MHz
Integration Range (1.875MHz – 20MHz)
Integration Range (12kHz – 20MHz)
115
254
fs
25MHz
-85
dBc
Notes:
5.
All phase noise measurements were taken with an Agilent 5052B phase noise system.
6.
Defined as skew between outputs at the same supply voltage and with equal load conditions and same frequency; Measured at the output
differential crossing points.
7.
Measured using 25MHz crystal as the input reference source. If using an external reference input, use a low phase noise source. With an external
reference, the phase noise will follow the input source phase noise up to about 1MHz.
October 2011
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SM802117
Phase Noise Plots
October 2011
Phase Noise Plot: 125MHz, 1.875MHz − 20MHz
115fS
Phase Noise Plot: 125MHz, 12kHz − 20MHz
254fS
7
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SM802117
Timing Diagrams
Figure 1. Duty Cycle TIming
Figure 2. All Outputs Rise/Fall Time
Figure 3. RMS Phase/Noise/Jitter
October 2011
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SM802117
Input and Output Stage
Figure 4. LVPECL Output Load and Test Circuit
Figure 5. Crystal Input Interface
October 2011
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[email protected] or (408) 955-1690
Micrel, Inc.
SM802117
Package Information
24-Pin QFN
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB www.micrel.com
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Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
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© 2011 Micrel, Incorporated.
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