SUMMIT SMB117A

SMB113A/B/SMB117/A
Preliminary Information
High-power, Four-channel Programmable DC-DC System Power Managers
FEATURES & APPLICATIONS
INTRODUCTION
• Digital programming of all major parameters via
I2C interface and non-volatile memory
• Output voltage set point
• Input/battery voltage monitoring
• Output power-up/down sequencing
• Digital soft-start and output slew rate
• Dynamic voltage control of all outputs
• UV/OV monitoring of all outputs
• Enable/Disable outputs independently
• User friendly Graphical User Interface (GUI)
• Four synchronous step-down output channels
• Integrated RESET monitor
• +2.7V to +6.0V Input Range
• Highly accurate output voltage: <1.5%
• Factory programmable dead times
• 0% to 100% Duty Cycle operation
• Undervoltage Lockout (UVLO) with hysteresis
• 250kHz (SMB117A), 400kHz (SMB117), 800kHz
(SMB113A), 1MHz (SMB113B) operating frequency
• 96 bytes of user configurable nonvolatile memory
Applications
•
•
•
•
•
•
Car & Marine Navigation Systems
Set-top Boxes
TVs
DDR Memory
Mobile Computing/PDAs
Office Equipment
• DMB Systems
The SMB113A/B and SMB117/A are highly integrated and
flexible four-channel power managers designed for use in a
wide range of applications. The built-in digital programmability
allows system designers to custom tailor the device to suit
almost any multi-channel power supply application from digital
camcorders to set-top boxes. Complete with a user friendly
GUI, all programmable settings, including output voltages and
input/output voltage monitoring, can be customized with ease.
The SMB113A/B and SMB117/A integrate all the essential
blocks required to implement a complete four-channel power
subsystem consisting of four synchronous step-down “buck”
controllers. Additionally sophisticated power control/monitoring
functions required by complex systems are built-in. These
include digitally programmable output voltage set point, powerup/down sequencing, enable/disable, dynamic voltage
management and UV/OV monitoring on all channels.
The integration of features and built-in flexibility of the
SMB113A/B and SMB117/A allows the system designer to
create a “platform solution” that can be easily modified via
software without major hardware changes. Combined with the
re-programmability of the SMB113A/B and SMB117/A, this
facilitates rapid design cycles and proliferation from a base
design to future product generations.
The SMB113A/B and SMB117/A are suited to a wide variety of
applications with an input range of +2.7V to +6.0V. Higher
input voltage operation can easily be implemented with a small
number of external components.
Output voltages are
extremely accurate (<1.5%). Communication is accomplished
2
via the industry standard I C bus. All user-programmed
settings are stored in non-volatile EEPROM of which 96 bytes
may be used as general-purpose memory. The devices are
offered in both the commercial and the industrial operating
temperature range. The package type is a lead-free, RoHS
compliant, 5x5 QFN-32.
SIMPLIFIED APPLICATIONS DRAWING
+2.7V to +6.0V
or
Li-Ion
SMB113A/B
+2.7V to +6.0V
or
Li-Ion
+0.5V to Vin (Prog.) @ 1.5A/5A
I2C/SMBus
Enable Input
Reset Input
RESET Output
(Power Good)
System
Control
and
Monitoring
+0.5V to Vin (Prog.) @ 5A/10A
CPU Core
I2C/SMBus
4 StepDown
(Buck)
Channels
RESET
Monitor
+0.5V to Vin (Prog.) @ 1.5A/5A
Memory, I/O
Enable Input
+0.5V to Vin (Prog.) @ 1.5A/5A
+0.5V to Vin (Prog.) @ 1.5A/5A
SMB117/A
DSP/Codec
Analog/RF
Reset Input
RESET Output
(Power Good)
System
Control
and
Monitoring
RESET
Monitor
4 StepDown
(Buck)
Channels
+0.5V to Vin (Prog.) @ 5A/10A
+0.5V to Vin (Prog.) @ 5A/10A
+0.5V to Vin (Prog.) @ 5A/10A
CPU Core
Memory, I/O
DSP/Codec
Analog/RF
Figure 1 – Applications schematic featuring the SMB113A/B/117/A programmable DC-DC controllers.
Note: This is an applications example only. Some pins, components and values are not shown.
© SUMMIT Microelectronics, Inc. 2007
757 N. Mary Avenue • Sunnyvale CA 94085
Phone 408 523-1000 • FAX 408 523-1266
http://www.summitmicro.com/
2111 2.4 6/24/2008
1
SMB113A/B/SMB117/A
Preliminary Information
GENERAL DESCRIPTION
The SMB113A/B and SMB117/A are fully programmable
DC-DC controllers that incorporate power delivery and
advanced power monitoring and control functionality.
The devices integrate four synchronous “buck” stepdown controllers in a space saving package.
The SMB113A uses a fixed 800kHz whereas the
SMB113B uses a fixed 1MHz, the SMB117 a fixed
400kHz and the SMB117A a fixed 250kHz Pulse Width
Modulation (PWM) control circuit. A type-three voltage
mode compensation network is used offering a cost
effective solution without compromising transient
response performance. By utilizing external N- and P–
type MOSFET transistors the efficiency and load current
level can be customized to fit a wide array of system
requirements.
The SMB113A/B and SMB117/A contain four buck
outputs capable of producing an output voltage less than
the input voltage. Each buck output voltage is set by an
internal resistor divider and a programmable voltage
reference. The integrated resistor divider eliminates the
cost and space necessary for external components and
has several programmable values.
Through the
programmability of the reference and the resistor divider,
practically any output voltage smaller than the battery
can be produced without the need to change external
components.
The SMB113A/B and SMB117/A are capable of poweron/off cascade sequencing where each channel can be
assigned one of four unique sequence positions. During
sequencing each channel in a given sequencing position
is guaranteed to reach its programmed output voltage
before the channel(s) occupying the next sequence
position initiate their respective soft-start sequence. A
unique programmable delay exists between each power
on/off sequence position. In addition to power on/off
sequencing all supplies can be powered on/off
Summit Microelectronics, Inc.
individually through an I2C command or by assertion of
the enable pin.
Each output voltage is monitored for under-voltage and
over-voltage (UV/OV) conditions, using a comparatorbased circuit where the output voltage is compared
against an internal programmable reference.
An
additional feature of the output voltage monitoring is a
programmable glitch filter capable of digitally filtering a
transient OV/UV fault condition from a true system error.
When a fault is detected for a period in excess of the
glitch filter, all supplies may be sequenced down or
immediately disabled and an output status pin can be
asserted.
The current system status is always
accessible via internal registers containing the status of
all four channels.
The SMB113A/B and SMB117/A also possess an
Under-voltage Lockout (UVLO) circuit to ensure the
devices will not power up until the input voltage has
reached a safe operating voltage. The UVLO function
exhibits hysteresis, ensuring that noise or a brown out
voltage on the supply rail does not inadvertently lead to
a system failure.
The SMB113A/B and SMB117/A provide dynamic
voltage management over all of their output voltages.
Through an I2C command, all output voltage levels can
be increased or decreased to a pre-programmed level.
In addition, each output is slew rate limited by soft-start
circuitry that is user-programmable and requires no
external capacitors.
All programmable settings on the SMB113A/B and the
SMB117/A are stored in non-volatile registers and are
easily accessed and modified over an industry standard
I2C serial bus. For fastest prototype development times
Summit offers an evaluation card and a Graphical User
Interface (GUI).
2111 2.4 6/24/2008
2
SMB113A/B/SMB117/A
Preliminary Information
TYPICAL APPLICATION
VIN: +2.7V to +6.0V
SMB113A/B
(SMB117/A)
VBATT
HVSUP3
VDDCAP
GND
HSDRV_CH3
+0.8V to VIN @ 5A (10A)
LSDRV_CH3
VM_CH3
SDA
SCL
PWREN
COMP1_CH3
COMP2_CH3
HEALTHY/nRESET
HOST_RESET
HVSUP2
HSDRV_CH2
+0.8V to VIN @ 5A (10A)
HVSUP0
HSDRV_CH0
+0.8V to VIN @ 5A (10A)
LSDRV_CH2
LSDRV_CH0
VM_CH2
COMP1_CH2
VM_CH0
COMP2_CH2
COMP1_CH0
HVSUP1
COMP2_CH0
HSDRV_CH1
+0.8V to VIN @ 5A (10A)
LSDRV_CH1
VM_CH1
COMP1_CH1
COMP2_CH1
Figure 2 – Typical application schematic
Summit Microelectronics, Inc
2111 2.4 6/24/2008
3
SMB113A/B/SMB117/A
Preliminary Information
INTERNAL BLOCK DIAGRAM
COMP2_CH[0,1,2,3]
VM_CH[0,1,2,3]
HVSUP[0,1,2,3]
100k
–
z
+
z
I2C/SMBUS
OA
DUTY
CYCLE
LIMIT
+
z
–
SDA
SCL
CLAMP
OSC
Fixed 250/400/
800/1000kHz
COMP1_CH[0,1,2,3]
z
+
z
–
VREF
GLITCH
FILTER
+
–
GLITCH
FILTER
LOW LIMIT
OVER VOLTAGE
DETECTION
UNDER VOLTAGE
DETECTION
VREF
VBATT
LSDRV[0,1,2,3]
SEQUENCING
AND
MONITORING
LOGIC
ENABLE
BANDGAP
HSDRV[0,1,2,3]
DEADTIME
MAX LIMIT
LEVEL
SHIFTER
DIGITAL TO
ANALOG
CONVERTER
Channel 0,1,2,3
Synchronous buck
PWM Converter
PWREN0
GND
VREF
VDDCAP
VDD_CAP
2.5V
REGULATOR
z
z
+
–
UV2 z
z D
LEVEL
SHIFTER
+
–
Q
UV1z
VREF
Figure 3 –SMB113A/B and SMB117/A internal block diagram. Programmable functional blocks include: level
shifters, digital to analog converter and the VM_CH[0,1,2,3] voltage dividers.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
4
SMB113A/B/SMB117/A
Preliminary Information
PIN DESCRIPTION
Pin Number
Pin Type
Pin Name
1
OUT
HSDRV_CH0
2
OUT
HEALTHY
(nRESET)
3
IN
COMP1_CH0
4
IN
COMP2_CH0
5
IN
VM_CH0
6
I/O
SDA
7
IN
SCL
8
OUT
LSDRV_CH1
9
PWR
HVSUP1
10
OUT
HSDRV_CH1
11
IN
HOST_RESET
12
IN
COMP1_CH1
13
IN
COMP2_CH1
Summit Microelectronics, Inc
Pin Description
The HSDRV_CH0 (Channel 0 High-side Driver) pin is the upper
switching node of the channel 0 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH0 and assertion of
LSDRV_CH0 to prevent excessive current flow during switching.
The HEALTHY pin is an open drain output. High when all
enabled output supplies are within the programmed levels.
HEALTHY will ignore any disabled supply.
There is a
programmable glitch filter on the under-voltage and over-voltage
sensors so that short transients outside of the limits will be
ignored by HEALTHY. This pin can also be programmed to act
as a Reset Output (nRESET). In this case, it releases with a
programmable delay after all outputs are valid. When used, this
pin should be pulled high by an external pull-up resistor.
The COMP1_CH0 (Channel 0 primary Compensation) pin is the
primary feedback input of the channel 0 step-down buck
controller. The COMP1_CH0 pin is internally connected to a
programmable resistor divider.
The COMP2_CH0 (Channel 0 secondary Compensation) pin is
the secondary feedback input of the channel 0 step-down buck
controller.
The VM_CH0 (Channel 0 Voltage Monitor) pin connects the
channel 0 step-down controller output. Internally the VM_CH0 pin
connects to a programmable resistor divider.
SDA (Serial Data) is an open drain bi-directional pin used as the
I2C data line. SDA must be tied high through a pull-up resistor.
SCL (Serial Clock) is an open drain input pin used as the I2C
clock line. SCL must be tied high through a pull-up resistor.
The LSDRV_CH1 (Channel 1 Low-side Driver) pin is the lower
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of n-channel MOSFET.
Channel 1 High Voltage Supply for Channel 1 buck driver.
The HSDRV_CH1 (Channel 1 High-side Driver) pin is the upper
switching node of the channel 1 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay
exists between the assertion of HSDRV_CH1 and assertion of
LSDRV_CH1 to prevent excessive current flow during switching.
The HOST_RESET pin is an active high reset input. When this
pin is asserted high, the nRESET output will immediately go low.
When HOST_RESET is brought low, nRESET will go high after a
programmed reset delay. When pin 2 is used as a HEALTHY
output, this pin needs to be attached to GND or VBATT via a
resistor.
The COMP1_CH1 (Channel 1 primary Compensation) pin is the
primary compensation input of the channel 1 step-down buck
controller. The COMP1_CH1 pin is internally connected to a
programmable resistor divider.
The COMP2_CH1 (Channel 1 secondary Compensation) pin is
the secondary compensation input of the channel 1 step-down
buck controller.
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SMB113A/B/SMB117/A
Preliminary Information
PIN DESCRIPTION
Pin Number
Pin Type
Pin Name
14
IN
VM_CH1
15
CAP
VDD_CAP
16
PWR
VBATT
17
OUT
LSDRV_CH2
18
PWR
HVSUP2
19
OUT
HSDRV_CH2
20
IN
COMP2_CH2
21
IN
COMP1_CH2
22
IN
VM_CH2
23
OUT
LSDRV_CH3
24
PWR
HVSUP3
25
OUT
HSDRV_CH3
26
IN
PWREN
27
IN
COMP2_CH3
28
IN
COMP1_CH3
Summit Microelectronics, Inc
Pin Description
The VM_CH1 (Channel 1 Voltage Monitor) pin connects the channel 1
step-down controller output. Internally the VM_CH1 pin connects to an
internal programmable resistor divider.
The VDD_CAP (VDD Capacitor) pin is an external capacitor input used
to filter the internal supply.
Power supply to part.
The LSDRV_CH2 (Channel 2 Low-side Driver) pin is the lower
switching node of the channel 2 synchronous step-down buck
controller. Attaches to the gate of n-channel MOSFET.
Channel 2 High Voltage Supply for Channel 2 buck driver.
The HSDRV_CH2 (Channel 2 High-side Driver) pin is the upper
switching node of the channel 2 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay exists
between the assertion of HSDRV_CH2 and assertion of LSDRV_CH2
to prevent excessive current flow during switching.
The COMP2_CH2 (Channel 2 secondary Compensation) pin is the
secondary compensation input of the channel 2 step-down buck
controller.
The COMP1_CH2 (Channel 2 primary Compensation) pin is the
primary compensation input of the channel 2 step-down buck
controller. Each pin is internally connected to a programmable resistor
divider.
The VM_CH2 (Channel 2 Voltage Monitor) pin connects the channel 6
step-down controller output. Internally the VM_CH2 pin connects to an
internal programmable resistor divider.
The LSDRV_CH3 (Channel 3 Low-side Driver) pin is the lower
switching node of the channel 3 synchronous step-down buck
controller. Attaches to the gate of n-channel MOSFET.
Channel 3 High Voltage Supply for Channel 3 buck driver.
The HSDRV_CH3 (Channel 3 High-side Driver) pin is the upper
switching node of the channel 3 synchronous step-down buck
controller. Attach to the gate of p-channel MOSFET. A delay exists
between the assertion of HSDRV_CH3 and assertion of LSDRV_CH3
to prevent excessive current flow during switching.
The PWREN (Power Enable) pin is a programmable input used to
enable (disable) selected supplies. This pin can also be programmed
to latch and act as a debounced, manual push button input. Active high
when level triggered, active low when used as a push- button input.
When unused this pin should be tied to a solid logic level.
The COMP2_CH3 (Channel 3 secondary Compensation) pin is the
secondary compensation input of the channel 3 step-down buck
controller.
The COMP1_CH3 (Channel 3 primary Compensation) pin is the
primary compensation input of the channel 3 step-down buck
controller. Each pin is internally connected to a programmable resistor
divider.
2111 2.4 6/24/2008
6
SMB113A/B/SMB117/A
Preliminary Information
PIN DESCRIPTION
Pin Number
Pin Type
Pin Name
Pin Description
29
IN
VM_CH3
The VM_CH3 (Channel 3 Voltage Monitor) pin connects the channel 3
step-down controller output. Internally the VM_CH3 pin connects to an
internal programmable resistor divider.
30
PWR
GND
31
OUT
LSDRV_CH0
32
PWR
HVSUP0
PAD
PWR
GND
Summit Microelectronics, Inc
Ground
The LSDRV_CH0 (Channel 0 Low-side Driver) pin is the lower switching
node of the channel 0 synchronous step-down buck controller. Attach to
the gate of n-channel MOSFET.
Channel 0 High Voltage Supply used to power the channel 0 buck
driver.
Exposed metal (thermal) Pad on bottom of SMB113A/B and SMB117/A.
The thermal pad of the QFN package must be connected to the PCB
GND.
2111 2.4 6/24/2008
7
SMB113A/B/SMB117/A
Preliminary Information
PACKAGE AND PIN DESCRIPTION
Top View
30
29
28
27
26
HSDRV_CH3
PWREN
COMP2_CH3
COMP1_CH3
31
VM_CH3
LSDRV_CH0
32
GND
HVSUP0
SMB113A/B/SMB117/A
5mm x 5mm QFN-32
25
HSDRV_CH0
1
24
HVSUP3
HEALTHY
(nRESET)
2
23
LSDRV_CH3
COMP1_CH0
3
22
VM_CH2
COMP2_CH0
4
21
COMP1_CH2
VM_CH0
5
20
COMP2_CH2
SDA
6
19
HSDRV_CH2
SCL
7
18
HVSUP2
LSDRV_CH1
8
17
LSDRV_CH2
Summit Microelectronics, Inc
14
VM_CH1
2111 2.4 6/24/2008
15
16
VBATT
13
VDD_CAP
12
COMP2_CH1
11
HOST_RESET
10
HSDRV_CH1
HVSUP1
9
COMP1_CH1
GND
8
SMB113A/B/SMB117/A
Preliminary Information
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias .................... -55°C to +125°C
Storage Temperature.......................... -65°C to +150°C
Terminal Voltage with Respect to GND:
VBATT Supply Voltage ................... -0.3V to +6.5V
HVSUP Supply Voltage .................. -0.3V to +6.5V
All Others ...................................... -0.3V to VBATT
Output Short Circuit Current .................…………100mA
Reflow Solder Temperature (30 secs)............... +260°C
Junction Temperature........................................ +150°C
ESD Rating per JEDEC ..................................... +2000V
Latch-Up testing per JEDEC............................. ±100mA
Commercial Temperature Range............... 0°C to +70°C
Industrial Temperature Range ................ -40°C to +85°C
VBATT Supply Voltage ........................... +2.7V to +6.0V
HVSUP Supply Voltage........................... +2.7V to +6.0V
All Others.................................................GND to VBATT
Package Thermal Resistance (θJA), 32-Lead QFN
(thermal pad connected to PCB)....................... 37.2°C/W
Moisture Classification Level 3 (MSL 3) per J-STD-020
RELIABILITY CHARACTERISTICS
Data Retention ................................................ 100 Years
Endurance ................................................ 100,000 Cycle
Temperature Range ................................ -40°C to +85°C
Note - The device is not guaranteed to function outside its operating rating. Stresses listed under Absolute Maximum
Ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions outside those listed in the operational sections of the specification is not
implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
DC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Conditions
Min
Typ
Max
VBATT
Input supply voltage
Input supply voltage (operational)
2.7
6.0
VHVSUP
Buck driver supply voltage
Gate drive voltage
2.7
6.0
VUVLO
Under-voltage lockout
IDD-MONITOR
Monitoring current
IDD-ACTIVE
Active current
VDD_CAP
Internal supply, present on
VDD_CAP pin
VBATT rising
VBATT falling
2.2
1.9
All voltage inputs monitored. No
supplies switching, VBATT at 4.2V.
Total current all channels enabled. No
load. VBATT at 4.2V. Note 2.
2.3
2.0
Unit
V
V
V
V
290
400
µA
1.2
2.0
mA
V
No load
2.4
2.5
2.6
SMB113B
875
1000
1125
SMB113A
720
800
880
SMB117
360
400
440
SMB117A
212
250
288
Oscillator
fOSC
Oscillator frequency
OPP LT
Oscillator peak-to-peak
∆fSV
Frequency stability for voltage
∆fST
Frequency stability for
temperature
Summit Microelectronics, Inc
kHz
1
V
0.1
%/V
+25°C to +70°C, fOSC = 800kHz
0.18
+25°C to +85°C, fOSC = 800kHz
0.22
kHz/°
C
2111 2.4 6/24/2008
9
SMB113A/B/SMB117/A
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol Parameter
Conditions
Min
Typ
Max
Error Amplifier
Unit
AVOL
Open loop voltage Gain
At DC
60
dB
BW
Frequency bandwidth
At AVOL = 0 dB
30
MHz
ISOURCE
Output source current
At 0.5V
20
µA
ISINK
Output sink current
At 0.5V
800
µA
Output Block
VOUT
Voltage set point range.
100% Maximum Duty cycle
∆VOUT
Output accuracy, excluding
external resistor divider1
RDRVH
HSDRV ON resistance
RDRVL
LSDRV ON resistance
VCOMP1
Feedback voltage reference
100% Max Duty Cycle
D.C.
90% Max Duty Cycle
VBATT= 4.2V, ILOAD=0
VOUT = VBATT x (duty cycle)
VBATT= 6.0V, ILOAD=0
VOUT = VBATT x (duty cycle)
0.5
4.2
0.5
6.0
Commercial temperature range
-1.5
+1.5
Industrial temperature range
-2.0
+2.0
V
Output high
2
Output low
2
Output high
2
Output low
2
COMP1 pin
Programmable in 4mV steps
1.0
High Duty Cycle
100
Low Duty Cycle, Note 3
High Duty Cycle, Note 3
Ω
V
35
70
Low Duty Cycle
%
%
0
Logic Levels
VIH
Input high voltage
VIL
Input low
VOL
Open drain outputs
Summit Microelectronics, Inc
ISINK = 1mA
2111 2.4 6/24/2008
0.7 x
VDD_CAP
6.0
V
0
0.3 x
VDD_CAP
V
0
0.4
V
10
SMB113A/B/SMB117/A
Preliminary Information
DC OPERATING CHARACTERISTICS (CONTINUED)
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
2.55
3.60
V
2.55
3.60
V
Programmable Monitoring Thresholds
Programmable UV1 threshold
voltage measured on VBATT pin
in 150 mV increments
Programmable UV2 threshold
voltage measured on VBATT pin
in 150 mV increments
VPUV1
Programmable UV1 threshold
VPUV2
Programmable UV2 threshold
∆VPUV2
UV2 accuracy
±2
%
∆VPUV1
UV1 accuracy
±2
%
PUVTH
POVTH
Programmable under-voltage
threshold
Programmable over-voltage
threshold
Output voltage relative to
nominal operating voltage.
Note 3.
Output voltage relative to
nominal operating voltage.
Note 3.
-3
-5
-7
-8
-10
-12
-12
-15
-18
-16
-20
-24
+3
+5
+7
+8
+10
+12
+12
+15
+18
+16
+20
+24
%
%
Note 1: Voltage accuracies are only guaranteed for factory-programmed settings. Changing the output voltage from that reflected in the customer
specific CSIR code might result in inaccuracies exceeding those specified above by 1%.
Note 2: For more accurate active current levels under several load conditions, Summit’s proprietary design software can be used. Contact the
factory for more information.
Note 3: Guaranteed by Design and Characterization – not 100% tested in Production.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
11
SMB113A/B/SMB117/A
Preliminary Information
AC OPERATING CHARACTERISTICS
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.) Note 4
Symbol
Description
Conditions
Min
Typ
Max
Unit
1.5
12.5
Programmable power-On Programmable
power-on
sequence
tPPTO
ms
sequence timeout period. position to sequence position delay.
25
50
1.5
12.5
Programmable power-off
Programmable power-off sequence
ms
tDPOFF
sequence timeout period. position to sequence position delay.
25
50
Time between active enable in which
OFF
corresponding outputs must exceed there
50
Programmable sequence
programmed under voltage threshold. If
ms
tPST
termination period
100
exceeded, a force shutdown will be
200
initiated.
0
Period for which fault must persist before
Programmable glitch filter
tPGF
µs
fault triggered actions are taken.
8
25
Applicable when HEALTHY pin is used as
50
an nRESET output pin. Programmable
Reset timeout period
tRESET
ms
time following assertion of last supply
100
before nRESET pin is released high.
200
400
200
100
67
Programmable slew rate
Adjustable slew rate factor proportional to
SRREF
V/s
reference
output slew rate.
50
33
25
20
Channels 0 to 3
tRL
LS Driver output rise time
CG=100pF, VBATT=4.2V
4.2
ns
tFL
LS Driver output fall time
CG=100pF, VBATT=4.2V
4.2
ns
tRL
HS Driver output rise time
CG=100pF, VBATT=4.2V
2.9
ns
tFL
HS Driver output fall time
CG=100pF, VBATT=4.2V
2.9
ns
tDT
Driver non-overlap delay
High to low transition on HSDRV
30
Low to high transition on buck HSDRV
60
ns
Note 4: Timing specifications are 20% shorter for the SMB113B device and 60% longer for SMB117A.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
12
SMB113A/B/SMB117/A
Preliminary Information
I2C-2 WIRE SERIAL INTERFACE AC OPERATING CHARACTERISTICS – 100 kHz
(Over recommended operating conditions, unless otherwise noted. All voltages are relative to GND.)
100kHz
Symbol
Description
Conditions
Min
Typ
Max Units
fSCL
SCL clock frequency
0
TLOW
Clock low period
4.7
µs
THIGH
Clock high period
4.0
µs
tBUF
Bus free time
4.7
µs
tSU:STA
Start condition setup time
4.7
µs
tHD:STA
Start condition hold time
4.0
µs
tSU:STO
Stop condition setup time
4.7
µs
tAA
Clock edge to data valid
tDH
Data output hold time
tR
SCL and SDA rise time
SCL low to valid SDA (cycle
n)
SCL low (cycle n+1) to SDA
change
Note 5
tF
SCL and SDA fall time
Note 5
tSU:DAT
Data in setup time
250
ns
tHD:DAT
Data in hold time
0
ns
TI
Noise filter SCL and SDA
Noise suppression
tWR_CONFIG
Write cycle time config
Configuration registers
10
ms
tWR_EE
Write cycle time EE
Memory array
5
ms
Before new transmission –
Note 5
100
0.2
kHz
3.5
µs
0.2
µs
1000
ns
300
ns
136
ns
Note 5: Guaranteed by Design.
TIMING DIAGRAMS
tR
tF
tSU:STA
tHD:STA
tHIGH
tWR (For Write Operation Only)
tLOW
SCL
tHD:DAT
tSU:DAT
tSU:STO
tBUF
SDA (IN)
tAA
tDH
SDA (OUT)
Figure 4 – I2C timing diagram
Summit Microelectronics, Inc
2111 2.4 6/24/2008
13
SMB113A/B/SMB117/A
Preliminary Information
SMB113A EFFICIENCY GRAPHS
Efficiency at 3.3V
Efficiency at 2.5V
95
95
Efficiency (%)
100
Efficiency (%)
100
90
90
85
85
80
80
75
75
5.0V
4.2V
70
5.0V
4.2V
3.8V
3.6V
3.3V
3.0V
70
3.8V
65
65
3.6V
3.4V
60
0
0.5
1
1.5
60
0
2
Current (Amps)
0.5
1
1.5
2
Current (Amps)
Efficiency at 1.8V
100
Efficiency (%)
95
90
85
80
75
5.0V
4.2V
3.8V
3.6V
3.3V
3.0V
70
65
60
Efficiency at 1.5V
0
0.5
1
1.5
2
Current (Amps)
100
95
Efficiency (%)
95
Efficiency (%)
Efficiency at 1.2V
100
90
85
80
5.0V
4.2V
3.8V
3.6V
3.3V
3.0V
75
70
65
60
0
0.5
1
1.5
85
80
75
5.0V
3.8V
4.2V
3.6V
3.3V
3.0V
70
65
60
2
0
Current (Amps)
Summit Microelectronics, Inc
90
0.5
1
1.5
2
Current (Amps)
2111 2.4 6/24/2008
14
SMB113A/B/SMB117/A
Preliminary Information
SMB117 EFFICIENCY GRAPHS
Efficiency at 1.2V, 1.8V, 2.5V, 3.3V
100
90
Efficiency (%)
80
70
1.2V
60
1.8V
50
2.5V
40
3.3V
30
20
10
Vin = 5.0 Volts
0
0
2
4
6
Current (Amps)
8
10
12
Buck 2.5V
Summit Microelectronics, Inc
2111 2.4 6/24/2008
15
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION
DEVICE OPERATION
POWER SUPPLY
There are five supply input pins on the SMB113A/B
and SMB117/A: four HVSUP pins and the VBATT pin.
Each supply must be powered from an input voltage
between 2.7-6.0 volts.
The HVSUP1 though HVSUP4 are used to power the
HSDRV (PMOS driver) and LSDRV (NMOS driver)
outputs. The rail-to-rail swing on the HSDRV and
LSDRV pins is equal to the associated HVSUP supply
voltage.
The VBATT pin is internally regulated to 2.5V. This
2.5V supply is then filtered on the VDD_CAP pin and
used to power all internal circuitry. The VBATT pin is
monitored by an Under-Voltage Lockout (UVLO)
circuit, which prevents the device from turning on
when the voltage at this node is less than the UVLO
threshold.
OUTPUT VOLTAGE
All output voltages on the SMB113A/B and SMB117/A
can be set via the non-volatile configuration registers.
Each of the four step-down output voltages on the
SMB113A/B and SMB117/A can be adjusted for 100%
duty cycle or 0% duty cycle operation.
When 100% duty cycle mode is selected, the output
voltage can be set up to the input voltage on the
device, while the minimum output voltage is limited to
the min duty cycle specification in the DC operating
characteristics section.
When the 0% duty cycle mode is selected, the
maximum duty cycle is limited to the max duty cycle
specification in the DC operating characteristics
section.
POWER-ON/OFF CONTROL
Sequencing can be initiated: automatically, by a
volatile I2C Power on command, or by asserting the
PWREN pin. When the PWREN pin is programmed to
initiate sequencing, it can be level or edge triggered.
The PWREN input has a programmable de-bounce
time of 100, 50, or 25ms. The de-bounce time can also
be disabled.
When configured as a push-button enable, PWREN
must be asserted longer than the de-bounce time
before sequencing can commence, and pulled low for
the same period to disable the channels.
ENABLE
Each output can be enabled and disable by an enable
signal. The enable signal is can be provided from
Summit Microelectronics, Inc
either the PWREN pin or by the contents of the enable
register.
When enabling a channel from the enable register, the
register contents default state must be set so that the
output will be enabled or disabled following a POR
(power on reset). The default state is programmable.
CASCADE SEQUENCING
Each channel on the SMB113A/B and SMB117/A may
be placed in any one of 4 unique sequence positions,
as assigned by the configurable non-volatile register
contents. The SMB113A/B and SMB117/A navigate
between each sequence position using a feedbackbased
cascade-sequencing
circuit.
Cascade
sequencing is the process in which each channel is
continually compared against a programmable
reference voltage until the voltage on the monitored
channel exceeds the reference voltage, at which point
an internal sequence position counter is incremented
and the next sequence position is entered. In the
event that a channels enable input is not asserted
when the channel is to be sequenced on, that
sequence position will be skipped and the channel in
the next sequence position will be enabled.
Figure 5 – Power on sequencing waveforms.
Time = 4ms/devision, Scale = 1V/devision
Ch 1 = 3.3V output (Yellow trace)
Ch 2 = 2.5V output (Blue trace)
Ch 3 = 1.8V output (Purple trace)
Ch 4 = 1.2V output (Green trace)
POWER ON/OFF DELAY
There is a programmable delay between when
channels in subsequent sequence positions are
enabled. The delay is programmable at 50, 25, 12.5
and 1.5ms intervals. This delay is programmable for
each
of
the
four
sequence
positions.
2111 2.4 6/24/2008
16
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
MANUAL MODE
The SMB113A/B and SMB117/A provide a manual
power-on mode in which each channel may be
enabled individually irrespective of the state of other
channels. In this mode, the enable signal has
complete control over the channel, and all sequencing
is ignored. In Manual mode, channels will not be
disabled in the event of a UV/OV fault on any output or
the VBATT pin.
FORCE-SHUTDOWN
When a battery fault occurs, a UV/OV is detected on
any output, or an I2C force-shutdown command is
issued, all channels will be immediately disabled,
ignoring sequence positions or power off delay times.
SEQUENCE TERMINATION TIMER
At the beginning of each sequence position, an
internal programmable timer will begin to time out.
When this timer has expired, the SMB113A/B and
SMB117/A will automatically perform a force-shutdown
operation. This timer is user programmable with a
programmable sequence termination period (tPST) of
50, 100, 200 ms; this function can also be disabled.
POWER OFF SEQUENCING
The SMB113A/B and SMB117/A have a power-off
sequencing operation. During a power off operation,
the supplies will be powered off in the reverse order
they where powered on in. During the power off
sequencing, all enables are ignored.
When a power-off command is issued the SMB113A/B
and SMB117/A will set the sequence position counter
to the last sequence position and disable that channel
without soft-start control; once off, the power off delay
for the channel(s) in the next to last sequence position
will begin to timeout, after which that channel(s) will be
disabled. This process will continue until all channels
have been disabled and are off. The programmable
If a channel fails to turn off within the sequence
termination period, the sequence termination timer will
initiate a force shutdown, if enabled.
INPUT AND OUTPUT MONITORING
Both products monitor all outputs for under-voltage
(UV) and over-voltage (OV) faults. The monitored
levels are user programmable, and may be set at 5,
10, 15, and 20 percent of the nominal output voltage.
The VBATT pin is monitored for two user
programmable UV settings. The VBATT UV settings
are programmable from 2.55V to 3.45V in 150mV
increments. Once the UV/OV voltage set points have
been violated, the SMB113A/B and SMB117/A can be
programmed to respond in one of three ways, perform:
Summit Microelectronics, Inc
a power-off operation, a force-shutdown operation
and-or it can trigger the nRESET/HEALTHY pin.
SOFT START
The SMB113A/B and SMB117/A provide a
programmable soft-start function for all PWM outputs.
The soft-start control limits the slew rate that each
output is allowed to ramp up without the need for an
external capacitor. The soft start slew rate is
proportional to the product of the output voltage and a
slew rate reference. This global reference is
programmable and may be set to 400, 200, 100, 67,
50, 33, 25, and 20 Volts per second. The slew rate
control can also be disabled on any channel not
requiring the feature.
DYNAMIC VOLTAGE MANAGEMENT
The SMB113A/B/117/A have two additional voltage
settings, dynamic voltage control high and low
settings. Together with the nominal voltage setting,
three pre-determined voltage levels can be used. The
three voltage levels are ideal for situations where a
core voltage needs to be reduced for power
conservation.
The dynamic voltage control high and low settings
have the same voltage range as the controllers’
nominal output voltage. These settings are stored in
the non-volatile configuration registers and can be set
by a write to volatile configuration registers. The
dynamic voltage control command registers contain
two bits for each channel that adjust the output
voltages to the high, low or nominal set point after a
volatile I2C write command.
A seven level dynamic voltage control option is
available for channel 3. When enabled, seven level
dynamic voltage control allows channel 3 to be
dynamically modified to one of seven pre-determined
voltage levels. This transition is made by means of a
volatile I2C write command.
When all channels are at their voltage setting, a bit is
set in the dynamic voltage control status registers.
Vout
R2
R1
COMP1
VREF
+
–
Soft-Start Slew Rate=SRref* (1 + R2/R1)
Vout= Vref* (1 + R2/R1)
Figure 6 – The output voltage is set by the voltage
divider. The VREF voltage is programmable from 0
to 1.0 volt in 4mV increments via the I2C interface
2111 2.4 6/24/2008
17
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION
High Voltage Operation:
While the SMB113A has a max input voltage of 6.0V
the controller can operate to0 much higher voltages by
using the circuit depicted below. By inserting a
capacitor, C1, in series with the HSDRV gate signal
the HSDRV pin is isolated from the 12V supply, and
the AC coupling capacitor acts as a level translator
transferring the 0-5V signal from the HSDRV pin to a
12V to 7V (12V-5V = 7V) signal at the gate of the
PFET. When the gate stops switching the capacitor
12V
5V
becomes an open circuit and the gate will be pulled
high by R1 turning off the output. The schottky diode
and the pull-up resistor are used for DC restoration
and as a pull-up respectively.
Since the converter runs directly from the input supply
(12V in this instance) the efficiency is consistent with
that of a synchronous converter. Typical efficiency
curves are shown below.
All power comes directly from 12V supply
7V
HSDRV
time
C1
time
0.1uF
Schottky
Q2(P)
+12V
Q6
AC Coupling capacitor
DC Restoration
R1
1K
C28
22uF
L1
C33
0.1uF
Q1(N)
NP
FDC6420C
LSDRV
1
3.3uH
C45
C51
22uF
0.1uF
Vout
Figure 7 – High-voltage operation
Summit Microelectronics, Inc
2111 2.4 6/24/2008
18
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Figure 8 – SMB113A applications schematic.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
19
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Item
Description
Vendor / Part Number
Qty Ref. Des.
Resistors
1
300Ω, 1/16W, 1%, 0603, SMD
Vishay CRCW06033000F
4
R1, R4, R6, R8
2
6.04KΩ, 1/16W, 1%, 0603, SMD
Vishay CRCW06036041F
1
R2
3
4.99KΩ, 1/16W, 1%, 0603, SMD
Vishay CRCW06034991F
2
R3, R5
4
6.98KΩ, 1/16W, 1%, 0603, SMD
Vishay CRCW06036981F
1
R7
5
47Ω, 1/16W, 1%, 0603, SMD
Vishay CRCW06034702F
5
6
3Ω, 1/16W, 1%, 0603, SMD
Vishay CRCW06033R01F
8
7
8
10KΩ, 1/16W, 1%, 0603, SMD
300Ω, 1/16W, 1%, 0603, SMD
Vishay CRCW06031002F
Vishay CRCW06031000F
1
4
R9, R18, R19, R20, R21
R10, R11, R12, R13,
R14, R15, R16, R17
R20
R22, R23, R24, R27
Capacitors
0.1uF, 16V, ceramic, X7R, 0603, SMD
9
Kemet C0603C104K4RACTU
15
C1, C3, C6, C8, C16,
C21, C26, C28, C31,
C33, C34, C36, C38,
C40, C42
10
1uF, 10V, ceramic, Y5V, 0603, SMD
Panasonic ECJ-1VF1A105Z
2
C2, C35
11
12
10uF, 6.3V, ceramic, X5R, 0805, SMD
10uF, 25V, ceramic, X7R, 1210, SMD
9
4
C4, C25, C27, C29, C37
C5, C7, C15, C20,
13
330pF, 50V, ceramic, C0G, 0603, SMD
1
C9
14
120pF, 50V, ceramic, C0G, 0603, SMD
Kemet C0805C106K9PACTU
TDK C3225X7R1E106M
Murata
GRM1885C2A331JA01D
Vishay VJ0603A121KXAA
Murata
GRM188R72A681KA01D
Panasonic ECJ-1VC1H470J
Kemet C0603C471K5RACTU
Murata
GRM1885C2A331JA01D
Murata
GRM188R72A221KA01D
Vishay VJ0603A102KXAA
2
C10, C18
2
C11, C22
1
2
C13
C17, C12
2
C14, C19
680pF, 100V, ceramic, X7R, 0603, SMD
15
16
47pF, 50V, ceramic, NP0, 0603, SMD
470pF, 50V, ceramic, X7R, 0603, SMD
17
820pF, 50V, ceramic, C0G, 0603, SMD
18
19
220pF, 50V, ceramic, C0G, 0603, SMD
1000pF, 50V, ceramic, C0G, 0603, SMD
1
1
C23
C24
Semiconductors
20
MOSFET, Complementary
Fairchild, FDC6420C
4
Q1-Q4
21
SMB113ANC
Summit Microelectronics
1
U1
Sumida CDR7D28MNNP6R8NC
4
L1-4
Magnetics
22
Inductor, 6.8uH, 2.75A, SMD, Shielded
Summit Microelectronics, Inc
2111 2.4 6/24/2008
20
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
D1 Schottky VIN
Q2(P)
C12
0.1uF
R4 1K
C16
22uF
C17
0.1uF
Q5
FDC6420C
L1
R5 0
1
Q1(N)
3.3uH
D8
VBATT
U1
2
1
1
11
PWREN0
1
26
Optional Push-Button Enable
HOST_RESET
+12V VIN
1
SW1
C25
0.1uF
R10
1K
Q1
NPN
6
SDA
7
SCL
SMB113A
HSDRV_CH0
LSDRV_CH0
COMP1_CH0
COMP2_CH0
VM_CH0
HVSUP0
HEALTHY
VBATT
1
C15
C14
1uF
0.1uF 1uF
C2
PWREN0
SDA
SCL
GND
VBATT
VDDCAP
HSDRV_CH3
LSDRV_CH3
COMP1_CH3
COMP2_CH3
VM_CH3
HVSUP3
10
8
12
13
14
9
C18
0.1uF
C1
19
17
21
20
22
18
1K
L2
C22
0.1uF
C20
22uF
Q1(N)
R13 0
25
23
28
27
29
24
C37
SDA
SCL
I2C
C35
22uF
0.1uF
C40
C41
22uF
0.1uF
C46
C47
22uF
0.1uF
22pF
3300pF
R14 100
Q2(P)
0.1uF
Q3
C11
0.1uF
R16 1K
C29
0.1uF
C27
22uF
L3
Q1(N)
NP
FDC6420C
D10 3.3uH
C13
0.1uF
DongleVCC
9
7
5
3
1
CH1
C34
R23 499
R22 4.99K C38
DongleVCC
Rsrv10
+5V
Rsrv8
+10V
MR
Rsrv5
SDA
Gnd3
SCL
Gnd
1
C36
330pF
D5 Schottky VIN
Optional For Programming SMB113A
10
8
6
4
2
3.3uH
D9
0.1uF
J1
R3 100
Q4
FDC6420C
R12
C24
R30
47K
3300pF
D3 Schottky VIN
VBATT
R7
47K
CH0
R2 499
R1 4.99K C10
30
15
0.1uF
22pF
Q2(P)
HSDRV_CH1
LSDRV_CH1
COMP1_CH1
COMP2_CH1
VM_CH1
HVSUP1
VBATT
16
C9
1
31
3
4
5
32
HOST_RESET
HSDRV_CH2
LSDRV_CH2
COMP1_CH2
COMP2_CH2
VM_CH2
HVSUP2
D7
5.6V
C7
22uF
C8
330pF
R9
49.9K
HEALTHY/nRESET
C5
D2
VBATT
R17 0
C43
22pF
1
C42
330pF
CH2
R25 499
C19
0.1uF
R24 4.99K C44
3300pF
R37 100
C21
0.1uF
Q2
D6 Schottky
C30
Q2(P)
VIN
0.1uF
R19 1K
C31
22uF
C32
0.1uF
L4
Q1(N)
FDC6420C
D11 3.3uH
1
C48
330pF
R20 0
C49
CH3
22pF
R29 499
R28 4.99K C50
3300pF
R39 100
Figure 9 – Applications schematic showing SMB113A operation from a +12V input supply.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
21
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Item
Description-
Vendor / Part Number
Qty
Ref. Des.
Capacitors
1
2
3
4
5
6
0.1uF, 50V, ceramic, X7R, 0603, SMD
Murata
GRM188R71H104KA93D
Murata
GRM216R61E105KA12
Murata
22uF, 16V, ceramic, X5R, 1210, SMD
GRM32ER61C226ME20L
330pF, 50V, ceramic, NP0, 0603, SMD
Panasonic ECJ-1VC1H331J
Murata
22pF, 50V, ceramic, NP0, 0603, SMD
GRM1885C1H470JA01D
Murata
3300pF, 100V, ceramic, X7R, 0603, SMD
GRM188R71H332KA01D
1uF, 25V, ceramic, X5R, 0805, SMD
19
C1, C3, C7, C11, C13,
C12, C14, C17, C18, C19,
C21, C22, C24, C25, C29,
C30, C32, C35, C41, C47
2
C2, C15
4
C5, C16, C20, C27, C31,
C34, C40, C46
C8, C36, C42, C48
4
C9, C37, C43, C49
2
C10, C38, C44, C50
9
Resistors
7
499Ω, 1/10W, 1%, 0603, SMD
Vishay CRCW06034990F
4
R2, R23, R25, R29
8
9
10
11
12
100Ω, 1/10W, 1%, 0603, SMD
1KΩ, 1/10W, 1%, 0603, SMD
0Ω, 1/10W, 1%, 0603, SMD
49.9KΩ, 1/10W, 1%, 0603, SMD
2KΩ, 1/10W, 1%, 0603, SMD
Vishay CRCW06031000F
Vishay CRCW06031001F
Vishay CRCW06030R00F
Vishay CRCW06034992F
Vishay CRCW06032001F
4
5
4
4
1
R3, R14, R37, R39
R4, R10, R12, R16, R19
R5, R13, R17, R20
R6, R7, R8, R30
R9
13
4.99KΩ, 1/10W, 1%, 0603, SMD
Vishay CRCW06034991F
4
R1, R22, R24, R28
Semiconductors
14
15
Diode Schottky, 20V, 200mA, SS-mini
Panasonic MA2SD2400L
4
D1, D3, D5, D6
Diode, Schottky, 40V, 500mA SOD-123
5
D2, D12, D13, D14, D15
16
LED, Red, 0805, SMD
2
D4
17
Zener Diode, 5.6V, 500mW, SOD-123
Diodes Inc. B0540W-7
Lumex SML-LXT0805SRWTR
ON Semi MMSZ5V6T1G
1
D7
18
NPN, 40V, 1A, SOT-89
Zetex FCX491A
1
Q1
19
20
MOSFET, Complementary, 20V, SSOT-6 Analog Power AM3520C
4
Q2, Q3, Q4, Q5
SMB113A
Summit Microelectronics
1
U1
TDK HCP0703-3R3-R
4
L1, L2, L3, L4
Magnetics
21
Inductor 3.3uH
Summit Microelectronics, Inc
2111 2.4 6/24/2008
22
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Q12
5
6
7
8
4
R11 0
VBATT
D8
1
2
3
C17
0.1uF
C16
22uF
FDS6675BZ
Q13
5
6
7
8
4
R5 0
VBATT
SMB117
2
1
11
PWREN0
1
26
7
SCL
HSDRV_CH1
LSDRV_CH1
COMP1_CH1
COMP2_CH1
VM_CH1
HVSUP1
PWREN0
SDA
15
C15
C14
1uF
0.1uF 1uF
C2
VBATT
VDDCAP
HSDRV_CH3
LSDRV_CH3
COMP1_CH3
COMP2_CH3
VM_CH3
HVSUP3
C1
C9
22pF
C7
22uF
0.1uF
CH0
C10
3300pF
R2 499
R1 10K
R3 100
10
8
12
13
14
9
Q10
5
6
7
8
4
19
17
21
20
22
18
VBATT
FDS6675BZ
C22
0.1uF
C20
22uF
Q11
5
6
7
8
4
25
23
28
27
29
24
D9
1
2
3
R13 0
L2
1
1
2
3
2.0uH
FDS6680AS
VBATT
C11
0.1uF
CH1
C34
C35
22uF
0.1uF
C40
C41
22uF
0.1uF
C46
C47
22uF
0.1uF
C36
330pF
0.1uF
Optional For Programming SMB113A
C5
C8
330pF
R15 0
SCL
VBATT
16
1
31
3
4
5
32
HOST_RESET
HSDRV_CH2
LSDRV_CH2
COMP1_CH2
COMP2_CH2
VM_CH2
HVSUP2
1
VBATT
HEALTHY
GND
TP15
6
SDA
HSDRV_CH0
LSDRV_CH0
COMP1_CH0
COMP2_CH0
VM_CH0
HVSUP0
30
Optional Push-Button Enable
1
HOST_RESET
SW1
1
2.0uH
FDS6680AS
U1
R9
2K
HEALTHY/nRESET
L1
1
2
3
C37
22pF
C38
3300pF
R23 499
R22 10K
R14 100
DongleVCC
C13
0.1uF
R7
47K
SDA
SCL
R30
47K
DongleVCC
J1
10
8
6
4
2
Rsrv10
+5V
Rsrv8
+10V
MR
Rsrv5
SDA
Gnd3
SCL
Gnd
9
7
5
3
1
D2
Q6
VBATT
5
6
7
8
4
R18 0
VBATT
1
2
3
C19
0.1uF
I2C
FDS6675BZ
C29
0.1uF
C27
22uF
Q7
4
C21
0.1uF
D10
R17 0
5
6
7
8
L3
1
1
2
3
2.0uH
FDS6680AS
CH2
C42
330pF
C43
22pF
C44
3300pF
R25 499
R24 10K
R37 100
Q8
5
6
7
8
4
R21 0
VBATT
D11
1
2
3
C31
22uF
C32
0.1uF FDS6675BZ
Q9
5
6
7
8
4
R20 0
L4
CH3
1
1
2
3
2.0uH
FDS6680AS
C49
22pF
C50
3300pF
C48
330pF
R29 499
R28 10K
R39 100
Figure 10 – Applications schematic showing SMB117 operation from a +5V input supply with 10A output
current capability.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
23
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
Item
Description-
Vendor / Part Number
Qty
Ref. Des.
19
C1, C3, C7, C11, C13,
C12, C14, C17, C18, C19,
C21, C22, C24, C25, C29,
C30, C32, C35, C41, C47
2
C2, C15
Capacitors
0.1uF, 50V, ceramic, X7R, 0603, SMD
1
Murata
GRM188R71H104KA93D
Murata
GRM216R61E105KA12
Murata
22uF, 16V, ceramic, X5R, 1210, SMD
GRM32ER61C226ME20L
330pF, 50V, ceramic, NP0, 0603, SMD
Panasonic ECJ-1VC1H331J
Murata
22pF, 50V, ceramic, NP0, 0603, SMD
GRM1885C1H470JA01D
Murata
3300pF, 100V, ceramic, X7R, 0603, SMD
GRM188R71H332KA01D
1uF, 25V, ceramic, X5R, 0805, SMD
2
3
4
5
6
4
C5, C16, C20, C27, C31,
C34, C40, C46
C8, C36, C42, C48
4
C9, C37, C43, C49
2
C10, C38, C44, C50
9
Resistors
7
499Ω, 1/10W, 1%, 0603, SMD
Vishay CRCW06034990F
4
8
9
10
11
12
100Ω, 1/10W, 1%, 0603, SMD
1KΩ, 1/10W, 1%, 0603, SMD
Vishay CRCW06031000F
Vishay CRCW06031001F
0Ω, 1/10W, 1%, 0603, SMD
49.9KΩ, 1/10W, 1%, 0603, SMD
2KΩ, 1/10W, 1%, 0603, SMD
Vishay CRCW06030R00F
Vishay CRCW06034992F
Vishay CRCW06032001F
4
5
4
4
1
R2, R23, R25, R29
R3, R14, R37, R39
R4, R10, R12, R16, R19
R5, R13, R17, R20
R6, R7, R8, R30
R9
13
10KΩ, 1/10W, 1%, 0603, SMD
Vishay CRCW06031002F
4
R1, R22, R24, R28
5
D2, D12, D13, D14, D15
2
D4
Semiconductors
14
Diode, Schottky, 40V, 500mA SOD-123
15
LED, Red, 0805, SMD
16
MOSFET, NFET, 20V, SOT-8
Diodes Inc. B0540W-7
Lumex SML-LXT0805SRWTR
Fairchild FDS6680AS
17
MOSFET, PFET, 20V, SOT-8
SMB117
Fairchild FDS6675BZ
Summit Microelectronics
4
Q6, Q8, Q10, Q12
1
U1
Wurth 744314200
4
L1, L2, L3, L4
18
Q7, Q9, Q11, Q13
Magnetics
19
Inductor 2.0uH
Summit Microelectronics, Inc
2111 2.4 6/24/2008
24
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
COMPONENT SELECTION
Buck Outputs:
Inductor:
The starting point design of any and DC/DC converter
is the selection of the appropriate inductor for the
application. The optimal inductor value will set the
inductor current at 30% of the maximum expected load
current. The inductors current for a Buck converter is
as follows:
Buck: Equation 1:
L=
Vo(V IN − Vo)
Vin * 0.3 * I MAX * f
Where Vo is the output voltage, VIN is the input
voltage, f is the frequency, and IMAX is the max load
current.
For example: For a 1.2V output and a 3.6V input with
a 500mA max load, and a 1MHz switching frequency
the optimal inductor value is:
L=
1.2(3.6 − 1.2)
= 5.3uH
3.6 * 0.3 * 0.5 * 1E 6
Choosing the nearest standard inductor value we
select a 5.6uH inductor. It is important that the inductor
has a saturation current level greater than 1.2 times
the max load current.
Other parameters of interest when selecting an
inductor are the DCR (DC winding resistance). This
has a direct impact on the efficiency of the converter.
In general, the smaller the size of the inductor is the
larger the resistance. As the DCR goes up the power
loss increases according to the I2R relation. As a result
choosing a correct inductor is often a trade off
between size and efficiency.
Input Capacitor
Each converter should have a high value low
impedance input (or bulk) capacitor to act as a current
reservoir for the converter stage. This capacitor should
be either a X5R or X7R MLCC (multi-layer-ceramic
capacitor). The value of this capacitor is normally
chosen to reflect the ratio of the input and output
voltage with respect to the output capacitor. Typical
values range from 2.2uF to 10uF.
For Buck converters, the input capacitor supplies
square wave current to the inductor and thus it is
critical to place this capacitor as close to the PFET as
Summit Microelectronics, Inc
possible in order to minimize trace inductance that
would otherwise limit the rate of change of the current.
Output capacitor
Each converter should have a high value low
impedance output capacitor to act as a current
reservoir for current transients and to. This capacitor
should be either a X5R or X7R MLCC.
For a Buck converter, the value of this capacitance is
determined by the maximum expected transient
current. Since the converter has a finite response time,
during a load transient the current is provided by the
output capacitor. Since the voltage across the
capacitor drops proportionally to the capacitance, a
higher output capacitor reduces the voltage drop until
the feedback loop can react to increase the voltage to
equilibrium.
The voltage drop can be calculated according to:
Equation 2:
V =
I *T
C
Where I is the load or transient current, T is the time
the output capacitor is supporting the output and C is
the output capacitance. Typical values range from
10uF to 44uF.
Other important capacitor parameters include the
Equivalent Series Resistance (E.S.R) of the capacitor.
The ESR in conjunction with the ripple current
determines the ripple voltage on the output, for typical
values of MLCC the ESR ranges from 2-10mΩ. In
addition, carful attention must be paid to the voltage
rating of the capacitor the voltage rating of a capacitor
must never be exceeded. In addition, the DC bias
voltage rating can reduce the measured capacitance
by as much as 50% when the voltage is at half of the
max rating, make sure to look at the DC bias de-rating
curves when selecting a capacitor.
MOSFETS
When selecting the appropriate FET to use attention
must be paid to the gate to source rating, input
capacitance, and maximum power dissipation.
Most FETs are specified by an on resistance (RDSON)
for a given gate to source voltage (VGS). It is essential
to ensure that the FETs used will always have a VGS
voltage grater then the minimum value shown on the
datasheet. It is worth noting that the specified VGS
voltage must not be confused with the threshold
voltage of the FET.
2111 2.4 6/24/2008
25
SMB113A/B/SMB117/A
Preliminary Information
APPLICATIONS INFORMATION (CONTINUED)
The input capacitance must be chosen such that the
rise and fall times specified in the datasheet do not
exceed ~5% of the switching period.
To ensure the maximum load current will not exceed
the power rating of the FET, the power dissipation of
each FET must be determined. It is important to look
at each FET individually and then add the power
dissipation of complementary FETs after the power
dissipation over one cycle has been determined. The
Power dissipation can be approximated as follows:
Equation 3:
2
P ~ R DSON * I L * TON
Where TON is the on time of the primary switch. TON
can be calculated as follows:
Summit Microelectronics, Inc
Equations 4, 5:
Buck − NFET : (1 −
Buck − PFET :
VO
) *T
VIN
VO
*T
VIN
Compensation:
Summit provides a design tool to called Summit Power
Designer” that will automatically calculate the
compensation values for a design or allow the system
to be customized for a particular application. The
power designer software can be found at
http://www.summitmicro.com/prod_select/xls/SummitP
owerDesigner_Install.zip.
2111 2.4 6/24/2008
26
SMB113A/B/SMB117/A
Preliminary Information
DEVELOPMENT HARDWARE & SOFTWARE
device is then configured on-screen via an intuitive
graphical user interface employing drop-down menus.
The end user can obtain the Summit SMX3200
parallel port programming system or the I2C2USB
(SMX3201) USB programming system for device
prototype development. The SMX3200(1) system
consist of a programming Dongle, cable and
WindowsTM GUI software. It can be ordered on the
website or from a local representative. The latest
revisions of all software and an application brief
describing the SMX3200 and SMX3201 are available
from the website (http://www.summitmicro.com).
The Windows GUI software will generate the data and
send it in I2C serial bus format so that it can be directly
downloaded to the SMB113A/B or SMB117/A via the
programming Dongle and cable. An example of the
connection interface is shown in Figure 11.
When design prototyping is complete, the software
can generate a HEX data file that should be
transmitted to Summit for approval. Summit will then
assign a unique customer ID to the HEX code and
program production devices before the final electrical
test operations.
This will ensure proper device
operation in the end application.
The SMX3200 programming Dongle/cable interfaces
directly between a PC’s parallel port and the target
application; while the SMX3201 interfaces directly to
the PC’s USB port and the target application. The
Top view of straight 0.1" x 0.1 closed-side
connector. SMX3200/SMX3201 interface cable
connector.
Pin 9, 5.0V
Pin 10, Reserved
Pin 8, Reserved
Pin 7, 10V
Pin 5, Reserved
Pin 6, MR#
Pin 4, SDA
Pin 3, GND
Pin 2, SCL
Pin 1, GND
VBATT
SMB113A/B
SMB117/A
SDA
SCL
10
8
6
4
2
9
7
5
3
1
0.1µF
GND
Figure 11 – SMX3200/SMX3201 Programmer I2C serial bus connections to program the SMB113A/B or
SMB117/A.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
27
SMB113A/B/SMB117/A
Preliminary Information
I2C PROGRAMMING INFORMATION
SERIAL INTERFACE
Access to the configuration registers, general-purpose
memory and command and status registers is carried
out over an industry standard 2-wire serial interface
(I2C). SDA is a bi-directional data line and SCL is a
clock input. Data is clocked in on the rising edge of
SCL and clocked out on the falling edge of SCL. All
data transfers begin with the MSB. During data
transfers, SDA must remain stable while SCL is high.
Data is transferred in 8-bit packets with an intervening
clock period in which an Acknowledge is provided by
the device receiving data. The SCL high period (tHIGH)
is used for generating Start and Stop conditions that
precede and end most transactions on the serial bus.
A high-to-low transition of SDA while SCL is high is
considered a Start condition while a low-to-high
transition of SDA while SCL is high is considered a
Stop condition.
The interface protocol allows operation of multiple
devices and types of devices on a single bus through
unique device addressing.
The address byte is
comprised of a 7-bit device type identifier (slave
address). The remaining bit indicates either a read or
a write operation. Refer to Table 1 for a description of
the address bytes used by the SMB113A/B.
The device type identifier for the memory array, the
configuration registers and the command and status
registers are accessible with the same slave address.
The slave address can be can be programmed to any
seven bit number 0000000BIN through 1111111BIN.
WRITE
Writing to the memory or a configuration register is
illustrated in Figures 12and 13 A Start condition
followed by the slave address byte is provided by the
host; the SMB113A/B and SMB117/A respond with an
Acknowledge; the host then responds by sending the
memory address pointer or configuration register
address pointer; the SMB113A/B and SMB117/A
respond with an acknowledge; the host then clocks in
one byte of data. For memory and configuration
register writes, up to 15 additional bytes of data can be
clocked in by the host to write to consecutive
addresses within the same page.
Summit Microelectronics, Inc
After the last byte is clocked in and the host receives
an Acknowledge, a Stop condition must be issued to
initiate the nonvolatile write operation.
READ
The address pointer for the non-volatile configuration
registers and memory registers as well as the volatile
command and status registers must be set before data
can be read from the SMB113A/B or the SMB117/A.
This is accomplished by issuing a dummy write
command, which is a write command that is not
followed by a Stop condition.
A dummy write
command sets the address from which data is read.
After the dummy write command is issued, a Start
command followed by the address byte is sent from
the host. The host then waits for an Acknowledge and
then begins clocking data out of the slave device. The
first byte read is data from the address pointer set
during the dummy write command. Additional bytes
can be clocked out of consecutive addresses with the
host providing an Acknowledge after each byte. After
the data is read from the desired registers, the read
operation is terminated by the host holding SDA high
during the Acknowledge clock cycle and then issuing a
Stop condition. Refer to Figure 14for an illustration of
the read sequence.
CONFIGURATION REGISTERS
The configuration registers are grouped with the
general-purpose memory.
GENERAL-PURPOSE MEMORY
The 96-byte general-purpose memory block is
segmented into two continuous independently lockable
blocks. The first 48-byte memory block begins at
register address pointer A0HEX and the second memory
block begins at the register address pointer C0HEX; see
Table 1. Each memory block can be locked
individually by writing to a dedicated register in the
configuration memory space.
2111 2.4 6/24/2008
28
SMB113A/B/SMB117/A
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
GRAPHICAL USER INTERFACE (GUI)
Device configuration utilizing the Windows based
SMB113A/B/117/A graphical user interface (GUI) is
highly recommended. The software is available from
the Summit website (http://www.summitmicro.com ).
Using the GUI in conjunction with this datasheet,
simplifies the process of device prototyping and the
Slave
Address
0000000BIN
to
1111111BIN
interaction of the various functional blocks. A
programming Dongle (SMX3200) is available from
Summit to communicate with the SMB113A/B and
SMB117/A. The Dongle connects directly to the
parallel port of a PC and programs the device through
a cable using the I2C bus protocol. See figure 11 and
the SMX3200 Data Sheet.
Register Type
Configuration Registers are located in
00 HEX thru 9FHEX
General-Purpose Memory Block 0 is
located in A0 HEX thru BFHEX
General-Purpose Memory Block 1 is
located in C0 HEX thru FFHEX
Table 1 – Possible address bytes used by the SMB113A/B and the SMB117/A.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
29
SMB113A/B/SMB117/A
Preliminary Information
I2C PROGRAMMING INFORMATION (CONTINUED)
M aster
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
7
W
C
5
C
4
C
3
Data
C
2
C
1
C
0
D
7
A
C
K
Slave
S
T
O
P
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 12 – Register Byte Write
S
T
A
R
T
M aster
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
C
6
C
7
W
C
5
C
4
C
3
Data (1)
C
2
C
1
C
0
D
7
A
C
K
Slave
D
6
D
7
D
6
D
5
D
4
D
3
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
S
T
O
P
Data (16)
Data (2)
M aster
D
5
D
2
D
1
D
0
D
7
D
6
D
5
D
2
D
1
D
0
D
7
A
C
K
Slave
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
C
K
A
C
K
Figure 13 – Register Page Write
Master
S
T
A
R
T
Configuration
Register Address
Bus Address
S
A
3
S
A
2
S
A
1
S
A
0
A
2
A
1
A
0
S
T
A
R
T
C
7
W
C
6
C
5
C
4
C
3
C
2
C
1
C
0
A
C
K
Slave
Master
Bus Address
S
A
3
Slave
D
6
D
5
D
4
D
3
S
A
1
S
A
0
A
2
A
1
D
1
D
0
D
7
R
A
C
K
N
A
C
K
Data (n)
D
2
A
0
A
C
K
Data (1)
D
7
S
A
2
D
6
D
5
D
2
D
1
D
0
A
C
K
D
7
D
6
D
5
D
4
D
3
D
2
D
1
S
T
O
P
D
0
A
C
K
Figure 14 – Register Read
Summit Microelectronics, Inc
2111 2.4 6/24/2008
30
SMB113A/B/SMB117/A
Preliminary Information
PACKAGE
Summit Microelectronics, Inc
2111 2.4 6/24/2008
31
SMB113A/B/SMB117/A
Preliminary Information
PART MARKING
Summit Part Number:
SMB113A, SMB113B,
SMB117 or SMB117A
SUMMIT
SMB113AN
xx
Annn L AYYWW
Pin 1
Status Tracking Code
(01, 02,...)
(Summit Use)
Date Code (YYWW)
Lot tracking code (Summit use)
100% Sn, RoHS compliant
Drawing not
to scale
Part Number suffix
(Contains Customer specific
ordering requirements)
Product Tracking Code (Summit use)
ORDERING INFORMATION
Summit
Part Number
SMB113A N
C
nnn
L
SMB113A, SMB113B,
SMB117 or SMB117A
Part Number Suffix
Package
N = 32-Pad QFN
Environmental Attribute
L = 100% Sn, RoHS compliant
Temperature Range
Specific requirements are contained in the suffix
C = Commercial
BLANK = Industrial
The default device ordering number is SMB113ANC-650L. It is tested over the commercial temperature range. The ordering number is
derived from the customer supplied hex file. New device suffix numbers are assigned to non-default requirements.
NOTICE
NOTE 1 – This is a Preliminary data sheet that describes a Summit that is in pre-production with limited characterization.
SUMMIT Microelectronics, Inc. reserves the right to make changes to the products contained in this publication in order to improve
design, performance or reliability. SUMMIT Microelectronics, Inc. assumes no responsibility for the use of any circuits described
herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent
infringement. Charts and schedules contained herein reflect representative operating parameters, and may vary depending upon a
user’s specific application. While the information in this publication has been carefully checked, SUMMIT Microelectronics, Inc. shall
not be liable for any damages arising as a result of any error or omission.
SUMMIT Microelectronics, Inc. does not recommend the use of any of its products in life support or aviation applications where the
failure or malfunction of the product can reasonably be expected to cause any failure of either system or to significantly affect their
safety or effectiveness. Products are not authorized for use in such applications unless SUMMIT Microelectronics, Inc. receives
written assurances, to its satisfaction, that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks;
and (c) potential liability of SUMMIT Microelectronics, Inc. is adequately protected under the circumstances.
Revision 2.4 This document supersedes all previous versions. Please check the Summit Microelectronics Inc. web site at
http://www.summitmicro.com for data sheet updates.
© Copyright 2007 SUMMIT MICROELECTRONICS, Inc. PROGRAMMABLE POWER FOR A GREEN PLANET™
ADOCTM is a registered trademark of Summit Microelectronics Inc., I2C is a trademark of Philips Corporation.
Summit Microelectronics, Inc
2111 2.4 6/24/2008
32