SN55LVDS31-SP www.ti.com SLLSEB5 – MARCH 2012 HIGH-SPEED DIFFERENTIAL LINE DRIVER Check for Samples: SN55LVDS31-SP FEATURES 1 • • • • • • • • • • QML-V Qualified, SMD 5962-97621 Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and 100-Ω Load Typical Output Voltage Rise and Fall Times of 500 ps (400 Mbps) Typical Propagation Delay Times of 1.7 ns Operate From a Single 3.3-V Supply Power Dissipation 25 mW Typical Per Driver at 200 MHz Driver at High Impedance When Disabled or With VCC = 0 Bus-Terminal ESD Protection Exceeds 8 kV Low-Voltage TTL (LVTTL) Logic Input Levels • Cold Sparing for Space and High Reliability Applications Requiring Redundancy J OR W PACKAGE (TOP VIEW) 1A 1Y 1Z G 2Z 2Y 2A GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 4A 4Y 4Z G 3Z 3Y 3A DESCRIPTION The SN55LVDS31 is a differential line driver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as TIA/EIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. This driver will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled. The intended application of this device and signaling technique is both point-to-point and multidrop (one driver and multiple receivers) data transmission over controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment. The SN55LVDS31 is characterized for operation from –55°C to 125°C. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated SN55LVDS31-SP SLLSEB5 – MARCH 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) TA –55°C to 125°C (1) PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING CDIP - J 5962-9762101VEA 5962-9762101VEA CFP - W 5962-9762101VFA 5962-9762101VFA For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. (2) xxx Logic Symbol SN55LVDS31 Logic Diagram (Positive Logic) SN55LVDS31 G G 1A 2A 3A 4A 4 12 G ≥1 G EN 1 7 1A 2 3 6 5 9 10 11 15 14 13 1Y 2A 4 12 1 7 2 3 6 5 1Z 2Y 3A 9 10 11 2Z 3Y 3Z 4A 15 14 13 1Y 1Z 2Y 2Z 3Y 3Z 4Y 4Z 4Y 4Z This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. 2 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP SN55LVDS31-SP www.ti.com SLLSEB5 – MARCH 2012 FUNCTION TABLE Table 1. SN55LVDS31 (1) (1) ENABLES OUTPUTS INPUT A G G Y Z H H X H L H L H X L H X L H L L X L L H X L H Z Z Open H X L H Open X L L H H = high level, L = low level, X = irrelevant, Z = high impedance (off) EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS EQUIVALENT OF EACH A INPUT EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS VCC VCC TYPICAL OF ALL OUTPUTS VCC 50 Ω 50 Ω Input Input 7V 7V 300 kΩ 10 kΩ 5Ω Y or Z Output 7V Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP 3 SN55LVDS31-SP SLLSEB5 – MARCH 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT VCC Supply voltage range VI Input voltage range (2) –0.5 V to 4 V –0.5 V to VCC + 0.5 V Continuous total power dissipation See Dissipation Rating Table Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds Tstg (1) 260°C Storage temperature range –65°C to 150°C Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages, except differential I/O bus voltages, are with respect to the network ground terminal. (2) DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING TA = 125°C POWER RATING J 1375 mW 11 mW/°C 880 mW 715 mW 275 mW W 1000 mW 8 mW/°C 640 mW 520 mW 200 mW (1) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. RECOMMENDED OPERATING CONDITIONS MIN NOM VCC Supply voltage 3 VIH High-level input voltage 2 VIL Low-level input voltage TA Operating free-air temperature 3.3 MAX 3.6 UNIT V V –55 0.8 V 125 °C MAX UNIT 454 mV 50 mV ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP (1) TEST CONDITIONS VOD Differential output voltage magnitude RL = 100 Ω, See Figure 2 247 ΔVOD Change in differential output voltage magnitude RL = 100 Ω, between logic states See Figure 2 –50 VOC(SS) Steady-state common-mode output voltage See Figure 3 1.125 ΔVOC(SS) Change in steady-state common-mode output voltage between logic states See Figure 3 –50 VOC(PP) Peak-to-peak common-mode output voltage See Figure 3 ICC Supply current 340 1.2 1.375 50 50 VI = 0.8 V or 2 V, Enabled, No load VI = 0.8 or 2 V, RL = 100 Ω, Enabled VI = 0 or VCC, Disabled V mV mV 9 20 25 35 0.25 1 mA IIH High-level input current VIH = 2 4 20 μA IIL Low-level input current VIL = 0.8 V 0.1 10 μA VO(Y) or VO(Z) = 0 –4 –24 IOS Short-circuit output current IOZ High-impedance output current VO = 0 or 2.4 V IO(OFF) Power-off output current VCC = 0, Ci Input capacitance (1) 4 VOD = 0 ±12 VO = 2.4 V 3 mA ±1 μA ±4 μA pF All typical values are at TA = 25°C and with VCC = 3.3 V. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP SN55LVDS31-SP www.ti.com SLLSEB5 – MARCH 2012 SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT tPLH Propagation delay time, low-to-high-level output 0.5 1.4 4 ns tPHL Propagation delay time, high-to-low-level output 1 1.7 4.5 ns tr Differential output signal rise time (20% to 80%) 0.4 0.5 1 ns tf Differential output signal fall time (80% to 20%) 0.4 0.5 1 ns tsk(p) Pulse skew (|tPHL – tPLH|) 0.3 0.6 ns tsk(o) Channel-to-channel output skew (2) 0.3 0.6 ns tPZH Propagation delay time, high-impedance-to-high-level output 5.4 15 ns tPZL Propagation delay time, high-impedance-to-low-level output 2.5 15 ns tPHZ Propagation delay time, high-level-to-high-impedance output 8.1 17 ns tPLZ Propagation delay time, low-level-to-high-impedance output 7.3 15 ns (1) (2) RL = 100 Ω, CL = 10 pF, See Figure 2 See Figure 4 All typical values are at TA = 25°C and with VCC = 3.3 V. tsk(o) is the maximum delay time difference between drivers on the same device. PARAMETER MEASUREMENT INFORMATION IOY Y II A Z IOZ VOD VOY VOC VI (VOY + VOZ)/2 VOZ Figure 1. Voltage and Current Definitions 2V 1.4 V 0.8 V Input tPLH Y Input (see Note A) Z VOD tPHL 100 Ω ± 1% 100% 80% VOD CL = 10 pF (2 Places) (see Note B) 0 20% 0% tf tr NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP 5 SN55LVDS31-SP SLLSEB5 – MARCH 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Y Input (see Note A) 49.9 Ω ± 1% (2 Places) 3V A A 0 VOC(PP) Z (see Note C) VOC(SS) VOC CL = 10 pF (2 Places) (see Note B) VOC NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps, pulse width = 10 ± 0.2 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. C. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz. Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage 49.9 Ω ± 1% (2 Places) Y Inputs (see Note A) 0.8 V or 2 V Z 1.2 V G G 1,2EN or 3,4EN CL = 10 pF (2 Places) (see Note B) G, 1,2EN, OR 3,4EN 2V 1.4 V 0.8 V G 2V 1.4 V 0.8 V tPZH VOY VOZ tPHZ VOY or VOZ tPZL 100%, ≅1.4 V 50% 0%, 1.2 V A at 2 V, G at VCC and Input to G or G at GND and Input to G for ’LVDS31 Only 100%, 1.2 V 50% 0%, ≅1 V A at 0.8 V, G at VCC and Input to G or G at GND and Input to G for ’LVDS31 Only tPLZ VOZ or VOY NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps, pulse width = 500 ± 10 ns. B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T. Figure 4. Enable-/Disable-Time Circuit and Definitions 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP SN55LVDS31-SP www.ti.com SLLSEB5 – MARCH 2012 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY LOW-TO-HIGH PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 35 I CC − Supply Current − mA 33 tPLH − Low-to-High Propagation Delay Time - ns 2.8 Four Drivers Loaded Per Figure 3 and Switching Simultaneously VCC = 3.6 V 31 29 VCC = 3 V 27 25 VCC = 3.3 V 23 21 19 17 15 50 150 100 200 2.6 VCC = 3.3 V VCC = 3.6 V 2.4 2.2 VCC = 3 V 2 1.8 1.6 -55 f − Frequency − MHz -40 25 TA - Free-Air Temperature - °C Figure 5. 125 Figure 6. tPHL − Low-to-High Propagation Delay Time - ns HIGH-TO-LOW PROPAGATION DELAY TIME vs FREE-AIR TEMPERATURE 3.5 VCC = 3 V VCC = 3.3 V 3 2.5 2 VCC = 3.6 V 1.5 1 0.5 0 -55 -40 25 125 TA - Free-Air Temperature - °C Figure 7. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP 7 SN55LVDS31-SP SLLSEB5 – MARCH 2012 www.ti.com APPLICATION INFORMATION The SN55LVDS31 is generally used as a building block for high-speed point-to-point data transmission where ground differences are less than 1 V. The SN55LVDS31 can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers approach ECL speeds without the power and dual supply requirements. TRANSMISSION DISTANCE vs SIGNALING RATE Transmission Distance − m 100 30% Jitter (see Note A) 10 5% Jitter (see Note A) 1 24 AWG UTP 96 Ω (PVC Dielectric) 0.1 10 100 1000 Signaling Rate − Mbps A. This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern. Figure 8. Typical Transmission Distance Versus Signaling Rate 1 2 ZO = 100 Ω 3 VCC 4 5 1A VCC 1Y 4A 1Z 4Y G 4Z 2Z G 16 15 3.3 V 0.1 µF (see Note A) 0.001 µF (see Note A) 14 ZO = 100 Ω 13 12 See Note B ZO = 100 Ω 6 7 8 2Y 3Z 2A 3Y GND 3A 11 10 ZO = 100 Ω 9 NOTES: A. Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitors should be located as close as possible to the device terminals. B. Unused enable inputs should be tied to VCC or GND, as appropriate. Figure 9. Typical Application Circuit Schematic 8 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP SN55LVDS31-SP www.ti.com SLLSEB5 – MARCH 2012 1/4 ’LVDS31 Strb/Data_TX Tp Bias on Twisted-Pair A Strb/Data_Enable TP 55 Ω ’LVDS32 5 kΩ Data/Strobe 55 Ω 3.3 V TP 20 kΩ 500 Ω VG on Twisted-Pair B 1 Arb_RX 500 Ω 20 kΩ 3.3 V 500 Ω 20 kΩ 2 Arb_RX 500 Ω 20 kΩ 3.3 V 7 kΩ Twisted-Pair B Only 7 kΩ 10 kΩ Port_Status 3.3 kΩ NOTES: A. B. C. D. Resistors are leadless, thick film (0603), 5% tolerance. Decoupling capacitance is not shown, but recommended. VCC is 3 V to 3.6 V. The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394. Figure 10. 100-Mbps IEEE 1394 Transceiver Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP 9 SN55LVDS31-SP SLLSEB5 – MARCH 2012 www.ti.com 0.01 µF 1 1A VCC ≈3.6 V 16 5V 0.1 µF (see Note A) 2 ZO = 100 Ω 3 VCC 4 5 1Y 4A 1Z 4Y G 4Z 2Z G 1N645 (2 places) 15 14 ZO = 100 Ω 13 12 See Note B ZO = 100 Ω 6 7 8 2Y 3Z 2A 3Y GND 3A 11 10 ZO = 100 Ω 9 A. Place a 0.1-μF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground plane. The capacitor should be located as close as possible to the device terminals. B. Unused enable inputs should be tied to VCC or GND, as appropriate. Figure 11. Operation With 5-V Supply COLD SPARING Systems using cold sparing have a redundant device electrically connected without power supplied. To support this configuration, the spare must present a high-input impedance to the system so that it does not draw appreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device. When the device is powered off, VCC must be clamped to ground and the I/O voltages applied must be within the specified recommended operating conditions. RELATED INFORMATION IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for more information. For more application guidelines, see the following documents: • Low-Voltage Differential Signaling Design Notes (SLLA014) • Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038) • Reducing EMI With LVDS (SLLA030) • Slew Rate Control of LVDS Circuits (SLLA034) • Using an LVDS Receiver With RS-422 Data (SLLA031) 10 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): SN55LVDS31-SP PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2012 PACKAGING INFORMATION Orderable Device 5962-9762101VFA Status (1) Package Type Package Drawing ACTIVE CFP W Pins Package Qty 16 1 Eco Plan TBD (2) Lead/ Ball Finish A42 MSL Peak Temp (3) Samples (Requires Login) N / A for Pkg Type (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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