TI SN65HVD485ED

DGK
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D
P
SLLS612 − JUNE 2004
FEATURES
D Bus-Pin ESD Protection Up to 15 kV
D 1/2 Unit Load—Up to 64 Nodes on a Bus
D Bus Open Failsafe Receiver
D Available in Small MSOP-8 Package
D Meets or Exceeds the Requirements of the
D
DESCRIPTION
The SN65HVD485E is a half-duplex transceiver designed
for RS-485 data bus networks. Powered by a 5-V supply,
it is fully compliant with the TIA/EIA-485A standard. This
device is suitable for data transmission up to 10 Mbps over
long twisted-pair cables and is designed to operate with
very low supply current, typically less than 2 mA, exclusive
of the load. When in the inactive shutdown mode, the
supply current drops below 1 mA.
TIA/EIA−485A Standard
Industry-Standard SN75176 Footprint
The wide common-mode range and high ESD protection
levels of this device make it suitable for demanding
applications such as, electrical inverters, status/command
signals across telecom racks, cabled chassis
interconnects, and industrial automation networks where
noise tolerance is essential. The SN65HVD485E matches
the industry-standard footprint of the SN75176. Power-on
reset circuits keep the outputs in a high-impedence state
until the supply voltage has stabilized. A thermal shutdown
function protects the device from damage due to system
fault conditions. The SN65HVD485E is characterized for
operation from −40°C to 85°C air temperature.
APPLICATIONS
D Motor Control
D Power Inverters
D Industrial Automation
D Building Automation Networks
D Industrial Process Control
D Battery-Powered Applications
D Telecommunications Equipment
Improved Replacement for:
PART NUMBER
REPLACE WITH
ADM485
HVD485E:
Better ESD protection (±15 kV vs. unspecified)
Faster signaling rate (10 Mbps vs. 5 Mbps)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
SP485E
HVD485E:
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
LMS485E
HVD485E:
Higher signaling rate (10 Mbps vs. 2.5 Mbps)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
DS485
HVD485E:
Higher signaling rate (10 Mbps vs. 2.5 Mbps)
Better ESD (±15 kV vs. ±2 kV)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
LTC485
HVD485E:
Better ESD (±15 kV vs. ±2 kV)
Wider power supply tolerance (10% vs. 5%)
MAX485E
HVD485E:
Higher signaling rate (10 Mbps vs. 2.5 Mbps)
More nodes on a bus (64 vs. 32)
Wider power supply tolerance (10% vs. 5%)
ST485E
HVD485E:
Higher signaling rate (10 Mbps vs. 5 Mbps)
Wider power supply tolerance (10% vs. 5%)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"# $"%&! '#( '"!
! $#!! $# )# # #* "# '' +,(
'"! $!#- '# #!#&, !&"'# #- && $##(
Copyright  2004, Texas Instruments Incorporated
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SLLS612 − JUNE 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
TA
PACKAGE TYPE
D(1)
P
SN65HVD485EP
Marked as 65HVD485
−40°C to 85°C
DGK(2)
SN65HVD485ED
Marked as VP485
SN65HVD485EDGK
Marked as NWJ
(1) The D package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD485EDR).
(2) The DGK package is available taped and reeled. Add an R suffix to the device type (i.e., SN65HVD485EDGKR).
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1) (2)
UNITS
Supply voltage range, VCC
−0.5 V to 7 V
Voltage range at A or B
−9 V to 14 V
Voltage range at any logic pin
−0.3 V to VCC + 0.3 V
Receiver output current
−24 mA to 24 mA
Voltage input range, transient pulse, A and B, through 100 Ω (see Figure 13)
−50 V to 50 V
Storage temperature range
−65°C to 130°C
Junction temperature, TJ
170°C
Continuous total power dissipation
Refer to Package Dissipation Table
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
PACKAGE DISSIPATION RATINGS
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
507 mW
DERATING FACTOR(3)
ABOVE TA = 25°C
4.82 mW/°C
289 mW
217 mW
824 mW
7.85 mW/°C
471 mW
353 mW
Low k(1)
Low k(1)
686 mW
6.53 mW/°C
392 mW
294 mW
394 mW
3.76 mW/°C
255 mW
169 mW
High k(2)
583 mW
5.55 mW/°C
333 mW
250 mW
PACKAGE
JEDEC BOARD MODEL
D
Low k(1)
High k(2)
P
DGK
TA <25°C
POWER RATING
(1) In accordance with the low-k thermal metric definitions of EIA/JESD51-3
(2) In accordance with the high-k thermal metric definitions of EIA/JESDS1-7
(3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
RECOMMENDED OPERATING CONDITIONS(1)
MIN
TYP
MAX
UNIT
Supply voltage, VCC
4.5
5.5
V
Input voltage at any bus terminal (separately or common mode), VI
−7
12
V
High-level input voltage (D, DE, or RE inputs), VIH
2
0
VCC
0.8
V
Low-level input voltage (D, DE, or RE inputs), VIL
−12
12
V
−60
60
−8
8
Differential input voltage, VID
Driver
Output current, IO
Differential load resistance, RL
Signaling rate, 1/tUI
Receiver
54
0
mA
Ω
60
10
Operating free−air temperature, TA
−40
85
(2)
Junction temperature, TJ
−40
130
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum, is used in this data sheet.
(2) See thermal characteristics table for information on maintenance of this specification for the DGK package.
2
V
Mbps
°C
°C
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SUPPLY CURRENT
over recommended operating conditions unless otherwise noted
PARAMETER
ICC
TEST CONDITIONS
Driver and receiver enabled
D at VCC or open or 0V,
No load
Driver and receiver disabled
D at VCC or open,
(1) All typical values are at 25°C and with a 5-V supply.
MIN
TYP(1)
MAX
UNIT
DE at VCC, RE at 0 V,
2
mA
DE at 0 V, RE at VCC
1
mA
ELECTROSTATIC DISCHARGE PROTECTION
PARAMETER
TEST CONDITIONS
Human body model
Human body model(2)
MIN TYP(1)
Bus terminals and GND
All pins
Charged-device-model(3)
All pins
(1) All typical values at 25°C
(2) Tested in accordance with JEDEC Standard 22, Test Method A114-A.
(3) Tested in accordance with JEDEC Standard 22, Test Method C101.
MAX
UNIT
±15
kV
±4
kV
±1
kV
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
VOD
Differential output voltage
IO = 0, No load
RL = 54 Ω, See Figure 1
VTEST = −7 V to 12 V,
See Figure 2
∆VOD
VOC(SS)
Change in magnitude of differential output voltage
∆VOC(SS)
Change in steady-state common-mode output
voltage
VOC(PP)
IOZ
TEST CONDITIONS
See Figure 1 and Figure 2
Steady-state common-mode output voltage
See Figure 3
MIN
3
4.3
1.5
2.3
High-impedance output current
MAX
UNIT
V
1.5
−0.2
0
0.2
1
2.6
3
−0.1
0
0.1
See Figure 3
II
Input current
IOS
Short-circuit output current
(1) All typical values are at 25°C and with a 5V-supply.
TYP(1)
500
V
V
mV
See receiver input currents
D, DE
−100
100
−7 V ≤ VO ≤ 12 V, See Figure 7
−250
250
µA
A
mA
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tr
Differential output signal rise time
tf
Differential output signal fall time
tsk(p)
Pulse skew ( |tPHL - tPLH| )
tPZH
Propagation delay time, high-impedance-to-high-level output
tPHZ
Propagation delay time, high-level-to-high-impedance output
tPZL
Propagation delay time, high-impedance-to-low-level output
tPLZ
Propagation delay time, low-level-to-high-impedance output
tPZH(SHDN) Propagation delay time, shutdown-to-high-level output
tPZL(SHDN)
Propagation delay time, shutdown-to-low-level output
TEST CONDITIONS
MIN
TYP
MAX
UNIT
30
30
RL = 54 Ω,, CL = 50 pF,
See Figure 4
25
ns
25
5
RL = 110 Ω,
RE at 0 V, See Figure 5
150
RL = 110 Ω, RE at 0 V
See Figure 6
150
100
100
ns
ns
RL = 110 Ω, RE at VCC,
See Figure 5
2600
ns
RL = 110 Ω, RE at VCC,
See Figure 6
2600
ns
3
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RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
VIT+
VIT−
Positive-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ − VIT−)
VOH
High-level output voltage
VID = 200 mV, IOH = −8 mA, See
Figure 8
VOL
Low-level output voltage
VID = −200 mV, IOH = 8 mA, See
Figure 8
IOZ
High-impedance-state output current
II
Negative-going input threshold voltage
IO = −8 mA
IO = 8 mA
IIH
IIL
High-level input current (RE)
Cdiff
Differential input capacitance
Low-level input current (RE)
TYP(1)
−85
−200
VO = 0 to VCC, RE= VCC
VIH = 12 V, VCC = 5 V
VIH = 12 V, VCC = 0
VIH = −7 V, VCC = 5 V
Bus input current
MIN
4
MAX
−10
UNIT
mV
−115
mV
30
mV
4.6
V
0.15
0.4
−1
1
V
µA
0.5
0.5
mA
−0.4
VIH = −7 V, VCC = 0
VIH = 2 V
−0.4
−60
−30
µA
VIL = 0.8 V
VI = 0.4 sin (4E6πt) + 0.5 V,
DE at 0 V
−60
−30
µA
7
pF
(1) All typical values are at 25°C and with a 5-V supply.
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions unless otherwise noted
PARAMETER
tPLH
tPHL
Propagation delay time, low-to-high-level output
tsk(p)
tr
Pulse skew ( |tPHL − tPLH| )
tf
tPZH
Output signal fall time
tPZL
tPHZ
Output enable time to low level
4
MIN
TYP
Output signal rise time
200
VID = −1.5 V to 1.5 V,
CL = 15 pF, See Figure 9
Propagation delay time, shutdown-to-low-level output
UNIT
ns
8
3
3
Output enable time to high level
Output enable time from high level
MAX
200
Propagation delay time, high-to-low-level output
tPLZ
Output enable time from low level
tPZH(SHDN) Propagation delay time, shutdown-to-high-level output
tPZL(SHDN)
TEST CONDITIONS
ns
50
CL = 15 pF, DE at 3 V,
See Figure 10 and Figure 11
50
50
ns
50
CL = 15 pF, DE at 0 V,
See Figure 12
3500
3500
µss
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PARAMETER MEASUREMENT INFORMATION
NOTE:Test load capacitance includes probe and jig capacitance (unless otherwise specified). Signal generator characteristics: rise and
fall time < 6 ns, pulse rate 100 kHz, 50% duty cycle. ZO = 50 Ω (unless otherwise specified).
A IOA
II
0 V or 3 V
27 Ω
VOD
D
50 pF
27 Ω
B IOB
VOC
Figure 1. Driver Test Circuit, VOD and VOC Without Common-Mode Loading
375 Ω
IOA
VOD
0 V or 3 V
60 Ω
375 Ω
IOB
VTEST = −7 V to 12 V
VTEST
Figure 2. Driver Test Circuit, VOD With Common-Mode Loading
27 Ω
A
VA
D
Signal
Generator
50 Ω
B
27 Ω
93.25 V
VB
50 pF
91.75 V
∆VOC(SS)
VOC(PP)
VOC
VOC
Figure 3. Driver VOC Test Circuit and Waveforms
3V
INPUT
RL = 54 Ω
Signal
Generator
VOD
1.5 V
90%
0V
tPHL
VOD(H)
10%
VOD(L)
tPLH
CL = 50 pF
50 Ω
1.5 V
0V
OUTPUT
tr
tf
Figure 4. Driver Switching Test Circuit and Waveforms
5
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SLLS612 − JUNE 2004
A
S1
D
0 V or 3 V
3 V if Testing A Output
0 V if Testing B Output
DE
Signal
Generator
3V
Output
B
1.5 V
DE
CL = 50 pF
RL = 110 Ω
1.5 V
0.5 V
tPZH
0V
VOH
Output
50 Ω
2.5 V
VOff 0
tPHZ
Figure 5. Driver Enable/Disable Test Circuit and Waveforms, High Output
5V
A
D
0 V or 3 V
0 V if Testing A Output
3 V if Testing B Output
DE
Signal
Generator
RL = 110 Ω
S1
3V
Output
B
1.5 V
DE
1.5 V
0V
CL = 50 pF
tPZL
tPLZ
Output
50 Ω
5V
2.5 V
VOL
0.5 V
Figure 6. Driver Enable/Disable Test Circuit and Waveforms, Low Output
IOS
IO
VO
VID
Voltage
Source
VO
Figure 7. Driver Short-Circuit Test
Signal
Generator
Figure 8. Receiver Parameter Definitions
50 Ω
Input B
VID
A
B
Signal
Generator
50 Ω
R
CL = 15 pF
IO
VO
1.5 V
50%
Input A
tPLH
Output
90%
1.5 V
tr
Figure 9. Receiver Switching Test Circuit and Waveforms
6
0V
tPHL
VOH
10% V
OL
tf
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VCC
VCC
D
DE
A
54 Ω
B
3V
1 kΩ
R
0V
1.5 V
0V
CL = 15 pF
RE
Signal
Generator
RE
tPZH
tPHZ
50 Ω
1.5 V
R
VOH
VOH −0.5 V
GND
Figure 10. Receiver Enable/Disable Test Circuit and Waveforms, Data Output High
0V
VCC
D
DE
A
54 Ω
B
3V
1 kΩ
R
RE
5V
1.5 V
0V
CL = 15 pF
RE
tPZL
Signal
Generator
tPLZ
VCC
50 Ω
R
1.5 V
VOL +0.5 V
VOL
Figure 11. Receiver Enable/Disable Test Circuit and Waveforms, Data Output Low
VCC
Switch Down for V(A) = 1.5 V,
Switch Up for V(A) = −1.5 V
A
1.5 V or
−1.5 V
R
B
3V
1 kΩ
CL = 15 pF
RE
Signal
Generator
50 Ω
RE
1.5 V
0V
tPZH(SHDN)
tPZL(SHDN)
5V
R
VOH
1.5 V
0V
VOL
Figure 12. Receiver Enable From Shutdown Test Circuit and Waveforms
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SLLS612 − JUNE 2004
VTEST
100 Ω
0V
Pulse Generator,
15 µs Duration,
1% Duty Cycle
15 µs
1.5 ms
−VTEST
Figure 13. Test Circuit and Waveforms, Transient Over-Voltage Test
DEVICE INFORMATION
PIN ASSIGNMENTS
LOGIC DIAGRAM (POSITIVE LOGIC)
D, P OR DGK PACKAGE
(TOP VIEW)
D
R
RE
DE
D
1
8
2
7
3
6
4
5
VCC
B
A
GND
4
3
DE
2
RE
6
R 1
7
A
B
FUNCTION TABLE
DRIVER
RECEIVER
OUTPUTS
INPUT
D
ENABLE
DE
A
DIFFERENTIAL INPUTS
VID = VA – VB
ENABLE
RE
OUTPUT
R
H
H
H
L
L
H
L
VID ≤ −0.2 V
−0.2 V < VID < −0.01 V
L
L
H
L
X
L
Z
?
Z
−0.01 V ≤ VID
L
H
Open
H
H
X
Open
Z
L
X
H
Z
Z
Open circuit
L
H
X
Open
Z
B
NOTE: H= high level; L = low level; Z = high impedance; X = irrelevant; ? = indeterminate
8
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SLLS612 − JUNE 2004
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
D and RE Input
DE Input
VCC
Input
200 kΩ
500 VCC
Input
9V
500 200 kΩ
9V
A Input
B Input
VCC
16 V
VCC
16 V
36 kΩ
180 k Ω
36 kΩ
180 kΩ
Input
Input
16 V
36 kΩ
16 V
36 kΩ
A and B Outputs
R Outputs
VCC
VCC
16 V
5Ω
Output
Output
16 V
9V
THERMAL CHARACTERISTICS
DGK Package
PARAMETER
ΘJA
Junction-to-ambient thermal resistance(1)
ΘJB
ΘJC
Junction-to-board thermal resistance
P(AVG)
Average power dissipation
TA
Ambient air temperature
TEST CONDITIONS
Low-k(2) board, no air flow
High-k(3) board, no air flow
MIN
TYP
MAX
266
°C/W
180
High-k(3) board, no air flow
108
Junction-to-case thermal resistance
°C/W
66
RL = 54 Ω, Input to D is a 10 Mbps
50% duty cycle square wave
Vcc at 5.5 V, TJ = 130°C
UNIT
219
mW
JEDEC High K board model
−40
93
°C
JEDEC Low K board model
−40
75
°C
TSD
Thermal shut-down junction temperature
165
°C
(1) See TI application note literature number SZZA003, Package Thermal Characterization Methodologies, for an explanation of this parameter.
(2) JESD51-3 Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
(3) JESD51-7 High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
9
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SLLS612 − JUNE 2004
TYPICAL CHARACTERISTICS
DRIVER DIFFERENTIAL OUTPUT VOLTAGE
vs
DIFFERENTIAL OUTPUT CURRENT
BUS INPUT CURRENT
vs
BUS INPUT VOLTAGE
5
80
TA = 25°C
VCC = 5 V
VOD − Differential Output Voltage − V
4.5
II − Input Bias Current − µ A
60
40
VCC = 0 V
20
0
VCC = 5 V
−20
−40
−60
−8
4
RL = 120Ω
3.5
3
RL = 60Ω
2.5
2
1.5
1
0.5
0
−6
−4
−2 0
2
4
6
VI − Bus Input Voltage − V
8
10
12
0
10
20
30
40
IO − Differential Output Current − mA
Figure 14
50
Figure 15
APPLICATION INFORMATION
RT
RT
NOTE: The line should be terminated at both ends with its characteristic impedance (RT = ZO).
Stub lengths off the main line should be kept as short as possible.
Figure 16. Typical Application Circuit
POWER USAGE IN AN RS-485 TRANSCEIVER
Power consumption is a concern in many applications. Power supply current is delivered to the bus load as well as to the
transceiver circuitry. For a typical RS-485 bus configuration, the load that an active driver must drive consists of all of the
receiving nodes, plus the termination resistors at each end of the bus.
The load presented by the receiving nodes depends on the input impedance of the receiver. The TIA/EIA-485-A standard
defines a unit load as allowing up to 1 mA. With up to 32 unit loads allowed on the bus, the total current supplied to all
receivers can be as high as 32 mA. The HVD485E is rated as a 1/2 unit load device, so up to 64 can be connected on a
bus.
The current in the termination resistors depends on the differential bus voltage. The standard requires active drivers to
produce at least 1.5 V of differential signal. For a bus terminated with one standard 120-Ω resistor at each end, this sums
to 25 mA differential output current whenever the bus is active. Typically the HVD485E can drive more than 25 mA to a
60 Ω load, resulting in a differential output voltage higher than the minimum required by the standard. (See Figure 15.)
Supply current increases with signaling rate primarily due to the totum pole outputs of the driver. When these outputs
change state, there is a moment when both the high-side and low-side output transistors are conducting and this creates
a short spike in the supply current. As the frequency of state changes increases, more power is used.
10
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SLLS612 − JUNE 2004
THERMAL CHARACTERISTICS OF IC PACKAGES
ΘJA (Junction-to-Ambient Thermal Resistance) is defined as the difference in junction temperature to ambient temperature
divided by the operating power
ΘJA is NOT a constant and is a strong function of
D
D
D
the PCB design (50% variation)
altitude (20% variation)
device power (5% variation)
ΘJA can be used to compare the thermal performance of packages if the specific test conditions are defined and used.
Standardized testing includes specification of PCB construction, test chamber volume, sensor locations, and the thermal
characteristics of holding fixtures. ΘJA is often misused when it is used to calculate junction temperatures for other
installations.
TI uses two test PCBs as defined by JEDEC specifications. The low-k board gives average in-use condition thermal
performance and consists of a single trace layer 25 mm long and 2-oz thick copper. The high-k board gives best case in−use
condition and consists of two 1-oz buried power planes with a single trace layer 25 mm long with 2-oz thick copper. A 4%
to 50% difference in ΘJA can be measured between these two test cards
ΘJC (Junction-to-Case Thermal Resistance) is defined as difference in junction temperature to case divided by the
operating power. It is measured by putting the mounted package up against a copper block cold plate to force heat to flow
from die, through the mold compound into the copper block.
ΘJC is a useful thermal characteristic when a heatsink is applied to package. It is NOT a useful characteristic to predict
junction temperature as it provides pessimistic numbers if the case temperature is measured in a non-standard system and
junction temperatures are backed out. It can be used with ΘJB in 1-dimensional thermal simulation of a package system.
ΘJB (Junction-to-Board Thermal Resistance) is defined to be the difference in the junction temperature and the PCB
temperature at the center of the package (closest to the die) when the PCB is clamped in a cold−plate structure. ΘJB is
only defined for the high-k test card.
ΘJB provides an overall thermal resistance between the die and the PCB. It includes a bit of the PCB thermal resistance
(especially for BGA’s with thermal balls) and can be used for simple 1-dimensional network analysis of package system
(see figure 18).
Ambient Node
CA Calculated
Surface Node
JC Calculated/Measured
Junction
JB Calculated/Measured
PC Board
Figure 17. Thermal Resistance
11
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
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Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Amplifiers
amplifier.ti.com
Audio
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
www.ti.com/broadband
Interface
interface.ti.com
Digital Control
www.ti.com/digitalcontrol
Logic
logic.ti.com
Military
www.ti.com/military
Power Mgmt
power.ti.com
Optical Networking
www.ti.com/opticalnetwork
Microcontrollers
microcontroller.ti.com
Security
www.ti.com/security
Telephony
www.ti.com/telephony
Video & Imaging
www.ti.com/video
Wireless
www.ti.com/wireless
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