SN65LVDS324
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1080p60 IMAGE SENSOR RECEIVER
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FEATURES
1
•
23
•
•
•
•
•
Bridges the Interface Between Video Image
Sensors and Processors
Receives Aptina HiSPi™, Panasonic LVDS, or
Sony LVDS Parallel; Outputs 1.8V CMOS with
10/12/14/16 Bits at 18.5MHz to 162MHz
SubLVDS Inputs Support Up To 648Mbps
Integrated 100Ω Differential Input Termination
Test Image Generation Feature
Compatible with TI OMAP™ and DaVinci™
Including DM385, DM8127, DM36x, and DMVA
•
•
•
Low Power 1.8V CMOS Process
Configurable Output Conventions
Packaged in 4.5 x 7mm BGA
APPLICATIONS
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IP Network Cameras
Machine Vision
Video Conferencing
Gesture Recognition
DESCRIPTION
The SN65LVDS324 is a SubLVDS deserializer that recovers words, detects sync codes, multiplies the input DDR
clock by a ratio, and outputs parallel CMOS 1.8V data on the rising clock edge. It bridges the video stream
interface between HD image sensors made by leading manufacturers, to a format that common processors can
accept. The supported pixel frequency is 18.5MHz to 162MHz — suitable for resolutions from VGA to 1080p60.
Four high-level modes are supported: Aptina 1-Channel 4-Lane, Aptina 1-Channel 2-Lane, Panasonic 2-Channel
2-Port, and Sony LVDS Parallel. Each supports 10/12/14/16 bit sub-modes, according to Table 1. Each mode
also has a configurable allowable frequency range, as specified by Table 3 register PLL_CFG.
The SN65LVDS324 is configured through its I2C-programmable registers. This volatile memory must be written
after power up. Configuration options include the MSB/LSB output order, sync polarity convention, data slew
rate, and two output timing modes (long-setup or clock-centered), for wider compatibility with different processors
and software. The TESTMODE_VIDEO feature is designed to assist engineering development. The max
allowable frame size is 8191 x 8191.
With integrated differential input termination, and a footprint of 4.5 x 7mm, the SN65LVDS324 provides a
differentiated solution with optimized form, function, and cost. It operates through an ambient temperature range
of –40°C to 85°C.
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Figure 1. General System Diagram
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OMAP, DaVinci are trademarks of Texas Instruments.
HiSPi is a trademark of Aptina.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
SN65LVDS324
SLLSED9 – NOVEMBER 2012
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL DESCRIPTION
Control Logic and
(Control and Status Registers)
SD11P
SCL
SOF/EOF
SOL/EOL
12b
LVDS Parallel
SYNC Decoder
SD10P
12b
100Ω
DDR LVDS Receiver
SD10N
SD9P
100Ω
SD9N
SD0P
100Ω
SD0N
4b
4b
SCLKP
100Ω
2-Channel 2-Port
Word Recovery
and SYNC Decode
1-Channel 4-Lane
1-Channel 2-Lane
Word Recovery
and SYNC Decode
SOF/EOF
SOL/EOL
16b
SOF/EOF
SOL/EOL
D15
HS
VS
D0
Parallel Interface
100Ω
SD11N
SDA
I2 C
Parallel Output Protocol Engine
RST
16b
VSYNC
HSYNC
16b
CLKOUT
SCLKN
VCC
Clock Generator
VCCA
PLL
GND
CLK * (1/3, 1/2, 2/3, 4/7, 2)
GNDA
Figure 2. Functional Block Diagram
Reset Implementation
When RST is Low, the PLL is disabled, the SubLVDS inputs are disabled, and all outputs drive either VOH or VOL
with no toggling. It is critical to transition the RST input from a low to high level after the VCC supply has reached
the minimum recommended operating voltage. This is achieved by an external capacitor connected between
RST and GND, and/or by a control signal to the RST input. Both implementations are shown:
VCC
VCC
RST
GPO
RST
RRST = 150 kΩ
RRST = 150 kΩ
C
C
SN65LVDS324
Controller
Figure 3. External Capacitor Controlled RST
2
SN65LVDS324
Figure 4. RST Input from Active Controller
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Device Configurations
Table 1. SN65LVDS324 Modes, Common Frequencies, and Signals Used (1) (2)
SENSOR_CFG
(CSR 09[2:0])
000
001
010
011
100
110
101
111
(1)
(2)
SubLVDS
Interface
Mode
Bits
Per
Pixel
Sony
LVDS
Parallel
10
Panasonic
2-Channel
2-Port
12
Aptina
1-Channel
4-Lane
Aptina
1-Channel
2-Lane
Target
Video
12
16
1080p
60fps
Target SCLK
Frequency
(MHz)
Target
PLL_CFG
(CSR 0A[1:0])
74.25
10
222.75
10
11
12
222.75
10
16
297
11
14
129.9375
00
222.75
10
720p
60fps
SCLK
Sensor
Clock
148.5
297
12
Target
CLKOUT
Frequency
(MHz)
Sensor
Ch1
Clock
Sensor
Clock
74.25
SD
[0:1]
SD2
SD
[3:4]
SD
[5:9]
SD
[10:11]
X[2]
X[3:4]
X[5:9]
X[10:11]
Sensor
Ch2
Clock
Ch2
X[0:1]
X[2]
X[3],
GND
GND
GND
GND
GND
GND
X[0:1]
Ch1
X[0:1]
X[0:1]
X[0:11] represent the connected sensor's LVDS data lanes.
GND represents a connection to the system reference ground.
Aptina Mode Specifics
Only the Streaming-SP HiSPi mode is supported. If "FLR" and "CRC" are in the data stream, the SN65LVDS324
will transmit them. "IDL" cannot match a sync code or be all-zero.
VSYNC and HSYNC Output Timing
Figure 5 describes the horizontal and vertical blanking periods, and how they generally relate to the VSYNC and
HSYNC outputs. The SN65LVDS324 asserts VSYNC (driven high) by default, and drives VSYNC high for at
least one CLKOUT cycle at the beginning of each video frame. The SN65LVDS324 sensor interface logic
determines the beginning of an active video frame by sensor-dependent methods.
There may be certain VSYNC and HSYNC operating requirements in the video processing pipeline in the DSP,
such as a required number of vertical blanking lines, requirements for horizontal sync during vertical blanking, or
requirements for data patterns during blanking times, special requirements for still image capture, etc. Systems
that utilize SN65LVDS324 are required to configure the sensor to meet the vertical blanking and horizontal
blanking requirements set by DSP video processing pipeline; these limitations shall be met by the sensor and not
by SN65LVDS324 logic.
Figure 5. VSYNC and HSYNC Output Relation to Active Video Frames
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HSYNC is asserted (driven high) by default. HSYNC is driven low during the active video data stream transfer,
as illustrated in Figure 6. HSYNC may be de-asserted (driven low) while VSYNC is asserted or de-asserted.
As shown in Figure 6, the HSYNC output is generally asserted following an EOL (End of Line) indication from the
image sensor, and de-asserted (driven low) following a SOL (Start of Line) indication. Figure 6 further illustrates
the data expected on the output interface during blanking periods.
Figure 6. HSYNC Output Relation to Line Data Stream
NOTE
The SN65LVDS324 overrides the fixed patterns illustrated in Figure 6 (FFF0h and FFFFh
as shown by notes *1 and *2) when line data is received from the sensor during blanking
periods.
Local I2C Interface Overview
The SCL and SDA terminals are used for I2C clock and I2C data, respectively. The SN65LVDS324 I2C interface
conforms to the two-wire serial interface defined by the I2C Bus Specification, Version 2.1 (January 2000), and
supports standard mode transfers up to 400 kbps.
The device address byte is the first byte received following the START condition from the master device. The 7
bit device address for SN65LVDS324 is factory preset to 7'b0101101 (0x2D). Table 2 clarifies the SN65LVDS324
target address.
Table 2. SN65LVDS324 I2C Target Address Description
SN65LVDS324 I2C TARGET Address (1)
(1)
Bit 7 (MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (W/R)
0
1
0
1
1
0
1
0/1
When ADDR=1, Address Cycle is 0x5A (Write) and 0x5B (Read)
The following procedure is followed to write to the SN65LVDS324 I2C registers:
1. The master initiates a write operation by generating a start condition (S), followed by the SN65LVDS324 7-bit
address and a zero-value "W/R" bit to indicate a write cycle.
2. The SN65LVDS324 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within SN65LVDS324) to be written, consisting of one
byte of data, MSB-first.
4. The SN65LVDS324 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
4
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6. The SN65LVDS324 acknowledges the byte transfer.
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the SN65LVDS324.
8. The master terminates the write operation by generating a stop condition (P).
The following procedure is followed to read the SN65LVDS324 I2C registers:
1. The master initiates a read operation by generating a start condition (S), followed by the SN65LVDS324 7-bit
address and a one-value "W/R" bit to indicate a read cycle.
2. The SN65LVDS324 acknowledges the address cycle.
3. The SN65LVDS324 transmit the contents of the memory registers MSB-first starting at the last address
specified.
4. The SN65LVDS324 will wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
5. If an ACK is received, the SN65LVDS324 transmits the next byte of data.
6. The master terminates the read operation by generating a stop condition (P).
Control and Status Registers Overview
CSR's are accessible through the local I2C interface. Refer to Table 3 for SN65LVDS324 CSR descriptions.
Reads from reserved fields not described return zeros, and writes are ignored.
CSR's "SENSOR_CFG" and "PLL_CFG" must be set before the input clock (SCLK) is applied.
Table 3. SN65LVDS324 CSR Bit Field Definitions
ACCESS
ADDRESS
BIT(S)
0x00 – 0x07
7:0
DEVICE_ID
Returns a string of ASCII characters "LVDS324" preceded by one space character.
Addresses 0x00 - 0x07 = {0x20, 0x4C, 0x56, 0x44, 0x53, 0x33, 0x32, 0x34}
R
0x08
7:0
DEVICE_REV
Device revision; returns 0x01
R
0x09
DESCRIPTION
(1)
7
SOFT_RESET
This bit automatically clears when set to '1' and returns zeros when read. When set, the device is
reset to the default condition.
RW
6
TESTMODE_VIDEO
When enabled, the device outputs a known color pattern with SCLK applied. The pattern is 128 lines
of red, 128 of green, and 128 of blue, repeated. CSR addresses 0B, 0C, 0D, and 0E set the active
image area, while addresses 1F, 20, 21, and 22 set the entire frame including blanking.
SENSOR_CFG and PLL_CFG control the bpp, PLL multiplier, and PLL range. The CLKOUT
frequency directly scales the frame rate; for the default 2250x1100 frame, a CLKOUT frequency of
148.5MHz causes 60fps.
0 – Disabled (default)
1 – Enabled
RW
5
LSB_FIRST_OUTPUT
0 – Output data is MSB first; D[15:0] output represents MSB at D0
1 – Output data is LSB first; D[15:0] output represents LSB at D0 (default)
RW
4
SYNC_ACTIVE_HIGH
0 – VSYNC and HSYNC are output low during blanking periods
1 – VSYNC and HSYNC are output high during blanking periods (default)
RW
3
CLK_CENTERED_TIMING
0 – Output timing accommodates long setup time receivers [e.g. DaVinci] (default)
1 – Outputs are clock-centered for relatively matched setup/hold receivers [e.g. OMAP]
RW
SENSOR_CFG
This field shall be written to configure the sensor interface per Table 1.
2:0
(1)
000 – LVDS Parallel 10bpp mode (default)
001 – LVDS Parallel 12bpp mode
010 – 2-Channel 2-Port 12bpp mode
011 – 2-Channel 2-Port 16bpp mode
100 – 1-Channel 4-Lane 12bpp
101 – 1-Channel 4-Lane 14bpp
110 – 1-Channel 4-Lane 16bpp
111 – 1-Channel 2-Lane 12bpp
mode
mode
mode
mode
RW
R = Read Only; RW = Read/Write (only reads return undetermined values)
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Table 3. SN65LVDS324 CSR Bit Field Definitions (continued)
ADDRESS
BIT(S)
ACCESS
DESCRIPTION
(1)
7
CLKOUT_PLL_LOCK
0 – Output pixel clock PLL not locked
1 – Output pixel clock PLL locked
6
VCM_MODE
0 – Selects Low common mode voltage range
1 – Selects High common mode voltage range (default)
RW
D_SLEW_RATE
Controls the rise and fall time for D[15:0].
00 – Slowest; sets to 50% of the baseline speed
01 – Slower; sets to 75% of the baseline speed
10 – Baseline (default)
11 – Fastest; sets to 150% of the baseline speed
RW
5:4
R
PLL_CFG
This field sets the allowable SCLK frequency range, based on the mode set by SENSOR_CFG. The
register defaults to 10 (and 01 for the 14bpp mode).
spacer
LVDS Parallel 10/12bpp (PLL Multiplier = 2)
00 – SCLK = 18.5 to 33MHz,
CLKOUT = 37 to 66MHz
01 – SCLK = 31 to 60MHz,
CLKOUT = 62 to 120MHz
10 – SCLK = 58 to 81MHz,
CLKOUT = 116 to 162MHz
11 – Reserved
spacer
2-Channel 2-Port 12bpp and 1-Channel 4-Lane 12bpp (PLL Multiplier = 2/3)
0x0A
00 – SCLK = 55.5 to 99MHz,
CLKOUT = 37 to 66MHz
01 – SCLK = 97 to 180MHz,
CLKOUT = 64.7 to 120MHz
10 – SCLK = 178 to 243MHz,
CLKOUT = 118.7 to 162MHz
11 – Reserved
1:0
spacer
2-Channel 2-Port 16bpp and 1-Channel 4-Lane 16bpp (PLL Multiplier = 1/2)
00 – SCLK = 74 to 120MHz,
CLKOUT = 37 to 60MHz
01 – SCLK = 118 to 180MHz,
CLKOUT = 59 to 90MHz
10 – SCLK = 178 to 222MHz,
CLKOUT = 89 to 111MHz
11 – SCLK = 220 to 324MHz,
CLKOUT = 110 to 162MHz
RW
spacer
1-Channel 4-Lane 14bpp (PLL Multiplier = 4/7)
00 – SCLK = 120 to 220MHz,
CLKOUT = 68.6 to 125.7MHz
01 – SCLK = 218 to 283.5MHz,
CLKOUT = 124.6 to 162MHz
10 – Reserved
11 – Reserved
spacer
1-Channel 2-Lane 12bpp (PLL Multiplier = 1/3)
00 – SCLK = 55.5 to 99MHz,
CLKOUT = 18.5 to 33MHz
01 – SCLK = 97 to 180MHz,
CLKOUT = 32.3 to 60MHz
10 – SCLK = 178 to 297MHz,
CLKOUT = 59.3 to 99MHz
11 – Reserved
6
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Table 3. SN65LVDS324 CSR Bit Field Definitions (continued)
ADDRESS
BIT(S)
ACCESS
DESCRIPTION
(1)
4:0
FRAME_WIDTH_MSB
The width of the active area; this field is the high order byte. The default is 1920 (0x0780), and this
field's default is 0x07. The max width is 8191.
When TESTMODE_VIDEO is disabled, this field is only used to set SENSOR_SPECIFIC registers
that flag window size errors.
RW
7:0
FRAME_WIDTH_LSB
The width of the active area; this field is the low order byte. The default is 1920 (0x0780), and this
field's default is 0x80. The max width is 8191.
When TESTMODE_VIDEO is disabled, this field is only used to set SENSOR_SPECIFIC registers
that flag window size errors.
RW
4:0
FRAME_HEIGHT_MSB
The height of the active area; this field is the high order byte. The default is 1080 (0x0438), and this
field's default is 0x04. The max height is 8191.
When TESTMODE_VIDEO is disabled, this field is only used to set SENSOR_SPECIFIC registers
that flag window size errors. In LVDS Parallel modes, the height must include all lines between SAVValid and EAV-Valid.
RW
0x0E
7:0
FRAME_HEIGHT_LSB
The height of the active area; this field is the low order byte. The default is 1080 (0x0438), and this
field's default is 0x38. The max height is 8191.
When TESTMODE_VIDEO is disabled, this field is only used to set SENSOR_SPECIFIC registers
that flag window size errors. In LVDS Parallel modes, the height must include all lines between SAVValid and EAV-Valid.
RW
0x0F – 0x1E
7:0
SENSOR_SPECIFIC
These are sensor-specific status registers, and depend on SENSOR_CFG. They are further
described by Table 4 through Table 6.
RW
4:0
TESTMODE_WIDTH_MSB
Applies only when TESTMODE_VIDEO is enabled, and configurable up to 8191 pixels. This field
controls the high order byte of the frame width including blanking; the default is 2250 (0x08CA), and
this field's default is 0x08.
For 720p, a width of 1500 (0x05DC) facilitates 60fps with 74.25MHz.
RW
7:0
TESTMODE_WIDTH_LSB
Applies only when TESTMODE_VIDEO is enabled, and configurable up to 8191 pixels. This field
controls the low order byte of the frame width including blanking; the default is 2250 (0x08CA), and
this field's default is 0xCA.
For 720p, a width of 1500 (0x05DC) facilitates 60fps with 74.25MHz.
RW
4:0
TESTMODE_HEIGHT_MSB
Applies only when TESTMODE_VIDEO is enabled, and configurable up to 8191 pixels. This field
controls the high order byte of the frame height including blanking; the default is 1100 (0x044C), and
this field's default is 0x04.
For 720p, a height of 825 (0x0339) facilitates 60fps with 74.25MHz.
RW
0x22
7:0
TESTMODE_ HEIGHT_LSB
Applies only when TESTMODE_VIDEO is enabled, and configurable up to 8191 pixels. This field
controls the low order byte of the frame height including blanking; the default is 1100 (0x044C), and
this field's default is 0x4C.
For 720p, a height of 825 (0x0339) facilitates 60fps with 74.25MHz.
RW
0x23 – 0x30
7:0
RESERVED
These registers are reserved for factory test. Do not write to them.
RW
0x0B
0x0C
0x0D
0x1F
0x20
0x21
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Table 4. Sensor-Specific Registers for Aptina Modes
ADDRESS
BIT(S)
6
FILLER_EN
0 – FLR codes are not used in data stream
1 – FLR codes are used in data stream (default)
RW
5
CRC_EN
0 – CRC is not used in the data stream
1 – CRC is used in the data stream (default)
RW
7
CLEAR_STATUS
When a '1' is written to this field, the status bits in 0x10 and 0x11 are cleared, and this bit is autocleared to a zero value (always returns zero when read)
W
3
CRC_ERR_LANE3
0 – No checksum error detected (default)
1 – Checksum error detected
Note: Bits in registers 0x10 and 0x11 are latched and cleared only when the CLEAR_STATUS field
is written.
R
2
CRC_ERR_LANE2; same bit function as CRC_ERR_LANE3 but applied to LANE 2.
R
1
CRC_ERR_LANE1; same bit function as CRC_ERR_LANE3 but applied to LANE 1.
R
0
CRC_ERR_LANE0; same bit function as CRC_ERR_LANE3 but applied to LANE 0.
R
5
UNKNOWN_SYNC_CODE
0 – No unexpected sync code (default)
1 – Sync code (final word of sync_code) does not match a defined type
R
4
SOF_ERR
0 – No SOF error occurred (default)
1 – SOF was detected when it was unexpected
R
3
SOL_ERR
0 – No SOL error occurred (default)
1 – SOL was detected when it was unexpected
R
2
SOV_ERR
0 – No SOV error occurred (default)
1 – SOV was detected when it was unexpected
R
0x0F
0x10
0x11
(1)
8
ACCESS (1)
DESCRIPTION
R = Read Only; RW = Read/Write; W = Write Only (reads return undetermined values)
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Table 5. Sensor-Specific Registers for Panasonic Modes
ADDRESS
BIT(S)
0x0F
7:0
0x10
0x11
(1)
ACCESS (1)
DESCRIPTION
Reserved.
R
7
CLEAR_STATUS
When a '1' is written to this field, the status bits in 0x11 are cleared, and this bit is auto-cleared to a
zero value (always returns zero when read)
W
7
FRAME_SIZE_ERROR
0 – Start up sequence has not identified a frame size error, decode window applied.
1 – Start up sequence identified a frame size error, decode window is not applied
R
5
UNKNOWN_SYNC_CODE
When set to'1', sync code (final word of sync_code) does not match a defined type
R
4
SOF_ERR
When set to '1', SOF was detected when it was unexpected per the decode window.
R
3
SOL_ERR
When set to '1', SOL was detected when it was unexpected per the decode window.
R
1
EOF_ERR
When set to '1', EOF was detected when it was unexpected per the decode window.
R
0
EOL_ERR
When set to '1', EOL was detected when it was unexpected per the decode window.
R
R = Read Only; W = Write Only
Table 6. Sensor-Specific Registers for Sony Modes
ADDRESS
BIT(S)
0x0F
7:0
0x10
0x11
(1)
ACCESS (1)
DESCRIPTION
Reserved.
R
7
CLEAR_STATUS
When a '1' is written to this field, the status bits in 0x11 are cleared, and this bit is auto-cleared to a
zero value (always returns zero when read)
W
7
FRAME_SIZE_ERROR
0 – Start up sequence has not identified a frame size error, decode window applied.
1 – Start up sequence identified a frame size error, decode window is not applied
R
5
UNKNOWN_SYNC_CODE
When set to '1', sync code (final word of sync_code) does not match a defined type
R
4
SAV_VALID_ERR
When set to '1', SAV (Valid Line) was unexpectedly detected per the decode window.
R
3
SAV_INVALID_ERR
When set to '1', SAV (Invalid Line) was unexpectedly detected per the decode window.
R
1
EAV_VALID_ERR
When set to '1', EAV (Valid Line) was unexpectedly detected per the decode window.
R
0
EAV_INVALID_ERR
When set to '1', EAV (Invalid Line) was unexpectedly detected per the decode window.
R
R = Read Only; W = Write Only (reads return undetermined values)
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1
2
3
4
5
6
ZQL PACKAGE
(TOP VIEW)
SCL
SDA
VSYNC
D14
D13
D12
SD0N
SD0P
HSYNC
D15
D11
D10
SD1N
SD1P
VCC
GND
D9
D8
SCLKN
SCLKP
VCCA
GNDA
D7
D6
SD2N
SD2P
GND
D5
D4
SD3N
SD3P
GNDA
GND
D3
D2
SD4N
SD4P
VCCA
VCC
D1
D0
SD5N
SD5P
GNDA
VCCA
CLKOUT
RST#
SD6P
SD7P
SD8P
SD9P
SD10P
SD11P
SD6N
SD7N
SD8N
SD9N
SD10N
SD11N
A
B
C
D
E
F
G
H
J
K
PIN FUNCTIONS
PIN
SIGNAL
SD[11:0]P/N
SubLVDS Input
(Failsafe)
SCLKP/N
CLKOUT
CMOS Output
HSYNC
SDA
GND
Parallel Output Clock.
Parallel Output Vertical Sync.
CMOS Input
(Failsafe)
CMOS
Input/Output
(Failsafe)
GNDA
VCCA
SubLVDS Input Clock.
In 2-Channel 2-Port mode, this input is the Channel 1 clock.
Parallel Output Horizontal Sync.
VSYNC
RST
SubLVDS Input Data Lanes with 100Ω differential termination. In the 2-Channel 2-Port
configurations, SD2P/N is used as Channel 2 clock.
See Table 1 for sensor SubLVDS signal mapping per configuration.
Parallel Output Pixel Data.
Pixel data outputs beyond the pixel data width configuration are driven low.
D[15:0]
SCL
DESCRIPTION
I/O
Local I2C Programming Interface Clock Signal.
Logic Reset. Active when Low.
Local I2C Programming Interface Data Signal.
Reference Ground for Analog Circuits.
Power Supply
VCC
1.8V Power Supply for Analog Circuits.
Reference Ground for Digital Circuits.
1.8V Power Supply for Digital Circuits.
ORDERING INFORMATION
(1)
10
PART NUMBER
PART MARKING
PACKAGE / SHIPPING (1)
SN65LVDS324ZQLR
LVDS324
59-ball PBGA / Reel
For the most current package and ordering information, see the TI web site at www.ti.com.
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ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNITS
V
Supply Voltage Range
VCCA, VCC
–0.3 to 2.175
Input Voltage Range
All Input Terminals
–0.5 to 2.175
V
Storage temperature
TS
–65 to 150
°C
Electrostatic discharge
(1)
(2)
(3)
Human Body Model
(2)
Charged-device model
±4
(3)
kV
±1.5
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Tested in accordance with JEDEC Standard 22, Test Method A114-B
Tested in accordance with JEDEC Standard 22, Test Method C101-A
THERMAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
(1)
TEST CONDITIONS
MIN
TYP MAX
UNIT
73.9
°C/W
θJA
Junction-to-free-air thermal resistance
High-K JEDEC test board, 2s2p (double signal layer,
double buried power plane), no air flow
θJCT
Junction-to-case-top thermal resistance
Cu cold plate measurement process
30.6
°C/W
θJB
Junction-to-board thermal resistance
EIA/JESD 51-8
37.7
°C/W
ψJT
Junction-to-top of package
EIA/JESD 51-2
1.3
°C/W
ψJB
Junction-to-board
EIA/JESD 51-6
36.9
°C/W
TJ
Junction temperature
(1)
125
°C
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX
UNIT
VCCA
Power supply; analog circuits
1.65
1.8
1.95
V
VCC
Power supply; digital circuits
1.65
1.8
1.95
V
fNOISE < 1MHz
100
fNOISE > 1MHz
40
VCCn(PP)
Power supply voltage noise
|VID|
Magnitude of differential input voltage; see Figure 7
90
350
CSR 0A[6] = 0
100
650
CSR 0A[6] = 1
550
1200
mV
mV
VCM
Input common mode voltage; see Figure 7
VCM
Peak to peak input common mode voltage variation; see Figure 8
50
mV
VIN_DC
SubLVDS receiver input voltage range
1400
mV
VID_OS
Differential input voltage overshoot/undershoot; see Figure 9
20%
TA
Operating free-air temperature
TCASE
Case temperature
101
°C
fI2C
Local I2C interface operating frequency
400
kHz
fCLK
SubLVDS input clock (SCLKP/N) frequency
324
MHz
tSETUP
SubLVDS data setup time to SCLKP/N
transition; see Figure 10
LVDS Parallel modes
tHOLD
SubLVDS data hold time after SCLKP/N
transition; see Figure 10
LVDS Parallel modes
tDUTCLK
SubLVDS CLK input clock duty cycle
CL
Parallel output load capacitance (1)
(1)
–40
85
18.5
1500
All other modes
°C
ps
350
1500
All other modes
mV
ps
350
45%
55%
5
6
pF
The SN65LVDS324 supports up to 10pF parallel output load capacitance under test conditions.
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DC ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VTHL
Low-level differential input voltage threshold
VTHH
High-level differential input voltage threshold
VIL
Low-level control signal input voltage
SCL, SDA
VIH
High-level control signal input voltage
SCL, SDA
VOH
High-level output voltage
IOH = –2 mA
VOL
Low-level output voltage
IOL = 2 mA
IOS
Short circuit output current
Output VOH driving GND short
ILEAK
Failsafe input leakage current
VCC = 0; VCC(PIN) =1.8 V
IIH
High level input current
IIL
Low level input current
Active current
RDIFF
Differential termination resistance
RRST
Reset input resistance
CIN
Input pin capacitance
UNIT
mV
40
0.3×VCC
0.7×VCC
mV
V
V
1.3
V
0.4
–35
V
mA
10
µA
5
µA
5
µA
LVDS Parallel 1080p60
89
125
2-Channel 2-Port 1080p60
1-Channel 4-Lane 1080p60
83
120
1-Channel 2-Lane 720p60
(1)
(2)
(3)
MAX
–40
VSD[11:0]P – VSD[11:0]N, VSCLKP – VSCLKN
SDA, SCL
(2) (3)
ICC
MIN TYP (1)
TEST CONDITIONS
mA
74
100
80
100
125
Ω
120
150
180
kΩ
1.5
pF
All typical values are at VCC = 1.8V and TA = 25°C
VCC = 1.95V; TA = 0°C; CL = 6pF; Worst case test pattern
VCC = 1.8V; TA = 25°C; CL = 5pF; Typical power test pattern
SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
FCLKOUT CLKOUT frequency
MIN
CL = 6 pF
18.5
CL = 6 pF; CSR 09[3] = 1
1.5
CL = 6 pF; CSR 09[3] = 0
3.8
CL = 6 pF; CSR 09[3] = 1
1.5
CL = 6 pF; CSR 09[3] = 0
0.2
tdel
Data valid to CLKOUT↑ (see Figure 11)
tpd
CLKOUT↑ to data switching (see Figure 11)
ten
Enable time, RST ↑ to output valid and CLKOUT meets
electrical specifications
FCLKOUT = 148.5 MHz,
See Figure 12
tr
Rise transition time, output (20% to 80%)
CL = 6 pF, CSR 0A[5:4] = 10
450
tf
Fall transition time, output (80% to 20%)
CL = 6 pF, CSR 0A[5:4] = 10
450
tdc
CLKOUT duty cycle
tj
CLKOUT residual jitter
(1)
12
45%
Peak to peak
TYP (1)
MAX
UNIT
162
MHz
ns
ns
2
ms
750
1300
ps
750
1300
55%
370
ps
All typical values are at VCC = 1.8V and TA = 25°C.
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Figure 7. SubLVDS Input Voltage Definitions
Figure 8. SubLVDS Delta Common Mode Input Voltage Definition
Figure 9. VID Overshoot Definition
SCLK
tSETUP t HOLD
SD[0:11]
Figure 10. SubLVDS Timing Definitions
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tdel
CLKOUT
tpd
D[15:0]
HSYNC
VSYNC
Figure 11. CMOS Output Timing Waveforms
Figure 12. Device Enable Waveforms
14
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TYPICAL APPLICATIONS
spacer
The SN65LVDS324 offers several operating modes, as described in this section. The typical mode of 1080p60
involves a 148.5MHz output clock.
The parallel output video interface provides up to 16-bits of data per pixel, a vertical synchronization signal
(VSYNC), and a horizontal synchronization signal (HSYNC) that are all synchronous to the output clock,
CLKOUT. VSYNC and HSYNC are by default logically active high, and output a high logic level during blanking
periods.
The following application diagrams illustrate each high-level typical configuration given in Table 1.
Sony LVDS Parallel 10-Bit Mode
Figure 13 illustrates the LVDS Parallel 10-bit mode for 1080p60 operation.
CLKOUT = 148.5MHz
D[15:10] Output = 6’b0
DSP I/O @ 1.8V CMOS
LVDS Parallel 10-Bit 1080p60
LVDS DDR @ 74.25MHz
1.8V
SN65LVDS324
VCC
VCCA
37.125 MHz
RST
NC
D[15:10]
D[9:0]
CLKOUT
VSYNC
HSYNC
SD[11:2]P
SD[11:2]N
SCLKP/N
D[11:2]_P
D[11:2]_N
CLK_P/N
1080p60
SD[1:0]P/N
IMAGE
SENSOR
1.8V
SDI
SCK
SDO
1.5kΩ
SCL
SDA
< 1cm difference in length
CLKIN
Digital Signal
Processor
3x 10Ω
Configuration and Control
CSR 09[2:0] = 3’b000
CSR 0A[1:0] = 2’b10
Figure 13. LVDS Parallel 10bpp Application
In this configuration, the image sensor transmits 10-bit video with a DDR reference clock operating at 74.25MHz.
The SN65LVDS324 provides a 2x PLL to convert the 74.25MHz SubLVDS input to a 148.5MHz pixel clock
output (CLKOUT) for the 10-bit output interface.
An SPI-like serial bus is used to configure and control the sensor in this typical application example. The DSP
shall properly configure the sensor to the particular target application, which may involve setting the electrical
interface and optical gain settings.
The SN65LVDS324 identifies sync codes from the data stream to identify vertical and horizontal sync conditions,
and sets the outputs HSYNC and VSYNC appropriately.
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TYPICAL APPLICATIONS (continued)
Sony LVDS Parallel 12-Bit Mode
Figure 14 illustrates the 12-bit LVDS Parallel mode for 1080p60 operation. This mode operates identically to the
LVDS Parallel 10-bit mode other than the data width and sync codes.
CLKOUT = 148.5MHz
D[15:12] Output = 4’b0
DSP I/O @ 1.8V CMOS
LVDS Parallel 12-Bit 1080p60
LVDS DDR @ 74.25MHz
1.8V
SN65LVDS324
VCC
VCCA
37.125 MHz
RST
NC
D[15:12]
D[11:0]
CLKOUT
VSYNC
HSYNC
SD[11:0]P
SD[11:0]N
SCLKP/N
D[11:0]_P
D[11:0]_N
CLK_P/N
1080p60
SD[1:0]P/N
IMAGE
SENSOR
1.8V
SDI
SCK
SDO
1.5kΩ
SCL
SDA
< 1cm difference in length
CLKIN
Digital Signal
Processor
3x 10Ω
Configuration and Control
CSR 09[2:0] = 3’b001
CSR 0A[1:0] = 2’b10
Figure 14. LVDS Parallel 12bpp Application
Panasonic 2-Channel 2-Port 12-Bit Mode
Figure 15 illustrates the 1080p60 2-Channel 2-Port 12-bit operating mode.
1.8V
CLKOUT = 148.5MHz
D[15:12] Output = 4’b0
DSP I/O @ 1.8V CMOS
SN65LVDS324
2-Channel 2-Port
12-Bit 1080p60
LVDS DDR @ 222.75MHz
VCC
VCCA
37.125 MHz
RST
NC
D[15:12]
D[11:0]
CLKOUT
VSYNC
HSYNC
CH1[1:0]_P/N
SD[1:0]P/N
SD[4:3]P/N
SCLKP/N
SD2P/N
SD[11:5]P/N
CLKIN
CH2[1:0]_P/N
CLK1_P/N
CLK2_P/N
1080p60
IMAGE
SENSOR
1.8V
1.5k Ω
SDI
SCK
SDO
Digital Signal
Processor
Configuration
and Control
CSR 09[2:0] = 3’b010
CSR 0A[1:0] = 2’b10
SCL
SDA
< 1cm difference in length
Figure 15. 2-Channel 2-Port 12bpp Application
The channel 2 clock is not guaranteed to be synchronous with channel 1; the SN65LVDS324 Word Alignment
function provides the data synchronization between channel 1 and channel 2. If the sensor output is dual-frame
WDR, the SN65LVDS324 transmits the data for both frames.
16
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TYPICAL APPLICATIONS (continued)
Panasonic 2-Channel 2-Port 16-bit Mode
Figure 16 illustrates the 16-bit color 1080p60 2-Channel 2-Port operating mode.
CLKOUT = 148.5MHz
DSP I/O @ 1.8V CMOS
1.8V
SN65LVDS324
2-Channel 2-Port
16-Bit 1080p60
LVDS DDR @ 297MHz
VCC
VCCA
37.125 MHz
RST
CH1[1:0]_P/N
SD[1:0]P/N
SD[4:3]P/N
SCLKP/N
SD2P/N
SD[11:5]P/N
D[15:0]
CLKOUT
VSYNC
HSYNC
CLKIN
CH2[1:0]_P/N
CLK1_P/N
CLK2_P/N
1080p60
IMAGE
SENSOR
1.8V
SDI
SCK
SDO
Digital Signal
Processor
1.5k Ω
Configuration
and Control
CSR 09[2:0] = 3’b011
CSR 0A[1:0] = 2’b11
SCL
SDA
< 1cm difference in length
Figure 16. 2-Channel 2-Port 16bpp Application
Aptina 1-Channel 4-Lane 12-bit Mode
Figure 17 illustrates the 1080p60 1-Channel 4-Lane 12-bit per pixel operating mode with an image sensor pixel
clock frequency is 148.5MHz (222.75MHz SubLVDS clock frequency). In this configuration, the SN65LVDS324
outputs the parallel pixel clock (CLKOUT) at 148.5MHz by implementing a PLL operating with a 2/3 multiplier
from the SubLVDS clock input (SCLKP/N).
CLKOUT = 148.5MHz
D[15:12] Output = 4’b0
DSP I/O @ 1.8V CMOS
1-Channel 4-Lane
12-Bit 1080p60
LVDS DDR @ 222.75MHz
1.8V
SN65LVDS324
VCC
VCCA
27MHz
Digital Signal
Processor
NC D[15:12]
D[11:0]
CLKOUT
VSYNC
HSYNC
SD[3:0]P
SD[3:0]N
SCLKP/N
SD[11:4]P/N
CLKIN
RST
SLVS[3:0]_P
SLVS[3:0]_N
SLVSC_P/N
1080p60
1.8V
IMAGE
SENSOR
2x
1.5k Ω
SCL
SDA
SCL
SDA
< 1cm difference in length
Configuration and Control
CSR 09[2:0] = 3’b100
CSR 0A[1:0] = 2’b10
Figure 17. 1-Channel 4-Lane 12bpp Application
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TYPICAL APPLICATIONS (continued)
Aptina 1-Channel 4-Lane 14-bit Mode
Figure 18 illustrates the 1080p60 1-Channel 4-Lane 14-bit per pixel operating mode. Some image sensors utilize
a compression method in 14-bit mode that communicates compressed data in 14 bits per pixel that can be
expanded to 16 or 20 bits per pixel by the DSP video processing pipeline.
CLKOUT = 74.25MHz
D[15:14] Output = 2’b0
DSP I/O @ 1.8V CMOS
1-Channel 4-Lane
14-Bit 1080p60
LVDS DDR @ 129.937MHz
1.8V
SN65LVDS324
VCC
VCCA
27MHz
Digital Signal
Processor
SD[3:0]P
SD[3:0]N
SCLKP/N
SD[11:4]P/N
NC D[15:14]
D[13:0]
CLKOUT
VSYNC
HSYNC
CLKIN
RST
SLVS[3:0]_P
SLVS[3:0]_N
SLVSC_P/N
720p60
1.8V
IMAGE
SENSOR
2x
1.5k Ω
SCL
SDA
SCL
SDA
< 2cm difference in length
Configuration and Control
CSR 09[2:0] = 3’b101
CSR 0A[1:0] = 2’b01
Figure 18. 1-Channel 4-Lane 14bpp Application
Aptina 1-Channel 4-Lane 16-bit Mode
Figure 19 illustrates the 1080p60 1-Channel 4-Lane 16-bit per pixel operating mode.
CLKOUT = 148.5MHz
DSP I/O @ 1.8V CMOS
1-Channel 4-Lane
16-Bit 1080p60
LVDS DDR @ 297MHz
1.8V
SN65LVDS324
VCC
VCCA
27MHz
Digital Signal
Processor
SD[3:0]P
SD[3:0]N
SCLKP/N
SD[11:4]P/N
D[15:0]
CLKOUT
VSYNC
HSYNC
CLKIN
RST
SLVS[3:0]_P
SLVS[3:0]_N
SLVSC_P/N
1080p60
1.8V
IMAGE
SENSOR
2x
1.5k Ω
SCL
SDA
SCL
SDA
< 1cm difference in length
Configuration and Control
CSR 09[2:0] = 3’b110
CSR 0A[1:0] = 2’b11
Figure 19. 1-Channel 4-Lane 16bpp Application
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TYPICAL APPLICATIONS (continued)
Aptina 1-Channel 2-Lane 12-bit Mode
Figure 20 illustrates the 720p60 1-Channel 2-Lane 12-bit per pixel operating mode.
CLKOUT = 74.25MHz
D[15:12] Output = 4’b0
DSP I/O @ 1.8V CMOS
1-Channel 2-Lane
12-Bit 1080p60
LVDS DDR @ 222.75MHz
1.8V
SN65LVDS324
VCC
VCCA
27MHz
Digital Signal
Processor
NC D[15:12]
D[11:0]
CLKOUT
VSYNC
HSYNC
SD[1:0]P
SD[1:0]N
SCLKP/N
SD[11:2]P/N
CLKIN
RST
SLVS[1:0]_P
SLVS[1:0]_N
SLVSC_P/N
720p60
1.8V
IMAGE
SENSOR
2x
1.5k Ω
SCL
SDA
SCL
SDA
< 2cm difference in length
Configuration and Control
CSR 09[2:0] = 3’b111
CSR 0A[1:0] = 2’b10
Figure 20. 1-Channel 2-Lane 12bpp Application
Decoupling Recommendations
To minimize the power supply noise floor, provide good decoupling near the SN65LVDS324 power pins. The use
of four ceramic capacitors (2x 0.01 µF and 2x 0.1 µF) provides good performance. At the very least, it is
recommended to install one 0.1 µF and one 0.01 µF capacitor near the SN65LVDS324. To avoid large current
loops and trace inductance, the trace length between decoupling capacitors and device power inputs pins must
be minimized. Placing the capacitor underneath the SN65LVDS324 on the bottom of the PCB is often a good
choice.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN65LVDS324ZQLR
ACTIVE
Package Type Package Pins Package Qty
Drawing
BGA
MICROSTAR
JUNIOR
ZQL
59
1000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
Call TI
Level-3-260C-168 HR
(4)
-40 to 85
LVDS324
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65LVDS324ZQLR
Package Package Pins
Type Drawing
BGA MI
CROSTA
R JUNI
OR
ZQL
59
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
4.8
B0
(mm)
K0
(mm)
P1
(mm)
7.3
1.5
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Jan-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65LVDS324ZQLR
BGA MICROSTAR
JUNIOR
ZQL
59
1000
336.6
336.6
31.8
Pack Materials-Page 2
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