TI SN65LVDS3487D

SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L – JULY 1997 – REVISED JULY 2007
HIGH-SPEED DIFFERENTIAL LINE DRIVERS
DESCRIPTION
The SN55LVDS31, SN65LVDS31, SN65LVDS3487,
and SN65LVDS9638 are differential line drivers that
implement the electrical characteristics of low-voltage
differential signaling (LVDS). This signaling
technique lowers the output voltage levels of 5-V
differential standard levels (such as TIA/EIA-422B) to
reduce the power, increase the switching speeds,
and allow operation with a 3.3-V supply rail. Any of
the four current-mode drivers will deliver a minimum
differential output voltage magnitude of 247 mV into
a 100-Ω load when enabled.
The intended application of these devices and
signaling technique is both point-to-point and
multidrop (one driver and multiple receivers) data
transmission over controlled impedance media of
approximately 100 Ω. The transmission media may
be printed-circuit board traces, backplanes, or
cables. The ultimate rate and distance of data
transfer is dependent upon the attenuation
characteristics of the media and the noise coupling
to the environment.
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4A
4Y
4Z
G
3Z
3Y
3A
3
2
1
20 19
4A
NC
SN55LVDS31FK
(TOP VIEW)
1Z
4
18 4Y
G
5
17 4Z
NC
6
16 NC
2Z
7
15 G
2Y
8
14 3Z
9
10 11 12 13
3Y
•
15
VCC
•
•
•
16
2
3A
•
1
NC
•
•
•
1A
1Y
1Z
G
2Z
2Y
2A
GND
1Y
•
SN55LVDS31 . . . J OR W
SN65LVDS31 . . . D OR PW
(Marked as LVDS31 or 65LVDS31)
(TOP VIEW)
1A
•
Meet or Exceed the Requirements of ANSI
TIA/EIA-644 Standard
Low-Voltage Differential Signaling With
Typical Output Voltage of 350 mV and 100-Ω
Load
Typical Output Voltage Rise and Fall Times of
500 ps (400 Mbps)
Typical Propagation Delay Times of 1.7 ns
Operate From a Single 3.3-V Supply
Power Dissipation 25 mW Typical Per Driver
at 200 MHz
Driver at High Impedance When Disabled or
With VCC = 0
Bus-Terminal ESD Protection Exceeds 8 kV
Low-Voltage TTL (LVTTL) Logic Input Levels
Pin Compatible With AM26LS31, MC3487, and
μA9638
Cold Sparing for Space and High Reliability
Applications Requiring Redundancy
2A
•
GND
FEATURES
SN65LVDS3487D
(Marked as LVDS3487 or 65LVDS3487)
(TOP VIEW)
1A
1Y
1Z
1,2EN
2Z
2Y
2A
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
4A
4Y
4Z
3,4EN
3Z
3Y
3A
SN65LVDS9638D (Marked as DK638 or LVDS38)
SN65LVDS9638DGN (Marked as L38)
SN65LVDS9638DGK (Marked as AXG)
(TOP VIEW)
VCC
1A
2A
GND
1
8
2
7
3
6
4
5
1Y
1Z
2Y
2Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2007, Texas Instruments Incorporated
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L – JULY 1997 – REVISED JULY 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The SN65LVDS31, SN65LVDS3487, and SN65LVDS9638 are characterized for operation from –40°C to 85°C.
The SN55LVDS31 is characterized for operation from –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGE (1)
TA
SMALL OUTLINE
–40°C to 85°C
(PW)
MSOP
CHIP CARRIER
(FK)
CERAMIC DIP
(J)
FLAT PACK
(W)
SN65LVDS31D
SN65LVDS31PW
—
—
—
—
SN65LVDS3487D
—
—
—
—
—
SN65LVDS9638D
—
SN65LVDS9638DGN
—
—
—
—
—
SN65LVDS9638DGK
—
—
—
SNJ55LVDS31J
SNJ55LVDS31W
SN55LVDS31W
–55°C to 125°C
(1)
(D)
—
—
—
SNJ55LVDS31FK
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
’LVDS31 logic diagram (positive logic)
logic symbol†
SN55LVDS31, SN65LVDS31
G
G
1A
2A
3A
4A
†
2
4
12
1
7
≥1
G
G
EN
1A
2
3
6
5
9
10
11
15
14
13
1Y
2A
4
12
1
3
7
3A
9
3Z
4Y
4Z
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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4A
10
11
2Z
3Y
6
5
1Z
2Y
2
15
14
13
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L – JULY 1997 – REVISED JULY 2007
SN65LVDS3487 logic diagram
(positive logic)
logic symbol†
SN65LVDS3487
1,2EN
1A
2A
3,4EN
3A
4A
†
4
EN
2
1
3
6
7
12
5
1Y
2Y
11
14
15
5
2Z
13
3,4EN
3Y
3Z
4A
9
10
11
1Z
2Y
2Z
3Y
3Z
12
15
14
13
4Y
4Y
4Z
4Z
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
SN65LVDS9638 logic diagram
(positive logic)
logic symbol†
SN65LVDS9638
1A
2A
†
6
7
3A
10
1Y
4
2A
EN
9
3
1,2EN
1Z
2
1
1A
2
3
8
7
6
5
1Y
1A
2
7
1Z
2Y
2Z
2A
8
3
6
5
1Y
1Z
2Y
2Z
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
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SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
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SLLS261L – JULY 1997 – REVISED JULY 2007
FUNCTION TABLES
SN55LVDS31, SN65LVDS31 (1)
(1)
ENABLES
OUTPUTS
INPUT
A
G
G
Y
H
H
X
H
L
L
H
X
L
H
H
X
L
H
L
L
X
L
L
H
Z
X
L
H
Z
Z
Open
H
X
L
H
Open
X
L
L
H
H = high level, L = low level, X = irrelevant, Z = high impedance
(off)
SN65LVDS3487 (1)
(1)
INPUT A
ENABLE EN
H
H
OUTPUTS
Y
Z
H
L
H
L
H
L
X
L
Z
Z
Open
H
L
H
H = high level, L = low level, X = irrelevant, Z = high impedance
(off)
SN65LVDS9638 (1)
INPUT A
(1)
4
OUTPUTS
Y
Z
H
H
L
L
L
H
Open
L
H
H = high level, L = low level
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SN65LVDS3487, SN65LVDS9638
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SLLS261L – JULY 1997 – REVISED JULY 2007
EQUIVALENT INPUT AND OUTPUT SCHEMATIC DIAGRAMS
EQUIVALENT OF EACH A INPUT
EQUIVALENT OF G, G, 1,2EN OR 3,4EN INPUTS
VCC
VCC
TYPICAL OF ALL OUTPUTS
VCC
50 Ω
50 Ω
Input
Input
10 kΩ
5Ω
Y or Z
Output
7V
7V
300 kΩ
7V
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VCC
Supply voltage range (2)
VI
Input voltage range
–0.5 V to 4 V
–0.5 V to VCC + 0.5 V
Continuous total power dissipation
See Dissipation Rating Table
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Tstg
(1)
(2)
260°C
Storage temperature range
–65°C to 150°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages, except differential I/O bus voltages, are with respect to the network ground terminal.
DISSIPATION RATING TABLE
(1)
(2)
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR (1)
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D (8)
725 mW
5.8 mW/°C
464 mW
377 mW
—
D (16)
950 mW
7.6 mW/°C
608 mW
494 mW
—
DGK
425 mW
3.4 mW/°C
272 mW
221 mW
—
DGN (2)
2.14 W
17.1 mW/°C
1.37 W
1.11 W
—
FK
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
J
1375 mW
11.0 mW/°C
880 mW
715 mW
275 mW
PW (16)
774 mW
6.2 mW/°C
496 mW
402 mW
—
W
1000 mW
8.0 mW/°C
640 mW
520 mW
200 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. See the application note PowerPAD Thermally
Enhanced Package (SLMA002).
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SN65LVDS3487, SN65LVDS9638
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SLLS261L – JULY 1997 – REVISED JULY 2007
RECOMMENDED OPERATING CONDITIONS
MIN NOM
VCC
Supply voltage
3
VIH
High-level input voltage
2
VIL
Low-level input voltage
TA
Operating free-air temperature
3.3
MAX
3.6
UNIT
V
V
0.8
SN65 prefix
–40
85
SN55 prefix
–55
125
V
°C
SN55LVDS31 ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP (1)
VOD
Differential output voltage magnitude
RL = 100 Ω,
See Figure 2
247
ΔVOD
Change in differential output voltage
magnitude between logic states
RL = 100 Ω,
See Figure 2
–50
VOC(SS)
Steady-state common-mode output voltage
See Figure 3
1.125
ΔVOC(SS)
Change in steady-state common-mode output
voltage between logic states
See Figure 3
–50
VOC(PP)
Peak-to-peak common-mode output voltage
See Figure 3
VI = 0.8 V or 2 V, Enabled, No load
VI = 0.8 or 2 V,
RL = 100 Ω, Enabled
VI = 0 or VCC,
Disabled
ICC
Supply current
IIH
High-level input current
VIH = 2
IIL
Low-level input current
IOS
Short-circuit output current
IOZ
High-impedance output current
VO = 0 or 2.4 V
IO(OFF)
Power-off output current
VCC = 0,
Ci
Input capacitance
(1)
340
1.2
MAX
UNIT
454
mV
50
mV
1.375
V
50
mV
50
150
mV
9
20
25
35
mA
0.25
1
4
20
μA
VIL = 0.8 V
0.1
10
μA
VO(Y) or VO(Z) = 0
–4
–24
±12
VOD = 0
VO = 2.4 V
mA
±1
μA
±4
μA
3
pF
All typical values are at TA = 25°C and with VCC = 3.3 V.
SN55LVDS31 SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
tPLH
Propagation delay time, low-to-high-level output
tPHL
Propagation delay time, high-to-low-level output
tr
Differential output signal rise time (20% to 80%)
tf
Differential output signal fall time (80% to 20%)
tsk(p)
tsk(o)
MIN
TYP (1)
MAX
0.5
1.4
4
ns
UNIT
1
1.7
4.5
ns
0.4
0.5
1
ns
0.4
0.5
1
ns
Pulse skew (|tPHL – tPLH|)
0.3
0.6
ns
Channel-to-channel output skew (2)
0.3
0.6
ns
tPZH
Propagation delay time, high-impedance-to-high-level output
5.4
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
2.5
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
8.1
17
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
7.3
15
ns
(1)
(2)
6
TEST CONDITIONS
RL = 100 Ω, CL = 10 pF,
See Figure 2
See Figure 4
All typical values are at TA = 25°C and with VCC = 3.3 V.
tsk(o) is the maximum delay time difference between drivers on the same device.
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SN65LVDS3487, SN65LVDS9638
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SLLS261L – JULY 1997 – REVISED JULY 2007
SN65LVDSxxxx ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
MIN
VOD
Differential output voltage magnitude
RL = 100 Ω,
See Figure 2
247
ΔVOD
Change in differential output voltage
magnitude between logic states
RL = 100 Ω,
See Figure 2
–50
VOC(SS)
Steady-state common-mode output voltage
See Figure 3
1.125
ΔVOC(S
Change in steady-state common-mode output
See Figure 3
voltage between logic states
–50
S)
VOC(PP)
Peak-to-peak common-mode output voltage
SN65LVDS31,
SN65LVDS3487
ICC
Supply current
SN65LVDS9638
UNIT
(1)
MAX
340
454
mV
50
mV
TYP
1.2
See Figure 3
1.37
5
50
mV
50
150
mV
9
20
25
35
1
VI = 0.8 V or 2 V,
Enabled, No load
VI = 0.8 or 2 V,
RL = 100 Ω, Enabled
VI = 0 or VCC,
Disabled
0.25
No load
4.7
8
9
13
VI = 0.8 V or 2 V
RL = 100 Ω
V
mA
mA
IIH
High-level input current
VIH = 2
4
20
μA
IIL
Low-level input current
VIL = 0.8 V
0.1
10
μA
VO(Y) or VO(Z) = 0
–4
–24
IOS
Short-circuit output current
IOZ
High-impedance output current
VO = 0 or 2.4 V
IO(OFF)
Power-off output current
VCC = 0,
Ci
Input capacitance
(1)
±12
VOD = 0
VO = 2.4 V
mA
±1
μA
±1
μA
3
pF
All typical values are at TA = 25°C and with VCC = 3.3 V.
SN65LVDSxxxx SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN65LVDS31
SN65LVDS3487
SN65LVDS9638
MIN TYP (1)
UNIT
MAX
tPLH
Propagation delay time, low-to-high-level output
0.5
1.4
2
ns
tPHL
Propagation delay time, high-to-low-level output
1
1.7
2.5
ns
tr
Differential output signal rise time (20% to 80%)
0.4
0.5
0.6
ns
tf
Differential output signal fall time (80% to 20%)
0.4
0.5
0.6
ns
tsk(p)
Pulse skew (|tPHL – tPLH|)
0.3
0.6
ns
tsk(o)
Channel-to-channel output skew (2)
0
0.3
ns
RL = 100 Ω, CL = 10 pF,
See Figure 2
(3)
tsk(pp)
Part-to-part skew
800
ps
tPZH
Propagation delay time, high-impedance-to-high-level output
5.4
15
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
2.5
15
ns
tPHZ
Propagation delay time, high-level-to-high-impedance output
8.1
15
ns
tPLZ
Propagation delay time, low-level-to-high-impedance output
7.3
15
ns
(1)
(2)
(3)
See Figure 4
All typical values are at TA = 25°C and with VCC = 3.3 V.
tsk(o) is the skew between specified outputs of a single device with all driving inputs connected together and the outputs switching in the
same direction while driving identical specified loads.
tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices
operate with the same supply voltages, same temperature, and have identical packages and test circuits.
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SLLS261L – JULY 1997 – REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION
IOY
Y
II
A
Z
IOZ
VOD
VOY
VOC
VI
(VOY + VOZ)/2
VOZ
Figure 1. Voltage and Current Definitions
2V
1.4 V
0.8 V
Input
tPLH
Y
Input
(see Note A)
VOD
Z
tPHL
100 Ω
± 1%
100%
80%
VOD
CL = 10 pF
(2 Places)
(see Note B)
0
20%
0%
tf
tr
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 2. Test Circuit, Timing, and Voltage Definitions for the Differential Output Signal
Y
Input
(see Note A)
49.9 Ω ± 1% (2 Places)
3V
A
A
0
VOC(PP)
Z
(see Note C)
VOC
CL = 10 pF
(2 Places)
(see Note B)
VOC(SS)
VOC
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, pulse repetition rate (PRR) = 50 Mpps,
pulse width = 10 ± 0.2 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
C. The measurement of VOC(PP) is made on test equipment with a –3-dB bandwidth of at least 300 MHz.
Figure 3. Test Circuit and Definitions for the Driver Common-Mode Output Voltage
8
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SLLS261L – JULY 1997 – REVISED JULY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
49.9 Ω ± 1% (2 Places)
Y
Inputs
(see Note A)
0.8 V or 2 V
Z
1.2 V
G
G
1,2EN or 3,4EN
CL = 10 pF
(2 Places)
(see Note B)
G, 1,2EN,
OR 3,4EN
2V
1.4 V
0.8 V
G
2V
1.4 V
0.8 V
tPZH
VOZ
or
VOY
VOZ
tPHZ
VOY
or
VOZ
tPZL
VOY
100%, ≅1.4 V
50%
0%, 1.2 V
A at 2 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 Only
100%, 1.2 V
50%
0%, ≅1 V
A at 0.8 V, G at VCC and Input to G
or
G at GND and Input to G for ’LVDS31 Only
tPLZ
NOTES: A. All input pulses are supplied by a generator having the following characteristics: tr or tf < 1 ns, pulse repetition rate (PRR) = 0.5 Mpps,
pulse width = 500 ± 10 ns.
B. CL includes instrumentation and fixture capacitance within 6 mm of the D.U.T.
Figure 4. Enable-/Disable-Time Circuit and Definitions
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SLLS261L – JULY 1997 – REVISED JULY 2007
TYPICAL CHARACTERISTICS
SN55LVDS31, SN65LVDS31
SUPPLY CURRENT
vs
FREQUENCY
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
35
I CC − Supply Current − mA
33
t PLH − Low-to-High Propagation Delay Time − ns
1.9
Four Drivers Loaded Per
Figure 3 and Switching
Simultaneously
VCC = 3.6 V
31
29
VCC = 3 V
27
25
VCC = 3.3 V
23
21
19
17
15
50
100
150
200
1.8
1.7
1.6
VCC = 3.3 V
1.5
VCC = 3 V
1.4
VCC = 3.6 V
1.3
1.2
1.1
1
−40
f − Frequency − MHz
−20
60
80
0
20
40
TA − Free-Air Temperature − °C
Figure 5.
Figure 6.
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
t PHL − High-to-Low Propagation Delay Time − ns
1.9
1.8
VCC = 3 V
1.7
1.6
VCC = 3.3 V
1.5
VCC = 3.6 V
1.4
1.3
1.2
1.1
1
−40
−20
60
80
0
20
40
TA − Free-Air Temperature − °C
Figure 7.
10
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100
100
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
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SLLS261L – JULY 1997 – REVISED JULY 2007
APPLICATION INFORMATION
The devices are generally used as building blocks for high-speed point-to-point data transmission where ground
differences are less than 1 V. Devices can interoperate with RS-422, PECL, and IEEE-P1596. Drivers/receivers
approach ECL speeds without the power and dual supply requirements.
TRANSMISSION DISTANCE
vs
SIGNALING RATE
Transmission Distance − m
100
30% Jitter
(see Note A)
10
5% Jitter
(see Note A)
1
24 AWG UTP 96 Ω
(PVC Dielectric)
0.1
10
100
1000
Signaling Rate − Mbps
A.
This parameter is the percentage of distortion of the unit interval (UI) with a pseudorandom data pattern.
Figure 8. Typical Transmission Distance Versus Signaling Rate
1
2
ZO = 100 Ω
3
VCC
4
5
1A
VCC
1Y
4A
1Z
4Y
G
4Z
2Z
G
16
3.3 V
15
0.1 µF
(see Note A)
0.001 µF
(see Note A)
14
13
ZO = 100 Ω
12
See Note B
ZO = 100 Ω
6
7
8
2Y
3Z
2A
3Y
GND
3A
11
10
ZO = 100 Ω
9
NOTES: A. Place a 0.1-µF and a 0.001-µF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitors should be located as close as possible to the device terminals.
B. Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 9. Typical Application Circuit Schematic
Submit Documentation Feedback
11
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L – JULY 1997 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
1/4 ’LVDS31
Strb/Data_TX
Tp Bias on
Twisted-Pair A
Strb/Data_Enable
TP
55 Ω
’LVDS32
5 kΩ
Data/Strobe
55 Ω
3.3 V
TP
20 kΩ
500 Ω
VG on
Twisted-Pair B
1 Arb_RX
500 Ω
20 kΩ
3.3 V
500 Ω
20 kΩ
2 Arb_RX
500 Ω
20 kΩ
3.3 V
7 kΩ
Twisted-Pair B Only
7 kΩ
10 kΩ
Port_Status
3.3 kΩ
NOTES: A.
B.
C.
D.
Resistors are leadless, thick film (0603), 5% tolerance.
Decoupling capacitance is not shown, but recommended.
VCC is 3 V to 3.6 V.
The differential output voltage of the ’LVDS31 can exceed that specified by IEEE1394.
Figure 10. 100-Mbps IEEE 1394 Transceiver
12
Submit Documentation Feedback
SN55LVDS31, SN65LVDS31
SN65LVDS3487, SN65LVDS9638
www.ti.com
SLLS261L – JULY 1997 – REVISED JULY 2007
APPLICATION INFORMATION (continued)
0.01 µF
1
1A
VCC
≈3.6 V
16
5V
0.1 µF
(see Note A)
2
ZO = 100 Ω
3
VCC
4
5
1Y
4A
1Z
4Y
G
4Z
2Z
G
1N645
(2 places)
15
14
ZO = 100 Ω
13
12
See Note B
ZO = 100 Ω
6
7
8
2Y
3Z
2A
3Y
GND
3A
11
10
ZO = 100 Ω
9
A.
Place a 0.1-μF Z5U ceramic, mica, or polystyrene dielectric, 0805 size, chip capacitor between VCC and the ground
plane. The capacitor should be located as close as possible to the device terminals.
B.
Unused enable inputs should be tied to VCC or GND, as appropriate.
Figure 11. Operation With 5-V Supply
COLD SPARING
Systems using cold sparing have a redundant device electrically connected without power supplied. To support
this configuration, the spare must present a high-input impedance to the system so that it does not draw
appreciable power. In cold sparing, voltage may be applied to an I/O before and during power up of a device.
When the device is powered off, VCC must be clamped to ground and the I/O voltages applied must be within the
specified recommended operating conditions.
RELATED INFORMATION
IBIS modeling is available for this device. Contact the local TI sales office or the TI Web site at www.ti.com for
more information.
For more application guidelines, see the following documents:
• Low-Voltage Differential Signaling Design Notes (SLLA014)
• Interface Circuits for TIA/EIA-644 (LVDS) (SLLA038)
• Reducing EMI With LVDS (SLLA030)
• Slew Rate Control of LVDS Circuits (SLLA034)
• Using an LVDS Receiver With RS-422 Data (SLLA031)
• Evaluating the LVDS EVM (SLLA033)
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
9-Oct-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
5962-9762101Q2A
ACTIVE
LCCC
FK
20
1
TBD
5962-9762101QEA
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
5962-9762101QFA
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
5962-9762101VFA
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
SN55LVDS31W
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
SN65LVDS31D
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31DG4
ACTIVE
SOIC
D
16
40
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31DRG4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31NSR
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31NSRG4
ACTIVE
SO
NS
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31PWRG4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS31QPWQ1
OBSOLETE
TSSOP
PW
16
SN65LVDS31QPWRQ1
OBSOLETE
TSSOP
PW
16
SN65LVDS3487D
ACTIVE
SOIC
D
16
40
SN65LVDS3487DG4
ACTIVE
SOIC
D
16
40
SN65LVDS3487DR
ACTIVE
SOIC
D
SN65LVDS3487DRG4
ACTIVE
SOIC
SN65LVDS9638D
ACTIVE
SN65LVDS9638DG4
TBD
POST-PLATE N / A for Pkg Type
Call TI
Call TI
TBD
Call TI
Call TI
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DGK
ACTIVE
MSOP
DGK
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DGKG4
ACTIVE
MSOP
DGK
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DGKR
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DGKRG4
ACTIVE
MSOP
DGK
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DGN
ACTIVE
MSOP-
DGN
8
CU NIPDAU
Level-1-260C-UNLIM
80
Addendum-Page 1
Green (RoHS &
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
9-Oct-2007
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Power
PAD
Lead/Ball Finish
MSL Peak Temp (3)
no Sb/Br)
SN65LVDS9638DGNR
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DGNRG4
ACTIVE
MSOPPower
PAD
DGN
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65LVDS9638DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SNJ55LVDS31FK
ACTIVE
LCCC
FK
20
1
TBD
SNJ55LVDS31J
ACTIVE
CDIP
J
16
1
TBD
A42 SNPB
N / A for Pkg Type
SNJ55LVDS31W
ACTIVE
CFP
W
16
1
TBD
A42 SNPB
N / A for Pkg Type
SNLVDS9638DGNG4
ACTIVE
MSOPPower
PAD
DGN
8
80
Green (RoHS &
no Sb/Br)
CU NIPDAU
POST-PLATE N / A for Pkg Type
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Nov-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN65LVDS31DR
D
16
SITE 27
330
16
6.5
10.3
2.1
8
16
Q1
SN65LVDS31NSR
NS
16
SITE 41
330
16
8.2
10.5
2.5
12
16
Q1
SN65LVDS31PWR
PW
16
SITE 60
330
12
6.67
5.4
1.6
8
12
Q1
SN65LVDS3487DR
D
16
SITE 60
330
16
6.5
10.3
2.1
8
16
Q1
SN65LVDS9638DGKR
DGK
8
SITE 35
330
12
5.3
3.4
1.4
8
12
Q1
SN65LVDS9638DGNR
DGN
8
SITE 35
330
12
5.3
3.4
1.4
8
12
Q1
SN65LVDS9638DR
D
8
SITE 60
330
12
6.4
5.2
2.1
8
12
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
5-Nov-2007
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
SN65LVDS31DR
D
16
SITE 27
342.9
336.6
28.58
SN65LVDS31NSR
NS
16
SITE 41
346.0
346.0
33.0
SN65LVDS31PWR
PW
16
SITE 60
346.0
346.0
29.0
SN65LVDS3487DR
D
16
SITE 60
346.0
346.0
33.0
SN65LVDS9638DGKR
DGK
8
SITE 35
358.0
335.0
35.0
SN65LVDS9638DGNR
DGN
8
SITE 35
358.0
335.0
35.0
SN65LVDS9638DR
D
8
SITE 60
346.0
346.0
29.0
Pack Materials-Page 2
MECHANICAL DATA
MLCC006B – OCTOBER 1996
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
18
17
16
15
14
13
NO. OF
TERMINALS
**
12
19
11
20
10
A
B
MIN
MAX
MIN
MAX
20
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
28
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
9
22
8
44
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
23
7
52
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
24
6
68
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
84
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
B SQ
A SQ
25
5
26
27
28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140 / D 10/96
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a metal lid.
The terminals are gold plated.
Falls within JEDEC MS-004
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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