TI SN65LVDS348D

SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
QUAD HIGH-SPEED DIFFERENTIAL RECEIVERS
FEATURES
D Meets or Exceeds the Requirements of ANSI
D
D
D
D
D
TIA/EIA-644A Standard
Single-Channel Signaling Rates1 up to
560 Mbps
–4 V to 5 V Common-Mode Input Voltage
Range
Flow-Through Architecture
Active Failsafe Assures a High-level Output
When an Input Signal Is not Present
SN65LVDS348 Provides a Wide
Common-Mode Range Replacement for the
SN65LVDS048A or the DS90LV048A
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
550
SN65LVDS352PW
Data Transfer Rate – Mxfr/s
500
450
APPLICATIONS
D Logic Level Translator
D Point-to-Point Baseband Data Transmission
D
D
D
Over 100-Ω Media
ECL/PECL-to-LVTTL Conversion
Wireless Base Stations
Central Office or PABX Switches
DESCRIPTION
The SN65LVDS348, SN65LVDT348, SN65LVDS352,
and SN65LVDT352 are high-speed, quadruple
differential receivers with a wide common-mode input
voltage range. This allows receipt of TIA/EIA-644
signals with up to 3-V of ground noise or a variety of
differential and single-ended logic levels. The ‘348 is in
a 16-pin package to match the industry-standard
footprint of the DS90LV048. The ‘352 adds two
additional VCC and GND pins in a 24-pin package to
provide higher data transfer rates with multiple
receivers in operation. All offer a flow-through
architecture with all inputs on one side and outputs on
the other to ease board layout and reduce crosstalk
between receivers. LVDT versions of both integrate a
110-Ω line termination resistor.
400
SN65LVDS348PW
350
Timer
300
250
200
–60
LVDT Device
Only
215 –1 prbs NRZ, VID = 0.4 V
VIC = 1.2 V, CL = 5.5 pF, 40% Open Eye
4 Receivers Switching, Input Jitter < 45 ps
–40
–20
0
20
40
60
TA – Free-Air Temperature – °C
80
100
(One of Four Shown)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1 The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
Copyright  2002 – 2003 Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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1
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
description (continued)
These receivers also provide 3x the standard’s minimum common-mode noise voltage tolerance. The –4 V to
5 V common-mode range allows usage in harsh operating environments or accepts LVPECL, PECL, LVECL,
ECL, CMOS, and LVCMOS levels without level shifting circuitry. See the Application Information Section for
more details on the ECL/PECL to LVDS interface.
Precise control of the differential input voltage thresholds allows for inclusion of 50 mV of input-voltage
hysteresis to improve noise rejection. The differential input thresholds are still no more than ±50 mV over the
full input common-mode voltage range.
The receiver inputs can withstand ±15 kV human-body model (HBM), with respect to ground, without damage.
This provides reliability in cabled and other connections where potentially damaging noise is always a threat.
The receivers also include a (patent-pending) failsafe circuit that provides a high-level output approximately
600 ns after loss of the input signal. The most common causes of signal loss are disconnected cables, shorted
lines, or powered-down transmitters. This prevents noise from being received as valid data under these fault
conditions. This feature may also be used for Wired-Or bus signaling.
The SN65LVDT348 and SN65LVDT352 include an integrated termination resistor. This reduces board space
requirements and parts count by eliminating the need for a separate termination resistor. This can also improve
signal integrity at the receiver by reducing the stub length from the line termination to the receiver.
The intended application of these devices and signaling technique is for point-to-point baseband data
transmission over controlled impedance media of approximately 100 Ω. The transmission media may be
printed-circuit board traces, backplanes, or cables. The ultimate rate and distance of data transfer is dependent
upon the attenuation characteristics of the media and the noise coupling to the environment.
The SN65LVDS348, SN65LVDT348, SN65LVDS352 and SN65LVDT352 are characterized for operation from
–40°C to 85°C.
SN65LVDS348, SN65LVDT348
D or PW PACKAGE
(TOP VIEW)
RIN1–
RIN1+
RIN2+
RIN2–
RIN3–
RIN3+
RIN4+
RIN4–
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
SN65LVDS352, SN65LVDT352
PW PACKAGE
(TOP VIEW)
1A
1B
2A
2B
EN 1,2
VCCA
AGND
EN 3,4
3A
3B
4A
4B
EN
ROUT1
ROUT2
VCC
GND
ROUT3
ROUT4
EN
1
2
3
4
5
6
7
8
9
10
11
12
NC – No internal connection
2
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24
23
22
21
20
19
18
17
16
15
14
13
NC
1Y
DGND1
VCCD1
2Y
NC
NC
3Y
VCCD2
DGND2
4Y
NC
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
functional block diagrams (one of four receivers shown)
348 Devices
To Three Other Receivers
352 Devices
To One Other Receiver
EN
EN
EN
A
RIN+
ROUT1
Y
RIN–
B
Timer
Timer
SN65LVDT348
Only
SN65LVDT352
Only
Window Comparator
Window Comparator
AVAILABLE OPTIONS
INTEGRATED
TERMINATION
PART NUMBER†
PACKAGE
TYPE
PACKAGE
MARKING
SOIC
LVDS348
SOIC
LVDT348
TSSOP
DL348
TSSOP
DE348
TSSOP
DL352
SN65LVDS348D
n
SN65LVDT348D
SN65LVDS348PW
n
SN65LVDT348PW
SN65LVDS352PW
SN65LVDT352PW
TSSOP
DE352
n
† Add the R suffix to the device type (e.g., SN65LVDS348DR) for taped and reeled carrier.
Function Tables
348 DEVICES
OUTPUTS
INPUTS
VID = VRIN+ – VRIN–
VID ≥ –32 mV
EN
EN
ROUT
H
L or OPEN
H
–100 mV < VID < –32 mV
H
L or OPEN
?
VID ≤ –100 mV
Open
H
L or OPEN
L
H
L or OPEN
H
L or OPEN
X
Z
X
H
Z
X
352 DEVICES
INPUTS
OUTPUTS
VID = VIA – VIB
VID ≥ –32 mV
EN
Y
H
H
–100 mV < VID < –32 mV
H
?
VID ≤ –100 mV
X
H
L
L or OPEN
Z
Open
H
H
H = high level, L = low level, X = irrelevant, Z = high impedance (off), ? = indeterminate
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3
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
equivalent input and output schematic diagrams
VCC
VCC
1 pF
6.5 kΩ
60 kΩ
Attenuation
Network
RIN+, A
200 kΩ
RIN–, B
7V
7V
7V
110 Ω
’LVDT Only
Attenuation
Network
VCC
VCC
100 Ω
37 Ω
ROUT, Y
EN, EN
7V
4
Attenuation
Network
7V
250 kΩ
3 pF
6.5 kΩ
7V
300 kΩ
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range (see Note 1), VCC, VCCA, VCCD1, and VCCD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Voltage range: Enables, ROUT, or Y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
Differential input magnitude VID (LVDT only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 V
RIN+, RIN–, A or B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to 6 V
Electrostatic discharge: Human body model (see Note 2): A, B, RIN+, RIN– and GND . . . . . . . . . . . . . . . . ±15 kV
All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±7 kV
Charged-device model (see Note 3): All pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±500 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to network ground terminal (GND, AGND).
2. Tested in accordance with JEDEC Standard 22, Test Method A114-A.
3. Tested in accordance with JEDEC Standard 22, Test Method C101.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
OPERATING FACTOR‡
ABOVE TA = 25°C
TA = 85°C
POWER RATING
D16
950 mW
7.6 mW/°C
494 mW
PW16
774 mW
6.2 mW/°C
402 mW
PW24
1087 mW
8.7 mW/°C
565 mW
‡ This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with
no air flow.
recommended operating conditions
MIN
NOM
MAX
Supply voltage, VCC, VCCA, VCCD1, and VCCD2
3
3.3
3.6
V
High-level input voltage, VIH
Enables
2
5
V
Low-level input voltage, VIL
Enables
0
0.8
V
VID (LVDT348, 352)
VID (LVDS348, 352)
0.1
0.8
Magnitude of differential input voltage
0.1
3
–4
5
V
–40
85
°C
Input voltage (any combination of common mode or input signals)
Operating free-air temperature, TA
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UNIT
V
5
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER
VITH1
TEST CONDITIONS
Negative-going differential input voltage
threshold
VITH3
Differential input failsafe voltage threshold
VID(HYS)
Differential input voltage hysteresis,
VITH1 – VITH2
ICC
High-level output voltage
Low-level output voltage
Power–off
Power
off in
input
ut current (RIN+,
RIN–, A or B inputs)
LVDT348,
LVDT352
–32
V
0.4
EN at 0 V, No load
Disabled, EN at 0 or EN at VCC
No load
Disabled, EN at 0
mV
mV
2.4
16
20
1.1
4
16
20
1.1
4
V
mA
mA
VI = –4 V,
0 V ≤ VI ≤ 2.4 V,
Other input open
–75
Other input 1.2 V
–20
0
VI = 5 V,
VI = –4 V,
Other input open
0
40
Other input open
–150
0
0 V ≤ VI ≤ 2.4 V,
Other input open
–40
0
VI = 5 V,
VCC = 1.5 V,
Other input open
Other input open
0
80
VI = –4 V or 5 V,
–50
50
VCC = 1.5 V,
Other input at 1.2 V
0 V ≤ VI ≤ 2.4 V,
–20
20
VCC = 1.5 V,
Other input open
VI = –4 V or 5 V,
–100
100
VCC = 1.5 V,
Other input open
VI = 0 V or 2.4 V,
–40
40
4
µA
132
Ω
0
10
µA
0
10
µA
–10
10
µA
LVDS348,
LVDS352
VID = 100 mV,
VIC = –3.9 V or 4.9 V
–4
RT
Differential input resistance
LVDT348,
LVDT352
VCC = 0 V,
VI = 0 V to 2.4 V
VID = 250 mV,
90
IIH
IIL
High-level input current
Enables
Low-level input current
Enables
VIH = 2 V
VIL = 0.8 V
IOZ
High-impedance output current
VO = 0 V
CIN
Input capacitance, RIN+, RIN– input to GND
or A or B input to AGND
VI = 0.4 sin (4E6πft) + 0.5 V
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µA
µA
µA
A
Differential input current
(IRIN+ – IRIN–, or IIA – IIB)
† All typical values are at 25°C and with a 3.3-V supply.
0
µA
A
IID
6
–100
50
Enabled, EN at VCC,
LVDS348,
LVDS352
II(OFF)
See Figure 1 and Table 1
LVDS352,
LVDT352
LVDT348,
LVDT348
LVDT352
mV
–50
LVDS348,
LVDT348
Input
In
ut current (RIN+, RIN–,
RIN ,
A or B inputs)
UNIT
50
Enabled, EN at VCC,
Supply current
MAX
See Figure 1 and Figure 2
IOH = –4 mA
IOL = 4 mA
LVDS348
LVDS348,
LVDS352
II
TYP†
Positive-going differential input voltage
threshold
VITH2
VOH
VOL
MIN
111
5
pF
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
switching characteristics over recommended operating conditions (unless otherwise noted)
MIN
TYP†
MAX
tPLH
tPHL
Propagation delay time, low-to-high-level output
2.5
4
6
ns
Propagation delay time, high-to-low-level output
2.5
4
6
ns
td1
td2
Delay time, failsafe disable time
9
ns
1.5
µs
tsk(p)
tsk(o)
Pulse skew (|tpHL1 – tpLH1|)
Output skew‡
tsk(pp)
tr
Part-to-part skew§
tf
tr
Output signal fall time
tf
tPHZ
Output signal fall time
tPLZ
tPZH
Propagation delay time, low-level-to-high-impedance output
PARAMETER
TEST CONDITIONS
Delay time, failsafe enable time
0.3
CL = 10 pF,
F
See Figure 3
200
ps
150
ps
1
Output signal rise time
Output signal rise time
CL = 1 pF,
F,
See Figure 3
ns
1
ns
650
ps
5
See Figure 4 and
Figure 5
Propagation delay time, high-impedance-to-high-level output
ns
1.2
400
Propagation delay time, high-level-to-high-impedance output
UNIT
ps
9
ns
5
9
ns
8
12
ns
tPZL
Propagation delay time, high-impedance-to-low-level output
8
12
ns
† All typical values are at 25°C and with a 3.3-V supply.
‡ tsk(o) is the magnitude of the time difference between the tPHL or tPLH of all receivers of a single device with all of their inputs connected together.
§ tsk(pp) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate
with the same supply voltages, at the same temperature, and have identical packages and test circuits.
PARAMETER MEASUREMENT INFORMATION
IIA or IRIN+
A or RIN+
Y or ROUT
VID
(VIA + VIB)/2 or
(VRIN+ + VRIN–)/2
VIA or VRIN+
VIC
B or RIN–
IIB or IRIN–
VIB or VRIN–
IOY or IROUT
VOY or VROUT
Figure 1. Voltage and Current Definitions
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
1000 Ω
100 Ω
+
1000 Ω
100 Ω†
VID
+
V2
V1
VO
–
–
10 pF
10 pF
10 pF
+
–
VIC
† Remove for testing LVDT device.
NOTES: A. Input signal of 3 MHz, duty cycle of 50±0.2%, and transition time of < 1ns.
B. Fixture capacitance ±20%.
C. Resistors are metal film, 1% tolerance, and surface mount
VITH1
0V
VID
–100 mV
VO
100 mV
VID
0V
VITH2
VO
Figure 2. VITH1 and VITH2, Input Voltage Threshold Test Circuit and Definitions
Table 1. Receiver Minimum and Maximum Failsafe Input Voltage
FAILSAFE THRESHOLD TEST VOLTAGES
APPLIED VOLTAGES†
RESULTANT INPUTS
VIB (mV)
–3900
VID (mV)
–100
VIC (mV)
–3950
–4000
–3968
–32
–3984
4900
5000
–100
4950
L
4968
5000
–32
4984
H
† Voltage applied for greater than 1.5 µs.
8
O tp t
Output
VIA (mV)
–4000
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L
H
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
A or RIN+
Y or ROUT
VID
VIA or VRIN+
B or RIN–
CL
VOY or VROUT
VIB or VRIN–
A or VRIN+
1.4 V
B or VRIN–
1V
>1.5 µs
0.4 V
VID
0V
–0.2 V
–0.4 V
tPHL
tPLH
td1
VOH
VCC/2
VOL
VOY or VROUT
tf
td2
tr
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 250 kHz,
duty cycle = 50 ±2%, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%.
Figure 3. Timing Test Circuit and Waveforms
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
1.2 V
RIN–
ROUT
500 Ω
RIN+
Inputs
EN
VROUT
10 pF
EN
+
_
VTEST
VTEST
2.5 V
VRIN+
1V
2V
1.4 V
0.8 V
2V
1.4 V
0.8 V
EN
EN
tPZL
tPZL
tPLZ
tPLZ
2.5 V
1.4 V
VOL +0.5 V
VOL
VROUT
VTEST
0V
1.4 V
VRIN+
2V
1.4 V
0.8 V
2V
1.4 V
EN
EN
0.8 V
tPZH
tPZH
tPHZ
tPHZ
VOH
VOH –0.5 V
1.4 V
0V
VROUT
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 500 kHz,
duty cycle = 50 ±2%, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%.
Figure 4. 348 Enable/Disable Time Test Circuit and Waveforms
10
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
PARAMETER MEASUREMENT INFORMATION
B
1.2 V
500 Ω
Y
A
Inputs
EN
VO
+
_
VTEST
10 pF
2.5 V
VTEST
A
1V
2V
1.4 V
0.8 V
EN
tPZL
tPLZ
2.5 V
1.4 V
VOL +0.5 V
VOL
VO
VTEST
A
0V
1.4 V
EN
2V
1.4 V
0.8 V
tPZH
tPHZ
VOH
VOH –0.5 V
1.4 V
0V
VO
NOTE: All input pulses are supplied by a generator having the following characteristics: tr or tf ≤ 1 ns, signaling rate = 500 kHz,
duty cycle = 50 ±2 %, CL includes instrumentation and fixture capacitance within 0,06 mm of the D.U.T and is ±20%.
Figure 5. 352 Enable/Disable Time Test Circuit and Waveforms
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11
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
TYPICAL CHARACTERISTICS
HIGH-TO-LOW PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
LOW-TO-HIGH PROPAGATION DELAY
vs
FREE-AIR TEMPERATURE
5
5
4.5
t PHL – High-to-Low Propagation Delay – ns
t PLH – Low-to-High Propagation Delay – ns
See Figure 3
VCC = 3 V
VCC = 3.3 V
4
VCC = 3.6 V
3.5
3
–50
0
50
See Figure 3
VCC = 3 V
4.5
VCC = 3.3 V
4
VCC = 3.6 V
3.5
3
–50
100
TA – Free-Air Temperature – °C
0
50
TA – Free-Air Temperature – °C
Figure 6
Figure 7
LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
0
TA = 25°C,
VCC = 3.3 V
TA = 25°C,
VCC = 3.3 V
I OH – High-Level Output Current – mA
I OL – Low-Level Output Current – mA
40
30
20
10
0
0
1
2
3
4
5
VOL – Low-Level Output Voltage – V
Figure 8
12
100
–10
–20
–30
–40
0
1
2
3
VOH – High-Level Output Voltage – V
Figure 9
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4
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
TYPICAL CHARACTERISTICS
DATA TRANSFER RATE
vs
FREE-AIR TEMPERATURE
RMS SUPPLY CURRENT
vs
SWITCHING FREQUENCY
110
215 –1 prbs NRZ,
VIC = 1.2 V,
CL = 5.5 pF,
40% Open Eye,
4 Receivers Switching,
VCC = 3.3 V,
SN65LVDS348PW
450
400
I CC – RMS Supply Current – mA
Maximum Transfer Rate – Mxfr/s
500
VID = 0.4 V
350
300
VID = 0.1 V
VID = 0.2 V
250
200
–60
–40
–20
0
20
40
60
80
100
TA – Free-Air Temperature – °C
4 Receivers Switching,
50% Duty Cycle,
CL = 5.5 pF,
TA = 25°C
90
VCC = 3.6 V
VCC = 3.3 V
70
VCC = 3 V
50
30
10
0
50
100
150
200
250
300
f – Switching Frequency – MHz
Figure 11
Figure 10
223 –1 prbs NRZ, TA = 25°C, CL = 5.5 pF,
4 Receivers Switching, VCC = 3.3 V
223 –1 prbs NRZ, TA = 25°C, CL = 5.5 pF,
4 Receivers Switching, VCC = 3.3 V
Figure 12. SN65LVDS348 Eye
Pattern Running at 200 Mxfr/s
Figure 13. SN65LVDS352 Eye
Pattern Running at 200 Mxfr/s
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
impedance matching and reflections
A termination mismatch can result in reflections that degrade the signal at the load. A low source impedance
causes the signal to alternate polarity at the load (oscillates) as shown in Figure 14. High source impedance
results in the signal accumulating monotonically to the final value (stair step) as shown in Figure 15. Both of
these modes result in a delay in valid signal and reduce the opening in the eye pattern. A 10% termination
mismatch results in a 5% reflection (ρ = ZL – ZO/ZL + ZO), even a 1:3 mismatch absorbs half of the incoming
signal. This shows that termination is important in the more critical cases, however, in a general sense, a rather
large termination mismatch is not as critical when the differential output signal is much greater than the receiver
sensitivity.
TIME DOMAIN RESPONSE
0.25
TIME DOMAIN RESPONSE
0.25
ZS = 0 Ω
ZO = 100 Ω
ZT = 132 Ω
V at Load
0.2
ZS = 0 Ω
ZO = 100 Ω
ZT = 90 Ω
0.2
V at Load
VI
0.15
Voltage – V
Voltage – V
VI
0.1
0.05
0.15
0.1
0.05
0
0
0
5
10
15
20
25
t – Time – ns
0
5
10
15
20
25
t – Time – ns
Figure 14. Low-Source Impedance
Figure 15. High-Source Impedance
For example a 200-mV drive signal into a 100-Ω lossless transmission media with a termination resistor of 90 Ω
to 132 Ω results in ~227 mV to 189 mV into the receiver. This would typically be more than enough signal into
a receiver with a sensitivity of ±50 mV assuming no other disturbance or attenuation on the line. The other
factors, which reduce the signal margin, do affect this and therefore it is important to match the impedance as
closely as possible to allow more noise immunity at the receiver.
14
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
active failsafe feature
A differential line receiver commonly has a failsafe circuit to prevent it from switching on input noise. Current
LVDS failsafe solutions require either external components with subsequent reductions in signal quality or
integrated solutions with limited application. This family of receivers has a new integrated failsafe that solves
the limitations seen in present solutions. A detailed theory of operation is presented in application note The
Active Fail-Safe in TI’s LVDS Receivers, literature number SLLA082B.
The following figure shows one receiver channel with active failsafe. It consists of a main receiver that can
respond to a high-speed input differential signal. Also connected to the input pair are two failsafe receivers that
form a window comparator. The window comparator has a much slower response than the main receiver and
it detects when the input differential falls below 80 mV. A 600-ns failsafe timer filters the window comparator
outputs. When failsafe is asserted, the failsafe logic drives the main receiver output to logic high.
Output
Buffer
Main Receiver
A
B
+
_
R
Reset
Failsafe
Timer
A > B + 80 mV
+
_
Failsafe
B > A + 80 mV
+
_
Window Comparator
Figure 16. Receiver With Active Failsafe
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15
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
ECL/PECL-to-LVTTL conversion with TI’s LVDS receiver
The various versions of emitter-coupled logic (i.e., ECL, PECL and LVPECL) are often the physical layer of
choice for system designers. Designers know that established technology is capable of high-speed data
transmission. In the past, system requirements often forced the selection of ECL. Now technologies like LVDS
provide designers with another alternative. While the total exchange of ECL for LVDS may not be a design
option, designers have been able to take advantage of LVDS by implementing a small resistor divider network
at the input of the LVDS receiver. TI has taken the next step by introducing a wide common-mode LVDS receiver
(no divider network required) which can be connected directly to an ECL driver with only the termination bias
voltage required for ECL termination (VCC – 2 V).
Figure 17 shows the use of an LV/PECL driver driving 5 meters of CAT–5 cable and being received by TI’s wide
common-mode receiver and the resulting eye-pattern. The values for R3 are required in order to provide a
resistor path to ground for the LV/PECL driver. With no resistor divider, R1 simply needs to match the
characteristic load impedance of 50 Ω. The R2 resistor is a small value intended to minimize common-mode
reflections.
VCC
ICC
R1 = 50 Ω
R2 = 50 Ω
5 Meters
of CAT-5
LV/PECL
R3
R3
VB
LVDS
VB
R1
VEE
VCC
ICC
R1
R2
R3 = 240 Ω
Figure 17. LVPECL or PECL to Remote Wide Common-Mode LVDS Receiver
16
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
APPLICATION INFORMATION
device power and grounding
The SN65LVDS352 device provides separate power and ground pins for the analog input section and the two
digital output sections. All of the power pins and all of the ground pins of the device must be tied together at some
point in the system. Figure 18 shows one recommended scheme for power and ground to the device. This point
will be determined by the power and grounding distribution design, which can greatly affect system
performance.
Key points to remember when routing power and grounds in your system are:
D
D
D
D
The grounding system must provide a low impedance path back to the power source.
The signal return must be close to the signal path.
Ground noise occurs due to ground loops and common-mode noise pick-up.
Closely spaced power and ground planes reduce inductance and increase capacitance.
A good rule to remember when doing your power distribution and board layout is that the current always flows
in the lowest impedance path. At dc the lowest resistance is the lowest impedance, but at high frequencies the
lowest impedance is the lowest inductance path.
VCC
VCCD1
Bypass
Capacitor†
DGND1
Bypass
Capacitor†
VCCA
AGND
VCCD2
Bypass
Capacitor†
DGND2
† Bypass capacitors used for data sheet electrical testing were low ESR ceramic, surface mount, 0.01 µF ±10%. For a more accurate
determination of these values refer to the application note, The Bypass Capacitor in High-Speed Environments, literature number
SCBA007A.
Figure 18. Recommended Power and Ground Connection
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17
SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
MECHANICAL DATA
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
8 PINS SHOWN
0.020 (0,51)
0.014 (0,35)
0.050 (1,27)
8
0.010 (0,25)
5
0.008 (0,20) NOM
0.244 (6,20)
0.228 (5,80)
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
4
0.010 (0,25)
0°– 8°
A
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
PINS **
0.004 (0,10)
8
14
16
A MAX
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
A MIN
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
DIM
4040047/E 09/01
NOTES: A.
B.
C.
D.
18
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
Falls within JEDEC MS-012
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SN65LVDS348, SN65LVDT348
SN65LVDS352, SN65LVDT352
SLLS523D – FEBRUARY 2002 – REVISED FEBRUATY 2003
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
www.ti.com
19
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