TI SN65HVD251

SN65HVD251
www.ti.com
SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
CAN TRANSCEIVER
FEATURES
•
•
•
•
•
•
•
•
•
•
•
(1)
Drop-In Improved Replacement for the
PCA82C250 and PCA82C251
Bus-Fault Protection of ±36 V
Meets or Exceeds ISO 11898
Signaling Rates(1) Up to 1 Mbps
High Input Impedance Allows up to 120
SN65HVD251 Nodes on a Bus
Bus Pin ESD Protection Exceeds 14 kV HBM
Unpowered Node Does Not Disturb the Bus
Low-Current Standby Mode — 200 µA Typical
Thermal Shutdown Protection
Glitch-Free Power-Up and Power-Down Bus
Protection For Hot-Plugging
DeviceNet Vendor ID # 806
The signaling rate of a line is the number of voltage transitions
that are made per second expressed in bps (bits per second).
APPLICATIONS
•
•
•
•
•
Designed for operation in harsh environments, the
device features cross-wire, over-voltage and loss of
ground protection to ±36 V. Also featured are
over-temperature protection as well as -7 V to 12 V
common-mode range, and tolerance to transients of
±200 V. The transceiver interfaces the single-ended
CAN controller with the differential CAN bus found in
industrial, building automation, and automotive applications.
Rs, pin 8, selects one of three different modes of
operation: high-speed, slope control, or low-power
mode. The high-speed mode of operation is selected
by connecting pin 8 to ground, allowing the transmitter output transistors to switch as fast as possible
with no limitation on the rise and fall slope. The rise
and fall slope can be adjusted by connecting a
resistor to ground at pin 8; the slope is proportional to
the pin's output current. Slope control with an external
resistor value of 10 kΩ gives ~ 15 V/us slew rate; 100
kΩ gives ~ 2 V/us slew rate.
If a high logic level is applied to the Rs pin 8, the
device enters a low-current standby mode where the
driver is switched off and the receiver remains active.
The local protocol controller returns the device to the
normal mode when it transmits to the bus.
CAN Data Buses
Industrial Automation
– DeviceNet™ Data Buses
– Smart Distributed Systems (SDS™)
SAE J1939 Standard Data Bus Interface
NMEA 2000 Standard Data Bus Interface
ISO 11783 Standard Data Bus Interface
The SN65HVD251 may be used in CAN,
DeviceNet™ or SDS™ applications with the Texas
Instruments' TMS320F241 and TMS320F243 DSPs
with CAN 2.0B controllers.
function diagram
(positive logic)
DESCRIPTION
The SN65HVD251 is intended for use in applications
employing the Controller Area Network (CAN) serial
communication physical layer in accordance with the
ISO 11898 Standard. The SN65HVD251 provides
differential transmit capability to the bus and differential receive capability to a CAN controller at speeds
up to 1 megabits per second (Mbps).
D
GND
1
8
Rs
2
7
Vcc
3
4
6
5
CANH
CANL
Vref
R
VCC
3
1
D
RS 8
R
4
5 V
ref
7
CANH
6 CANL
ORDERING INFORMATION
PART NUMBER
PACKAGE
MARKED AS
VP251
SN65HVD251D
8-pin SOIC (Tube)
SN65HVD251DR
8-pin SOIC (Tape & Reel)
VP251
SN65HVD251P
8-pin DIP
65HVD251
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DeviceNet is a trademark of Allen-Bradley.
SDS is a trademark of Honeywell.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2005, Texas Instruments Incorporated
SN65HVD251
www.ti.com
SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted (1) (2)
SN65HVD251
Supply voltage range, VCC
-0.3 V to 7 V
Voltage range at any bus terminal (CANH or CANL)
-36 V to 36 V
Transient voltage per ISO 7637, pulse 1, 2, 3a, 3b
CANH, CANL
±200 V
Input voltage range, VI (D, Rs, or R)
-0.3 V to VCC + 0.5
Receiver output current, IO
–10 mA to 10 mA
Human Body Model
Electrostatic discharge
(3)
Charged-Device Model
(4)
CANH, CANL and GND
14 kV
All pins
6 kV
All pins
1 kV
Continuous total power dissipation
(1)
(see Dissipation Rating
Table)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values, except differential I/O bus voltages, are with respect to network ground terminal.
Tested in accordance with JEDEC Standard 22, Test Method A114-A.
Tested in accordance with JEDEC Standard 22, Test Method C101.
(2)
(3)
(4)
ABSOLUTE MAXIMUM POWER DISSIPATION RATINGS
PACKAGE
SOIC (D)
PDIP (P)
(1)
(2)
(3)
DERATING FACTOR
ABOVE TA = 25°C
(1)
CIRCUIT BOARD
MODEL
TA = 25°C
POWER RATING
TA = 85°C POWER
RATING
TA = 125°C POWER
RATING
Low-K (2)
576 mW
4.8 mW/°C
288 mW
96 mW
High-K (3)
924 mW
7.7 mW/°C
462 mW
154 mW
Low-K (2)
888 mW
7.4 mW/°C
444 mW
148 mW
High-K (3)
1212 mW
10.1 mW/°C
606 mW
202 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow.
In accordance with the Low-K thermal metric definitions of EIA/JESD51-3.
In accordance with the High-K thermal metric definitions of EIA/JESD51-7.
THERMAL CHARACTERISTICS
PARAMETER
TEST CONDITIONS
VALUE
MIN
Θ JB
Junction-to-board thermal resistance
Θ JC
Junction-to-case thermal resistance
PD
Device power dissipation
TSD
Thermal shutdown junction temperature
2
TYP
D
78.7
P
48.9
D
44.6
P
66.6
UNITS
MAX
°C/W
°C/W
VCC = 5 V, Tj = 27 °C, RL = 60Ω,
RS at 0 V, Input to D a 500-kHz
50% duty cycle square wave
97.7
mW
VCC = 5.5 V, Tj = 130°C, RL = 60Ω,
RS at 0 V, Input to D a 500-kHz 50%
duty cycle square wave
142
mW
165
°C
SN65HVD251
www.ti.com
SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
RECOMMENDED OPERATING CONDITIONS
over recommended operating conditions (unless otherwise noted).
PARAMETER
MIN
Supply voltage, VCC
Voltage at any bus terminal (separately or common mode) VI or VIC
High-level input voltage, VIH
D input
Low-level input voltage, VIL
D input
NOM
V
-7 (1)
12
V
0.7 VCC
Input voltage to Rs, VI(Rs)
Input voltage at Rs for standby, VI(Rs)
V
-6
6
V
V
0
VCC
VCC
V
0
100
kΩ
Driver
-50
Receiver
mA
-4
Driver
50
Receiver
-40
Junction temperature, Tj
mA
4
Operating free-air temperature, TA
(1)
V
0.3 VCC
0.75 VCC
Rs wave-shaping resistance
Low-level output current, IOL
UNIT
5.5
Differential input voltage, VID
High-level output current, IOH
MAX
4.5
125
PDIP Package
145
SOIC Package
145
°C
°C
The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
DRIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP ( MAX UNIT
1)
VO(D)
Bus output voltage
(Dominant)
CANH
VO(R)
Bus output voltage
(Recessive)
CANH
VOD(D)
Differential output voltage (Dominant)
Figure 1 , D at 0 V, Rs at 0 V
VOD(D)
Differential output voltage (Dominant)
Figure 2 & Figure 3 , D at 0 V, Rs at 0 V
VOD(R)
Differential output voltage (Recessive)
Figure 1 & Figure 2 , D at 0.7 VCC
-120
VOD(R)
Differential output voltage (Recessive)
D at 0.7 VCC, no load
-0.5
VOC(pp)
Peak-to-peak common-mode output voltage
Figure 9, Rs at 0 V
IIH
High-level input current, D Input
D at 0.7 VCC
-40
0
µA
IIL
Low-level input current, D Input
D at 0.3 VCC
-60
0
µA
CANL
CANL
Figure 1 & Figure 2 ,
D at 0 V Rs at 0 V
Figure 1 & Figure 2 , D at 0.7VCC , Rs at 0 V
Figure 11, VCANH at -7 V, CANL Open
IOS(SS)
Short-circuit steady-state output current
2.75
Output capacitance
See receiver input capacitance
IOZ
High-impedance output current
See receiver input current
IIRs(s)
Rs input current for standby
Rs at 0.75 VCC
IIRs(f)
Rs input current for full speed operation
Rs at 0 V
ICC
Supply current
(1)
2
2.5
3
V
2
2.5
3
1.5
2
3
1.2
2
3.1
V
12
mV
0.05
600
V
V
mV
-200
2.5
-2
Figure 11, VCANL at 12 V, CANH Open
CO
4.5
2
Figure 11, VCANH at 12 V, CANL Open
Figure 11, VCANL at -7 V, CANH Open
3.5
0.5
mA
200
-10
-550
µA
0
µA
275
µA
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60Ω load, Rs at 0 V
65
Recessive
D at VCC, no load, Rs at 0 V
14
mA
All typical values are at 25°C and with a 5-V supply.
3
SN65HVD251
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
DRIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
tpLH
TEST CONDITIONS
Propagation delay time, low-to-high-level output
TYP
MAX
Figure 4, Rs at 0 V
MIN
40
70
Figure 4, Rs with 10 kΩ to ground
90
125
Figure 4, Rs with 100 kΩ to ground
500
800
85
125
Figure 4, Rs with 10 kΩ to ground
200
260
Figure 4, Rs with 100 kΩ to ground
1150
1450
Figure 4, Rs at 0 V
tpHL
Propagation delay time, high-to-low-level output
Figure 4, Rs at 0 V
tsk(p)
Pulse skew (|tpHL - tpLH|)
Figure 4, Rs with 10 kΩ to ground
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
tr
Differential output signal rise time
tf
Differential output signal fall time
ten
Enable time from standby to dominant
Figure 4, Rs with 100 kΩ to ground
Figure 4, Rs at 0 V
Figure 4, Rs with 10 kΩ to ground
Figure 4, Rs with 100 kΩ to ground
45
85
110
180
650
900
35
100
35
100
100
250
100
250
600
1550
600
1550
Figure 8
UNIT
ns
0.5
µs
RECEIVER ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VIT+
Positive-going input threshold voltage
VIT-
Negative-going input threshold voltage
Vhys
Hysteresis voltage (VIT+ - VIT-)
VOH
High-level output voltage
Figure 6, IO = -4mA
VOL
Low-level output voltage
Figure 6, IO = 4mA
MIN
TYP MAX UNIT
750
Rs at 0 V, (See Table 1)
500
650
mV
100
0.8
Vcc
V
0.2
Vcc
CANH or CANL at 12 V
II
900
CANH or CANL at 12 V,
VCC at 0 V
Bus input current
CANH or CANL at -7 V
CANH or CANL at -7 V,
VCC at 0 V
V
600
Other bus
pin at 0 V,
Rs at 0 V,
D at 0.7
VCC
715
µA
-460
-340
CI
Input capacitance, (CANH or CANL)
Pin-to-ground, VI = 0.4 sin (4E6πt) +
0.5 V, D at 0.7 VCC
20
CID
Differential input capacitance
Pin-to-pin, VI = 0.4 sin (4E6πt) + 0.5
V, D at 0.7 VCC
10
RID
Differential input resistance
D at 0.7 VCC, Rs at 0 V
40
100
kΩ
RIN
Input resistance, (CANH or CANL)
D at 0.7 VCC, Rs at 0 V
20
50
kΩ
275
µA
ICC
Supply current
4
pF
pF
Standby
Rs at VCC, D at VCC
Dominant
D at 0 V, 60Ω Load, Rs at 0 V
65
Recessive
D at VCC, No Load, Rs at 0 V
14
mA
SN65HVD251
www.ti.com
SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
RECEIVER SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
TYP
MAX
tpLH
Propagation delay time, low-to-high-level output
PARAMETER
TEST CONDITIONS
MIN
35
50
tpHL
Propagation delay time, high-to-low-level output
35
50
tsk(p)
Pulse skew (|tpHL - tpLH|)
tr
Output signal rise time
2
4
tf
Output signal fall time
2
4
tp(sb)
Propagation delay time in standby
Figure 6
20
Figure 12, Rs at VCC
UNIT
ns
500
VREF-PIN CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
VO
TEST CONDITIONS
-5 µA < IO < 5 µA
Reference output voltage
MIN
TYP
MAX
0.45 VCC
0.55 VCC
0.4 VCC
0.6 VCC
-50 µA < IO < 50 µA
UNIT
V
DEVICE SWITCHING CHARACTERISTICS
over recommended operating conditions (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
Figure 10, Rs at 0 V
tloop1
tloop2
tloop2
Total loop delay, driver input to receiver
output, recessive to dominant
Total loop delay, driver input to receiver
output, dominant to recessive
Total loop delay, driver input to receiver
output, dominant to recessive
MAX
60
100
Figure 10, Rs with 10 kΩ to ground
100
150
Figure 10, Rs with 100 kΩ to ground
440
800
Figure 10, Rs at 0 V
115
150
Figure 10, Rs with 10 kΩ to ground
235
290
Figure 10, Rs with 100 kΩ to ground
1070
1450
105
145
Figure 10, Rs at 0 V, VCC from 4.5 V to 5.1
V,
UNIT
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
IO(CANH)
VO(CANH)
D
VOD
II
IIRs
Rs
VI
60 1%
+
VI(Rs)
_
VO(CANH) + VO(CANL)
2
VOC
IO(CANL)
VO(CANL)
Figure 1. Driver Voltage, Current, and Test Definition
5
SN65HVD251
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Dominant
VO(CANH)
3.5 V
Recessive
2.5 V
VO(CANL)
1.5 V
Figure 2. Bus Logic State Voltage Definitions
330 1%
CANH
VI
D
60 1%
VOD
+
_
RS
CANL
–7 V VTEST 12 V
330 1%
Figure 3. Driver VOD
CANH
D
VI
Rs
(see Note A)
RL =
60 1%
+
VI(Rs)
_
CL =
50 pF 20%
(see Note B)
VO
CANH
VCC
VCC/2
VI
VCC/2
0V
tPHL
tPLH
0.9V
VO
90%
10%
tr
VO(D)
0.5V
VO(R)
tf
Figure 4. Driver Test Circuit and Voltage Waveforms
CANH
VI(CANH)
VI(CANH) + VI(CANL)
VIC =
2
VI(CANL)
R
IO
VID
CANL
VO
Figure 5. Receiver Voltage and Current Definitions
6
SN65HVD251
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
PARAMETER MEASUREMENT INFORMATION (continued)
CANH
R
VI
CANL
(see Note A)
1.5 V
IO
CL = 15 pF
20% (see Note B)
VO
3.5 V
VI
2.4 V
2V
1.5 V
tPLH
VO
tPHL
0.7 VCC
10%
90%
tr
VOH
0.3 VCC
10%
VOL
tf
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 6. Receiver Test Circuit and Voltage Waveforms
CANH
R
CANL
100 Pulse Generator
15 s Duration
1% Duty Cycle
tr, tr 100 ns
D at 0 V
or VCC
RS at 0 V or VCC
A.
This test is conducted to test survivability only. Data stability at the R output is not specified.
Figure 7. Test Circuit, Transient Over-Voltage Test
Table 1. Receiver Characteristics Over Common Mode Voltage
INPUT
MEASURED
OUTPUT
VCANH
VCANL
|VID|
12 V
11.1 V
900 mV
L
R
-6.1 V
-7 V
900 mV
L
-1 V
-7 V
6V
L
12 V
6V
6V
L
-6.5 V
-7 V
500 mV
H
12 V
11.5 V
500 mV
H
-7 V
-1 V
6V
H
6V
12 V
6V
H
open
open
X
H
VOL
VOH
7
SN65HVD251
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
DUT
CANH
0V
VI
D
60 1%
Rs
CANL
R
+
VO
_
15 pF 20%
VCC
0.7 VCC
VI
0V
VOH
0.3 VCC
VO
0.3 VCC
VOL
ten
Figure 8. ten Test Circuit and Voltage Waveforms
CANH
27 1%
D
VI
CANL
27 1%
RS
VOC
50 pF 20%
VOC(PP)
VOC
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
Figure 9. Peak-to-Peak Common Mode Output Voltage
8
SN65HVD251
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
DUT
CANH
VI
D
60 1%
10 k or 100 k 5%
_
RS
CANL
VRs +
R
+
VO
_
15 pF 20%
VCC
50%
D Input
0V
tLoop2
tLoop1
VOH
0.7 Vcc
R Output
0.3 Vcc
VOL
Figure 10. tLOOP Test Circuit and Voltage Waveforms
IOS
0 V or VCC
CANH
D
Rs
CANL
Vin –7 V or 12 V
IOS(SS)
IOS(P)
15 s
0V
12 V
Vin
0V
or
0V
10 s
Vin
–7 V
Figure 11. Driver Short-Circuit Test
9
SN65HVD251
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
CANH
R
VI
CANL
(see Note A)
CL = 15 pF
1.5 V
VO
(see Note B)
3.5 V
2.4 V
VI
1.5 V
tp(sb)
VOH
VO
0.3 VCC
VOL
A.
The input pulse is supplied by a generator having the following characteristics: PRR ≤ 125 kHz, 50% duty cycle, tr≤
6ns, tf≤ 6ns, ZO = 50Ω.
B.
CL includes instrumentation and fixture capacitance within ±20%.
Figure 12. Receiver Propagation Delay in Standby Test Circuit and Waveform
DEVICE INFORMATION
5V
R21%
R11%
CANH
+
R
VID
–
CANL
Vac
R11%
VI
R21%
VID
R1
R2
500 mV
50 450 900 mV
50 227 12 V
VI
–7 V
A.
All input pulses are supplied by a generator having the following characteristics: f < 1.5 MHz, TA = 25oC, VCC = 5.0 V.
Figure 13. Common-Mode Input Voltage Rejection Test
10
SN65HVD251
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
DEVICE INFORMATION (continued)
FUNCTION TABLES
Table 2. DRIVER
INPUTS
D
Voltage at Rs, VRs
OUTPUTS
CANH
BUS STATE
CANL
L
VRs < 1.2 V
H
L
Dominant
H
VRs < 1.2 V
Z
Z
Recessive
Open
X
Z
Z
Recessive
X
VRs > 0.75 VCC
Z
Z
Recessive
Table 3. RECEIVER
(1)
DIFFERENTIAL INPUTS [VID = V(CANH) - V(CANL)]
OUTPUT R (1)
VID≥ 0.9 V
L
0.5V < VID < 0.9 V
?
VID ≤ 0.5 V
H
Open
H
H = high level; L = low level; X = irrelevant; ? = indeterminate; Z = high impedance
11
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
R Output
D Input
Vcc
Vcc
100 k
1 k
15 Input
Output
9V
9V
CANH Input
CANL Input
Vcc
110 k
Vcc
110 k
9 k
45 k
9 k
45 k
Input
Input
40 V
9 k
40 V
CANH and CANL Outputs
9 k
Rs Input
Vcc
Vcc
Output
40 V
+
Input
Figure 14. Equivalent Input and Output Schematic Diagrams
12
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SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
TYPICAL CHARACTERISTICS
tLOOP1-LOOP TIME
vs
FREE-AIR TEMPERATURE
tLOOP2-LOOP TIME
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT (RMS)
vs
SIGNALING RATE
150
33
72
tLOOP2 – Loop Time – ns
VCC = 4.5 V
VCC = 5 V
70
68
66
VCC = 5.5 V
VCC = 5.5 V
VCC = 5 V
140
135
130
VCC = 4.5 V
64
125
62
–40 –25 –10 5
120
–40 –25 –10 5
20 35 50 65 80 95 110 125
VCC = 5 V,
TA = 25°C,
RS = 0 V,
RL = 60 Ω,
CL = 50 pF
32
31
30
29
28
27
26
25
0
35 50 65 80 95 110 125
250 500 750 1000 1250 1500 1750 2000
TA – Free-Air Temperature – C
Signaling Rate – kbps
Figure 15.
Figure 16.
Figure 17.
DRIVER LOW-LEVEL OUTPUT CURRENT
vs
LOW-LEVEL OUTPUT VOLTAGE
DRIVER HIGH-LEVEL OUTPUT CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
DOMINANT DIFFERENTIAL
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
140
IOH – Driver High-Level Output Current – mA
IOL – Driver Low-Level Output Current – mA
TA – Free-Air Temperature – C
20
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
120
100
80
60
40
20
0
0
1
2
3
4
5
80
VOD(D) – Dominant Differential Output Voltage – V
tLOOP1 – Loop Time – ns
145
ICC – RMS Supply Current – mA
RS = 0 V
RS = 0 V
74
VCC = 5 V,
TA = 25°C,
RS = 0 V,
D at 0V
70
60
50
40
30
20
10
0
0
1
2
3
4
5
VOCANH – High-Level Output Voltage – V
VOCANL – Low-Level Output Voltage – V
3
VCC = 5.5 V
2.5
2
VCC = 4.5 V
VCC = 5 V
1.5
1
RS = 0 V,
D at 0V,
RL = 60 Ω
0.5
0
–55
–40
0
25
70
85
125
TA – Free-Air Temperature – C
Figure 18.
Figure 19.
Figure 20.
DRIVER OUTPUT CURRENT
vs
SUPPLY VOLTAGE
DIFFERENTIAL OUTPUT
FALL TIME
vs
SLOPE RESISTANCE (Rs)
INPUT RESISTANCE MATCHING
vs
FREE-AIR TEMPERATURE
50
40
30
20
10
0
TA = 25°C
900
800
VCC = 5.5 V
VCC = 5 V
700
600
VCC = 4.5 V
500
400
300
200
2
3
4
VCC – Supply Voltage – V
Figure 21.
5
6
−0.50
VCC = 5.5 V
−1
−1.50
VCC = 5 V
−2
VCC = 4.5 V
−2.50
100
−3
0
1
Input Resistance Matching − %
TA = 25°C,
RS = 0 V,
D at 0V,
RL = 60 Ω
tf - Differential Output Fall Time - ns
IO – Driver Output Current – mA
0
1000
60
0
10 20 30 40 50 60 70 80 90 100
RS - Slope Resistance - k
Figure 22.
−50
0
50
100
150
TA − Free-Air Temperature − °C
Figure 23.
13
SN65HVD251
www.ti.com
SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
APPLICATION INFORMATION
The basics of bus arbitration require that the receiver
at the sending node designate the first bit as dominant or recessive after the initial wave of the first bit
of a message travels to the most remote node on a
network and back again. Typically, this sample is
made at 75% of the bit width, and within this
limitation, the maximum allowable signal distortion in
a CAN network is determined by network electrical
parameters.
Factors to be considered in network design include
the 5 ns/m propagation delay of typical twisted-pair
bus cable; signal amplitude loss due to the loss
mechanisms of the cable; and the number, length,
and spacing of drop-lines (stubs) on a network. Under
strict analysis, variations among the different oscil-
lators in a system must also be accounted for with
adjustments in signaling rate and stub & bus length.
Table 4 lists the maximum signaling rates achieved
with the SN65HVD251 in high-speed mode with
several bus lengths of category-5, shielded
twisted-pair (CAT 5 STP) cable.
Table 4. Maximum Signaling Rates for Various
Cable Lengths
BUS LENGTH (m)
SIGNALING RATE (kbps)
30
1000
100
500
250
250
500
125
1000
62.5
The ISO 11898 standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m with a
maximum of 30 nodes. However, with careful design, users can have longer cables, longer stub lengths, and
many more nodes on a bus. (Note: Non-standard application may come with a trade-off in signaling rate.) A bus
with a large number of nodes requires a transceiver with high input impedance such as the HVD251.
The Standard specifies the interconnect to be a single twisted-pair cable (shielded or unshielded) with 120-Ω
characteristic impedance (Zo). Resistors equal to the characteristic impedance of the line terminate both ends of
the cable to prevent signal reflections. Unterminated drop-lines connect nodes to the bus and should be kept as
short as possible to minimize signal reflections.
Connectors, while not specified by the ISO 11898 standard, should have as little effect as possible on standard
operating parameters such as capacitive loading. Although unshielded cable is used in many applications, data
transmission circuits employing CAN transceivers are usually used in applications requiring a rugged
interconnection with a wide common-mode voltage range. Therefore, shielded cable is recommended in these
electronically harsh environments, and when coupled with the –2-V to 7-V common-mode range of tolerable
ground noise specified in the standard, helps to ensure data integrity. The HVD251 extends data integrity beyond
that of the standard with an extended –7-V to 12-V range of common-mode operation.
NOISE MARGIN
900 mV Threshold
RECEIVER DETECTION WINDOW
75% SAMPLE POINT
500 mV Threshold
NOISE MARGIN
ALLOWABLE JITTER
Figure 24. Typical CAN Differential Signal Eye-Pattern
14
SN65HVD251
www.ti.com
SLLS545C – NOVEMBER 2002 – REVISED SEPTEMBER 2005
An eye pattern is a useful tool for measuring overall signal quality. As displayed in Figure 24, the differential
signal changes logic states in two places on the display, producing an eye. Instead of viewing only one logic
crossing on the scope, an entire bit of data is brought into view. The resulting eye pattern includes all effects of
systemic and random distortion, and displays the time during which a signal may be considered valid.
The height of the eye above or below the receiver threshold voltage level at the sampling point is the noise
margin of the system. Jitter is typically measured at the differential voltage zero-crossing during the logic state
transition of a signal. Note that jitter present at the receiver threshold voltage level is considered by some to be a
more effective representation of the jitter at the input of a receiver.
As the sum of skew and noise increases, the eye closes and data is corrupted. Closing the width decreases the
time available for accurate sampling, and lowering the height enters the 900 mV or 500 mV threshold of a
receiver.
Different sources induce noise onto a signal. The more obvious noise sources are the components of a
transmission circuit themselves; the signal transmitter, traces & cables, connectors, and the receiver. Beyond
that, there is a termination dependency, cross-talk from clock traces and other proximity effects, VCC & ground
bounce, and electromagnetic interference from near-by electrical equipment.
The balanced receiver inputs of the HVD251 mitigate most sources of signal corruption, and when used with a
quality shielded twisted-pair cable, help ensure data integrity.
Typical Application
Bus Lines – 40 m max
CANH
120 120 Stub Lines –– 0.3 m max
CANL
Vref
RS
VCC
5V
SN65HVD251
0.1 F
Vref
RS
VCC
CANTX
R
CANRX
0.1 F
SN65HVD251
GND
D
5V
Vref
RS
VCC
CANTX
R
CANRX
0.1 F
SN65HVD230
GND
D
3.3 V
GND
D
CANTX
R
CANRX
TMS320F243
TMS320F243
TMS320LF2407A
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Sensor, Actuator, or
Control Equipment
Figure 25. Typical HVD251 Application
15
PACKAGE OPTION ADDENDUM
www.ti.com
3-Sep-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
SN65HVD251D
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD251DG4
ACTIVE
SOIC
D
8
75
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD251DR
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD251DRG4
ACTIVE
SOIC
D
8
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN65HVD251P
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN65HVD251PE4
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN65HVD251DR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
6.4
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN65HVD251DR
SOIC
D
8
2500
340.5
338.1
20.6
Pack Materials-Page 2
MECHANICAL DATA
MPDI001A – JANUARY 1995 – REVISED JUNE 1999
P (R-PDIP-T8)
PLASTIC DUAL-IN-LINE
0.400 (10,60)
0.355 (9,02)
8
5
0.260 (6,60)
0.240 (6,10)
1
4
0.070 (1,78) MAX
0.325 (8,26)
0.300 (7,62)
0.020 (0,51) MIN
0.015 (0,38)
Gage Plane
0.200 (5,08) MAX
Seating Plane
0.010 (0,25) NOM
0.125 (3,18) MIN
0.100 (2,54)
0.021 (0,53)
0.015 (0,38)
0.430 (10,92)
MAX
0.010 (0,25) M
4040082/D 05/98
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-001
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
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