SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999 D D D D D EPIC (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD-22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) SN54LV367A . . . J OR W PACKAGE SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 1OE 1A1 1Y1 1A2 1Y2 1A3 1Y3 GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC 2OE 2A2 2Y2 2A1 2Y1 1A4 1Y4 SN54LV367A . . . FK PACKAGE (TOP VIEW) 1A1 1OE NC VCC 2OE D 1Y1 1A2 NC 1Y2 1A3 description 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2A2 2Y2 NC 2A1 2Y1 1Y3 GND NC 1Y4 1A4 The ’LV367A devices are hex buffers and line drivers designed for 2-V to 5.5-V VCC operation. These devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. 4 NC – No internal connection The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. The SN54LV367A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV367A is characterized for operation from –40°C to 85°C. FUNCTION TABLE (each buffer/driver) INPUTS OE A OUTPUT Y L H H L L L H X Z Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1999, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999 logic symbol† 1 EN 1OE 1A1 1A2 1A3 1A4 2 3 4 5 6 7 10 9 15 2A2 1Y2 1Y3 1Y4 EN 2OE 2A1 1Y1 12 11 14 13 2Y1 2Y2 † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. logic diagram (positive logic) 1OE 1A1 1 2 2OE 3 1Y1 2A1 15 12 To Three Other Channels To One Other Channel Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. 2 POST OFFICE BOX 655303 11 • DALLAS, TEXAS 75265 2Y1 SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range applied in the high or low state, VO (see Notes 1 and 2) . . . . . . –0.5 V to VCC + 0.5 V Output voltage range applied in high-impedance or power-off state, VO (see Note 1) . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999 recommended operating conditions (see Note 4) SN54LV367A VCC VIH Supply voltage High level input voltage High-level VIL Low level input voltage Low-level VI Input voltage VO IOH IOL ∆t/∆v Output voltage High level output current High-level Low level output current Low-level Input transition rise or fall rate VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V SN74LV367A MIN MAX 2 5.5 1.5 MIN MAX 2 5.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 0.5 0 High or low state 0 3-state 0 VCC × 0.3 5.5 VCC 5.5 V 0.5 VCC × 0.3 VCC × 0.3 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V VCC × 0.3 VCC × 0.3 0 0 0 VCC × 0.3 5.5 V V µA –50 –50 –2 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V –8 –8 –16 –16 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 8 8 16 V VCC 5.5 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V V 1.5 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V UNIT mA µA mA 16 0 200 0 200 0 100 0 100 ns/V VCC = 4.5 V to 5.5 V 0 20 0 20 TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL VCC IOH = –50 µA IOH = –2 mA 2 V to 5.5 V IOH = –8 mA IOH = –16 mA IOL = 50 µA IOL = 2 mA ICC Ioff VI = VCC or GND, VI or VO = 0 to 5.5 V Ci VI = VCC or GND VI = VCC or GND TYP SN74LV367A MAX MIN TYP VCC–0.1 2 3V 2.48 2.48 4.5 V 3.8 MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 5.5 V ±1 ±1 µA IOL = 8 mA IOL = 16 mA VI = VCC or GND VO = VCC or GND MIN VCC–0.1 2 2.3 V II IOZ Co SN54LV367A TEST CONDITIONS IO = 0 V 5.5 V ±5 ±5 µA 5.5 V 20 20 µA 5 µA 0V 5 3.3 V 3 3 pF 3.3 V 5.2 5.2 pF switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN TYP MAX SN54LV367A SN74LV367A MIN MAX MIN MAX tpd* ten* A Y 6.4 12.7 1 16 1 16 OE Y 6.9 14.9 1 20 1 20 tdis* OE Y 6.4 14.9 1 20 1 20 tpd ten A Y 8.6 17.5 1 21 1 21 OE Y 9.4 19.7 1 25 1 25 tdis OE Y 10.1 19.7 1 25 1 25 CL = 15 pF CL = 50 pF tsk(o) CL = 50 pF 2 2 UNIT ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN TYP MAX SN54LV367A MIN SN74LV367A MAX MIN MAX tpd* ten* A Y 4.7 8.3 1 10 1 10 OE Y 5.1 10.5 1 12.5 1 12.5 tdis* OE Y 4.9 10.5 1 12.5 1 12.5 tpd ten A Y 6.2 11.8 1 13.5 1 13.5 OE Y 6.8 14 1 16 1 16 tdis OE Y 7.3 13.6 1 15.5 1 15.5 tsk(o) CL = 15 pF CL = 50 pF CL = 50 pF 1.5 1.5 UNIT ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd* ten* A Y OE Y tdis* OE tpd A ten OE Y tdis OE Y LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN54LV367A MIN SN74LV367A MAX MIN MAX 3.6 5.9 1 7 1 7 3.8 7.2 1 8.5 1 8.5 Y 2.6 7.2 1 8.5 0 8.5 Y 4.5 7.9 1 9 1 9 4.9 9.2 1 10.5 1 10.5 4.5 9.2 1 10.5 0 10.5 CL = 15 pF CL = 50 pF tsk(o) CL = 50 pF 1 1 UNIT ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV367A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.5 0.8 V Quiet output, minimum dynamic VOL –0.2 –0.8 V VOH(V) VIH(D) Quiet output, minimum dynamic VOH 3 High-level dynamic input voltage V 2.31 V VIL(D) Low-level dynamic input voltage NOTE 5: Characteristics are for surface-mount packages only. 0.99 V VCC 3.3 V TYP UNIT 5V 17.4 operating characteristics, TA = 25°C PARAMETER Cpd d Power dissipation capacitance TEST CONDITIONS pF CL = 50 pF, PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 14.9 pF SN54LV367A, SN74LV367A HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 Open VCC GND VCC tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL VOH 50% VCC VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS 50% VCC 0V tPLZ ≈VCC Output Waveform 1 S1 at VCC (see Note B) 50% VCC tPZH tPLH 50% VCC 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control Output Waveform 2 S1 at GND (see Note B) VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. 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