SP5730 1.3GHz Low Phase Noise Frequency Synthesiser Preliminary Information DS4877 issue 1.9 July 1999 Features ● Complete 1.3GHz single chip system for ● ● ● ● ● ● ● ● Digital Terrestrial Television applications Selectable reference division ratio, compatible with (DTT) requirements Optimised for low phase noise, with comparison frequencies up to 4MHz No RF prescaler Selectable reference/comparison frequency output Four selectable I2C bus address I2C fast mode compliant and compatible with 3.3 and 5V logic levels Four switching ports ESD protection, (Normal ESD Handling procedures should be observed) Applications ● Digital Satellite ,Cable and Terrestrial tuning systems ● Communications systems Ordering Information SP5730A/KG/MP1S Sticks SP5730A/KG/MP1T Tape and Reel SP5730A/KG/QP1S Sticks SP5730A/KG/QP1T Tape amd Reel Description The SP5730 is a single chip frequency synthesiser designed for tuning systems up to 1.3GHz and is optimised for digital terrestrial applications. The RF preamplifier interfaces direct with the RF programmable divider, which is of MN+A construction so giving a step size equal to the loop comparison frequency and no prescaler phase noise degradation over the RF operating range. The comparison frequency is obtained either from an on-chip crystal controlled oscillator, or from an external source. The oscillator frequency, Fref, or phase comparator frequency, Fcomp, can be switched to the REF/COMP output providing a reference frequency for a second frequency synthesiser. The synthesiser is controlled via an I2C bus and is fast mode compliant. It can be hard wired to respond to one of four addresses to enable two or more synthesisers to be used on a common bus. The device contains four switching ports P0-P3. SP5730 Preliminary Information RF/COMP enable/select 12 BIT COUNT RF INPUT CRYSTAL Osc REF DIVIDER CRYSTAL CAP 8/9 3 BIT COUNT CHARGE PUMP Lock fpd/2 DRIVE PUMP disable c/p mode 15 BIT LATCH 2 BIT ADDRESS SDA 5 BIT 2 BIT fpd/2 select 4 BIT LATCH & PORT INTERFACE I 2 C BUS TRANSCEIVER 2 BIT SCL PORT P3 PORT P2 PORT P1PORT P0 Figure 1 Block diagram CRYSTALIOUT CAP CRYSTAL VEEA SDA IFINB SCL IFIN PORT P3/LOGLEV IVCCA PORT P2 QOUT PORT P1 VEEC 1 16 SL1711B CHARGE PUMP AGC DRIVE VCCB VEE VCODIS RF INPUT VCO B RF INPUT VCO A VCC VEEB REF/COMP PSCAL ADDRESS PSCALB PORT P0 VCCC MP16 Figure 2 Pin connections top view 2 MP16 & QP16 Preliminary Information SP5730 Electrical Characteristics o o Tamb= -40 C to 85 C, VCC= 4.5 to 5.5V These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Min Value Typ Supply current Units Max 20 mA Conditions RF input voltage 13,14 12.5 300 mVrms 100 MHz – 1.3GHz, see Figure. 4 RF input voltage 13,14 40 300 mVrms 50MHz - 100MHz, see Figure 4 RF input impedance 13,14 SDA, SCL See Figure. 5 4, 5 2 Input high voltage 3 5.5 V 5V I C logic selected Input low voltage 0 1.5 V 5V I C logic selected Input high voltage 2.3 3.5 V 3V3 I C logic selected Input low voltage 0 1 V 3V3 I C logic selected Input high current 10 µA Input voltage =Vcc Input low current 10 µA Input voltage = Vee Leakage current 10 µA Vee = Vcc Isink = 3mA Isink = 6mA Hysteresis SDA output voltage 4 0.4 0.4 0.6 V V V SCL clock rate 5 400 kH Charge pump output current 1 Charge pump output leakage 1 Charge pump drive output current 16 0.5 Crystal frequency Recommended crystal series resistance 2,3 2 10 External reference input Frequency 3 External reference drive level 3 2 2 2 See Table 6 Vpin1 = 2V 3 10 nA Vpin1 = 2V, Vcc = 5V, +25°C mA Vpin16 = 0.7V 20 200 MHz Ω See Figure 3 for application 4 MHz “parallel resonant” crystal. 2 20 MHz Sinewave coupled through 10 nF blocking capacitor 0.2 0.5 Vpp Sinewave coupled through 10 nF blocking capacitor 3 SP5730 Preliminary Information Electrical Characteristics (continued) o o Tamb= -40 C to 85 C, Vcc= 4.5 to 5.5V These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Pin Min Buffered REF/COMP output output amplitude output impedance Value Typ Units 11 0.35 250 Phase detector Comparison frequency Vpp Ω 4 Equivalent phase noise at phase detector RF division ratio SSB, within loop bandwidth Fcomp = 2MHz Fcomp = 125kHz 32767 Reference division ratio See Table 1 Output ports P0 - P3 sink current Leakage current 6-9 Address Select Input high current Input low current 10 Logic level select Input high level 6 Input low level Input current AC coupled 0.5-20MHz Enabled by bit RE= 1 See note 2 MHz dBc/Hz -152 -158 56 Conditions Max 10 mA µA See Note 1 Vport = 0.7 Vport = Vcc 1 -0.5 mA mA See Figure 4 Table 3 Vin = Vcc Vin = Vee 2 3 Vcc V 0 -10 1.5 10 V µA See note 3 5V I2C logic selected, or open circuit 3V3 I2C logic selected Vin = Vee to Vcc Notes: 1. Output ports high impedance on power up, with data, clock, and enable at logic ‘0’ 2. If the REF/COMP output is not used, the output should be left open circuit or connected to Vcc, and disabled by setting RE = 0 3. Bi-directional port. When used as an output, the input logic state is ignored. When used as an input the port should be switched in to high impedance (off) state. 4 Preliminary Information SP5730 Absolute Maximum Ratings All voltages are referred to Vee at 0V Characteristic Min Supply voltage, Vcc -0.3 RF input voltage All I/O port DC offsets -0.3 SDA and SCL DC offset -0.3 Storage temperature -55 Junction temperature QP16 thermal resistance, chip to ambient chip to case Power consumption at Vcc = 5.5V ESD protection 2 Max 7 2.5 Vcc+0.3 6V +150 150 Units V Vpp V oV oC C 80 20 83 °C/W °C/W mW kV Conditions Transient Differential All ports off mil std 883 latest revision method 3015 class 1 Functional Description The SP5730 contains all the elements necessary, with the exception of a frequency reference, loop filter and external high voltage transistor, to control a varicap tuned local oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. It can also be operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT) receivers The block diagram is shown in Figure 2. The RF input signal is fed to an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider, which is of MN+A architecture, where the dual modulus prescaler is 8/9, the A counter is 3-bits, and the M counter is 12 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1. The output of the phase detector feeds a charge pump and loop amplifier section, which when used with an external high voltage transistor and loop filter, integrates the current pulses into the varactor line voltage. The programmable divider output Fpd divided by two can be switched to port P0 by programming the device into test mode. The test modes are described in Table 4. Programming The SP5730 is controlled by an I2C data bus and is compatible with both standard and fast mode formats and with I2C data generated from nominal 3.3V and 5V sources. The I2C logic level is selected by the bi-directional port P3/LOGLEV. 5V logic levels are selected by connecting P3/LOGLEV to Vcc or leaving open circuit and 3.3V by connecting to ground. If this port is used as an input the P3 data should be programmed to high impedance. If used as an output 5V logic only levels can be used and in this case the logic state imposed by the port on the input is ignored. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesiser can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Table 2 illustrates the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one synthesiser in an I2C bus system. Table 3 shows how the address is selected by applying a voltage to the ‘address’ input. 5 SP5730 When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. Preliminary Information Programmable features RF programmable divider Function as described above Write mode Reference programmable divider Function as described above. With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 and byte 5 control the reference divider ratio, see Table 1, charge pump setting, see Table 6, REF/COMP output, seeTable 7, output ports and test modes, see Table 4. Charge pump current The charge pump current can be pro grammed by bits C1-C0 within data byte 5, as defined in Table 6. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic ‘0’ indicating byte 2, and a logic ‘1’ indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without readdressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. Test mode Read mode When the device is in read mode, the status byte read from the device takes the form shown in Table 2. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic ‘1’ if the Vcc supply to the device has dropped below 3V (at 25°C), e.g. when the device is initially turned ON. The POR is reset to ‘0’ when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to power up condition. Bit 2 (FL) indicates whether the device is phase locked, a logic ‘1’ is present if the device is locked, and a logic ‘0’ if the device is unlocked. 6 The test modes are invoked by bits REB. RS, T1 and T0 as described in Table 4. Reference/Comparison frequency output The reference frequency Fref or comparison frequency Fcomp can be switched to the REF/COMP output, function as defined in Table 7. RE and RS default to logic ‘I’ during device power up, thus enabling the comparison frequency Fcomp at the REF/COMP output. Preliminary Information R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SP5730 R3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Ratio 2 4 8 16 32 64 128 256 Illegal state 5 10 20 40 80 160 320 Illegal state 6 12 24 48 96 192 384 Illegal State 7 14 28 56 112 224 448 X = don’t care Table 1 Reference division ratio MSB Address 1 Programmable divider Programmable divider 0 27 Control Data Control Data LSB 1 214 0 213 0 212 0 211 MA1 210 MA0 29 0 28 A Byte 1 A Byte 2 26 25 24 23 22 21 20 A Byte 3 1 T1 T0 R4 R3 R2 R1 R0 A Byte 4 C1 C0 RE RS P3 P2 P1 P0 A Byte 5 Table 2 Write data format (MSB is transmitted first) 7 SP5730 Preliminary Information MSB 1 POR Address Status byte 1 FL 0 0 0 0 0 0 MA1 0 MA0 0 LSB 1 0 A A Byte 1 Byte 2 Table 2 Read data format (MSB is transmitted first) A MA1,MA0 14 0 2 -2 R4-R0 C1, C0 RE RS T1-T0 P3-P0 POR FL : : : : : : : : : : : Acknowledge bit Variable address bits (see Table 3) Programmable division ratio control bits Reference division ratio select (see Figure 3) Charge pump current select (see Figure 6) REF/COMP output enable REF/COMP output select when RE=1 (see Figure 2) Test mode control bits P3 - P0 port output states Power on reset indicator Phase lock flag MA1 0 0 1 1 MA0 0 1 0 1 Address input voltage level 0 - 0.1Vcc Open circuit 0.4Vcc - 0.6Vcc # 0.9Vcc - Vcc # Programmed by connecting a 30kΩ ± 5% resistor between pin 10 and Vcc Table 3 Address selection RE.RS 0 1 X X X T1 0 0 0 1 1 T0 0 0 1 0 1 Test mode description Normal operation Normal operation Port P0 = Fpd/2 Charge pump sink.* Status byte FL set to logic ‘0’ Charge pump source * Status byte FL set to logic ‘0’ Charge pump disabled * Status byte FL set to logic ‘1’ *clocks need to be present on crystal and RF inputs to enable charge pump test modes and to toggle Status byte bit FL X = Dont Care Table 4 Test modes 8 Preliminary Information C1 byte 5, bit 1 SP5730 Current in µA C0 byte 5, bit 2 0 0 1 1 Min +- 116 +- 247 +- 517 +- 1087 0 1 0 1 Typ +- 155 +- 330 +- 690 +- 1450 Max +- 194 +- 412 +- 862 +- 1812 Table 6 Charge pump current 2 68pF 150pF SP5730 3 Figure 3 XTAL oscillator application RE 0 0 1 1 X = don’t care RS 0 1 0 1 REF/COMP OUTPUT High impedance High impedance Test mode enabled, see Figure 5 Fref selected Fcomp selected Table 7; REF/COMP output 9 SP5730 Preliminary Information 300 37.5 25 12.5 50 100 500 1000 1300 1500 Frequency (MHz) Figure 4 Typical RF input sensitivity +j1 +j0.5 +j2 +j0.2 0 +j5 0.2 0.5 1 2 5 X –j5 –j0.2 –j2 –j0.5 –j1 FREQUENCY MARKERS AT 1.3GHz, 1.8GHz, 2.3GHz, 2..8GHz 50MHz, 500Mhz, 1GHz 1.3GHz Figure 5 RF input impedance 10 SCL5 GND 5V0 SDA5 I2C BUS J3 6 5 4 3 5V Synth C37 C38 100pF 100pF 4MHz 82pF X1 C30 R16 10K 5V Synth 0R C60 150pF R20 8 7 6 5 4 3 2 1 LOSEL C31 15nF SP5769 P1 P2 C44 C47 C49 C33 Phase Comparator 68pF C41 9 10 11 12 13 14 15 16 C34 100nF T1 BCW31 5V Synth PSOUT PSOUTB 1K R19 16K C39 2.2nF +5V 0V +30V 0V 5V Synth R9 1 2 3 4 5 J1 5 WAY 0.1" HEADER 1K R10 5V Synth R8 22K Figure 6 evaluation board schematic P0 Address Ref/Comp Vcc RF Input RF Input Vee Drive Output R7 13K C50 C51 C52 100nF 100pF 4u7F C32 Programmable Divider I2C Bus Interface Osc P3/LL SCL SDA Xtal Xtal Cap Charge Pump IC2 C43 100pF 100nF 100pF 100pF100nF 100nF 4u7F C42 5V Varactor Line Varactor Line 2 Preliminary Information SP5730 11 SP5730 Preliminary Information Figure 7 Evaluation board (top view) Figure 8 Evaluation board (bottom view) 12 http://www.mitelsemi.com World Headquarters - Canada Tel: +1 (613) 592 2122 Fax: +1 (613) 592 6909 North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Asia/Pacific Tel: +65 333 6193 Fax: +65 333 6192 Europe, Middle East, and Africa (EMEA) Tel: +44 (0) 1793 518528 Fax: +44 (0) 1793 518581 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. 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