SS4003 Smart Battery Power Management FEATURES Single-chip battery charger controller and gas gauge. Provides cell balance control output for charge control. Drives 5-segment LED display for remaining capacity indication. User-selectable charge-control dat a sets. Output for charging indicator Maximum voltage charge control for Individual cells. Provides secondary cell protection functions . APPLICATIONS Portable DVD Player and Computers. 2-Cell Battery Packs or Backup Devices. PACKAGE OUTLINE 24 Pin SOP or SSOP package. GENERAL DESCRIPTION The SS4003 Charger and Gas Gauge combo IC for battery pack or in-system installation provides an accurate charge control and maintains an accurate record of available charge in rechargeable batteries. The SS4003 is dedicated for Li-Ion chemistries, and monitors capacity and other critical parameters. The SS4003 uses an A-to-D converter for voltage and current measurement. The cumulative charge into (or discharge from) the battery is continuously calculated. The on-chip ADC also monitors individual cell voltage in the battery pack and allows the SS4003 to generate charge control signals to charge the pack safely. The SS4003 provides outputs to drive LEDs to depict remaining battery capacity from full to empty with a 5-segment display. The SS4003 uses the pre-defined self-discharge rate and other compensation factors stored in the ROM to accurately adjust remaining capacity for use and standby conditions based on time. The SS4003 also automatically calibrates or learns the true battery capacity in the course of a discharge cycle from near full to near empty level. 2/01/2005 Rev.1.01 www.SiliconStandard.com 1 of 10 SS4003 PIN CONFIGURATION LED3 1 24 LED4 LED2 2 23 LED5 PDC 3 22 ExtPwr Batt_Low 4 21 DispSel CLED 5 20 S2 CFLED 6 19 S1 LED1 7 18 OSC2 I 8 17 OSC1 V2 9 16 VDD V1 10 15 RES VSS 11 14 CCTL ADJ1 12 13 ADJ2 SS4003 2/01/2005 Rev.1.01 www.SiliconStandard.com 2 of 10 SS4003 PIN DEFINITION Pin Name Pin No I/O Description LED3 LED2 PDC Batt_Low CLED CFLED LED1 I V2 V1 VSS ADJ1 ADJ2 CCTL RES VDD OSC1 OSC2 S1 S2 DispSel ExtPwr LED5 LED4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Output Output Output Output Output Output Output Input (A)*1 Input (A)* Input (A)* Input Output Output Output Input Input Input Output Input Input Input Input Output Output Remain capacity display LED3 Remain capacity display LED2 Power down control output (high enable) Secondary battery pack protection control output Charge state indicator Charge full state indicator Remain capacity display LED1 (LSB) Current sense input: 2.5V @ 0mA, ±0.5V/A High potential cell voltage input Low potential cell voltage input Power ground Low potential cell balanced control output High potential cell balanced control output Charge control output (PWM) Reset input point Power supply Oscillator input 1 Oscillator output ROM data set select input 1 ROM data set select input 2 Battery remain capacity display control (falling edge trig) External power plug in input (low true) Remain capacity display LED5 (MSB) Remain capacity display LED4 * Input (A): Analog A/D input * Note 1: -0.5V/A, for charge mode and +0.5V/A for discharge mode 2/01/2005 Rev.1.01 www.SiliconStandard.com 3 of 10 SS4003 Charging Indicator The SS4003 provides an output pin to indicate the battery charge status. The CLED output shows the battery pack is in charge mode. When the external electric power is plugs in, the CLED is on (low) and SS4003 starts to charge. The CLED turns off (high) when charge full condition is reached or external power is removed. In case of charge fault condition, the CLED will alter the output state (high/low) in every second. The CFLED will turn on (low) when the battery is in charge full state during charging period. CFLED will turn off (high) in all other conditions. Battery Remaining-Capacity Indication The battery remaining-capacity is indicated by 5 LED output pins, LED1, LED2, LED3, LED4 and LED5. Low voltages on output pins drive LEDs ON. To reflect the remaining capacity the LED outputs are ON inclusively from LED1 to LED5. The more LED outputs ON the higher the capacity. When all 5 LEDs are ON, the battery capacity reaches above 90% of the Full Charged Capacity. One, two, three and four LEDs are ON when the capacity is above 10%, 25%, 50% and 75% of the Full Charged Capacity, respectively. If the relative state of charge was lower than 10%, the LED1 flashes every second. In the charge or discharge state, the LEDs keep showing the battery capacity. For saving the battery energy, the LEDs are turned off after about 5 seconds if not in the charge or discharge state. If a negative going signal is applied to DispSel pin and the pack is neither in charge mode nor in discharge mode, the relative state of charge display function will activate. The display function will terminate after 5 seconds if no state change occurred during the period of time. Reset The SS4003 is at reset state either first connected to the battery pack or the supply voltage goes below VLVR. On hard reset, the SS4003 initializes and reads the configuration data to configure the battery pack. A suggested Reset circuits is illustrated in Application Circuits 1. Sleep mode The SS4003 switches into the sleep mode either no charge flow detected for more than 30 seconds or the relative state of charge is 0%. In the sleep mode, most of logic circuitry in the chip is turned off to minimize the power consumption. SS4003 resumes operation either an external power is plugged in or detects current flow through the sense resistor or display function is activated. Measurement Operation The SS4003 accumulates charge and discharge current and estimates self-discharge. Charge current is controlled according to state-of-charge of the battery. The battery capacity is denoted as Remaining Capacity (RCAP) in terms of relative state of charge, represents the available battery capacity at any given time. Charging increases the RCAP. Discharging and self-discharge will decreases the RCAP. An internal register is used to monitor the amount of discharge so as to adjust the Full Charge Capacity (FCCAP). FCCAP is updated only if a complete cycle of battery discharge from full to empty level is done and not interleaved by any charge operation. Therefore, the SS4003 adapts its capacity determination based on the actual conditions of discharge. The battery's initial full capacity is set to the value stored in a ROM. Until FCCAP is updated, RCAP counts up to, but not beyond, this threshold during subsequent charge. The battery’s empty state is also programmed in the ROM. The battery low percentage stores the percentage of FCCAP while the battery voltage drops to the PEV threshold. 1. Full Charge Capacity (FCCAP): FCCAP is the latest measured discharge capacity of the battery. On initialization, FCCAP is set to the value stored in the ROM. During subsequent discharge, FCCAP is updated with the latest recognized complete discharging (or learning cycle), representing a discharge from full to near empty. A learning cycle is necessary for updating the FCCAP register. The FCCAP also serves as the 100% reference threshold used by the relative state-of-charge calculation and display. 2/01/2005 Rev.1.01 www.SiliconStandard.com 4 of 10 SS4003 2. Design Capacity (DCAP): The DCAP is the user-specified battery capacity and is programmed in the ROM. 3. Remaining Capacity (RCAP): RCAP counts up to the value of FCCAP during charge and counts down during discharge and selfdischarge. RCAP is set to a predefined value if the pack voltage drops down to a predefined level. If RCAP is equal to the predefined value, RCAP keeps until voltage drops below the predefined level. To prevent overstatement of charge during periods of overcharge, RCAP stops incrementing when RCAP = FCCAP. 4. Cumulated Discharge Count (CDC): The Cumulated Discharge Count is used to record the usage of the battery which response to the life of battery. The CDC counts up during discharge independent of RCAP and can continue increasing after RCAP has decremented to 0. The CDC resets to 0 when CDC = FCCAP. Charge Counting Charge activity is detected based on a positive voltage on pin I. The voltage input at pin I is measured and converted into current through the sense resistor. If charge activity is detected, the SS4003 increases the RCAP. Charge actions increment the RCAP according to the cumulated charge counts. Discharge Counting Discharge activity is detected based on a negative voltage on pin I. The voltage input at pin I is measured and converted into current through the sense resistor. If discharge activity is detected, the SS4003 decreases the RCAP. Self-Discharge Estimation Because of the self-discharge, the SS4003 decrements RCAP periodically until the charge full or charge empty condition is detected. The estimated self-discharge rate is programmed in a ROM. Charge Control SS4003 utilizes PWM methodology for charge control. There are three types of charge control, trickle charge, constant current charge, and constant voltage charge. The SS4003 updates the charging current based on the battery’s voltage. The SS4003 uses current taper detection for Li- Ion primary charge termination and over voltage detection to suspend charging. The SS4003 also provides a number of safety terminations based on battery capacity, voltage, and conditions of individual cell. The PWM output control range is form 0% to 99%. Two types of control can be applied in typical applications. Application Circuit 2 shows a PWM to DC voltage conversion circuits that can be used in linear control applications. 2/01/2005 Rev.1.01 www.SiliconStandard.com 5 of 10 SS4003 Trickle Charge CC Charge CV Charge Finished PMV PPV PBV ICC PCV Capacity I CV PLV PEV ITC Voltage Thresholds In conjunction with monitoring the voltage at pin I for charge/discharge currents, the SS4003 monitors the battery potential through the pin V. The voltage potential is determined through a resistor-divider network on tips of cells. The battery voltage is obtained by measuring the input voltages on tips of cells and dividing factors stored in a ROM. The cell voltages are monitored for the battery low (PLV) protection, battery exhausted (PEV) and charge control. As the pack voltage is lower than the PLV, the SS4003 will enable the battery low control output through the Batt_Low pin for secondary battery pack protection. Exhausting charge threshold levels are used to determine when the battery has reached a pre-programmed “empty” state. If a validate discharge period is present, the full charge capacity will update at this point. Four pre-programmed voltage thresholds, PCV, PBV, PPV and PMV, are used to determine the charge state. When the pack voltage is lower than the PCV, the charge control is in the trickle charge mode. In the trickle charge mode, the charge current is controlled at a level below 0.2C. The charge control will enter the pre-defined constant current charge mode if the pack voltage is higher than the PCV. The cell balance function activates after the pack voltage reach the PBV and keep in active state until both cells voltage are over PBV. As the pack voltage goes higher than the PPV, the charge mode transits from constant current to constant voltage charge mode. Through the whole charge period, the SS4003 continues monitor the individual cell voltage and keep both cell voltages not larger than the PMV (predefined cell maximum voltage). Cell Balancing The SS4003 also provides the cell balance function. Passive type of cell balance technologies is implemented in SS4003. The cell balance control output pin controlled the current bypass path during the charge period. The cell balance function is activate when one of the cell voltage over the pack balance start voltage (PBV). The cell balance function will turn off when both of the cell voltages are over the PBV. Battery Management Data Selections The SS4003 reserves 4 sets of battery information that can be selected by pin S1 and pin S2. If S1 and S2 inputs both are grounded, the first set will be used. The set information include: Full-charge capacity (FCCAP), Voltage at 50% of FCCAP, Pack maximum voltage, End-discharge voltage (3% of FCCAP), charge taper current, charge current, and trickle- charge current etc. Battery data could be sent to SSC in advance, and SSC could program the customer specified data sets. 2/01/2005 Rev.1.01 www.SiliconStandard.com 6 of 10 SS4003 ABSOLUTE MAXIMUM RATINGS Power Supply Voltage……….Vss-0.3V to Vss+6.0V Input Voltage………………….Vss-0.3V to VDD+0.3V Storage Temperature………..-50? to 125? Operating Temperature……...-40? to 85? D.C. Characteristic Symbol Ta=25? Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VDD Operating Voltage - f SYS =4MHz 4.75 5 5.25 V IDD1 Operating Current (Crystal OSC) 5V No load, f SYS =4MHz ADC disable - 2 4 mA IDD2 Operating Current (RC OSC)] 5V No load, f SYS =4MHz ADC disable - 2.5 4 mA ISTB1 Standby Current (WDT Enabled) 5V - - - 10 VIL1 Input Low Voltage for I/O Ports, - - 0 - 0.3VDD V VIH1 Input High Voltage for I/O Ports, - - VDD V VIL2 Input Low Voltage ( RES) - - 0.4V DD V VIH2 Input High Voltage (RES) - - 0.9V DD VDD V VLVR Low Voltage Reset - - 2.7 IOL I/O Port Sink Current 5V VOL=0.1V DD 10 IOH I/O Port Source Current 5V VOL=0.9V DD VAD A/D Input Voltage - EAD A/D Conversion Error IADC Additional Power Consumption if A/D Converter is Used 0.7V DD 0 3 3.3 V 20 - mA -5 -10 - mA - 0 ? VDD V - - - ±0.5 ±1 LSB 5V - - 1.5 3 mA A.C. Characteristics Symbol fSYS tWDTOSC Ta=25? Test Conditions Parameter Min. Typ. Max. Unit VDD Conditions System Clock - 5V - 4000 Oscillator Period 5V - 32 65 130 µs 1 - - µs 1024 ? - - tRES External Reset Low Pulse Width tSST System Start -up Timer Period tINT Interrupt Pulse Width 2/01/2005 Rev.1.01 µA - Wake-up from HALT - - www.SiliconStandard.com 1 - kHz *t SYS µs 7 of 10 SS4003 Operating frequency: 4 MHz (OSC1 PIN take 82K resistance to Vss, 470pF capacitance to Vdd, as Application circuit1) Application Circuit 1 : VDD 100KO 0.01uF 0.1uF LED Display LED1 ~ LED5 RES 10KO 0.1uF SS4003 470 pF OSC1 VDD 82KO OSC2 fsys / 4 Application circuit 2 : AOD403 R16 10K 2 D S V+ D2 3 G1 SKS30-04AT CON1 VB+ 1 C1 4.7u/16V TP4 1 2 CON1 C15 22u/16V R25 120K/1% TP1 C18 U4 1 1 TP5 1 R14 1 TP11 R1 330K/1% R18 470R U2 1 R11 2 33K/1% C2 0.1u/16V C11 1nF/16V 3 R19 100K/1% 4 TP12 VCC IN1- 7 OUT2 IN1+ 6 IN2- GND 5 IN2+ 3.3nF 100K/1% 2 3 C19 47nF 4 8 OUT1 VCC IN1- OUT2 IN1+ IN2- GND IN2+ 7 6 5 LM358 LM358 R20 R12 4.75K/1% 1 R31 33K/1% R32 4.7K 8 OUT1 R17 470K/1% 0.05R/1%/2W R22 470K/1% 3 D 2 PDC S C14 0.1u/16V TP6 1 Q4 1G VB+ R6 IN VB+ D7 V OUT GND 1N4148 VB+ 1 3 2 V VDD R26 56K/1% TP18 R2 100K 1 VB+ R38 1K/5% R37 1K/5% 1 VB+ 1 TP10 1M/OPEN 1N4148 V+ V+ TP9 1 Q10 D6 C23 1u R27 56K/1% R28 470K C20 1u VDD 2 3 1 Q7 Q2 MMBT2222A 3 1 C 1 B 2 R15 10K E 3 C Q5 1 MMBT2222A B E G TP17 D 1 TP7 R5 100K R3 100K S V+ C4 R35 TP8 Q3 MMBT2222A Q8 1 FUSE LED 1 2 D11 LED 1 D12 2 LED 1 U7 C 3 4.7K R50 1M R13 C12 0.1u/16V C13 4.7u/16V 100K S1 SW-SPST R46 TP13 4.7K C 3 VDD DC JACK VDD Rsens 4 2 D10 VB+ R45 10K/OPEN SKS30-04AT 4.7K 3 R44 G2 2 CHG(R) BattLow BattLow R41 100K 1 B R8 4.7M/5% R23 10K 1 B Q6 MMBT2222A D4 LED-R TP16 5 D4 R53 2 1 10K/OPEN F1 VB- 1 TP15 E Q1 MMBT2222A 2 3 2 1 V+ R21 1K/5% 1 TP2 LED-G 1 1 D1 ADIN+ 4 VB- R10 160R 1 R49 VDD TP14 J1 3 100K R39 160R S1 3k R43 4.7K 2 R33 S2 D3 2 FCHG(G) VM 1 S-8232AUFT G1 E 10K/OPEN 1 VSS D3 LED 1 1 B CO D2 2 D9 10K ICT D1 LED 1 1 DO 6 2 D8 C C3 0.1u/16V SENS VC 7 4.7K R36 C5 0.22u/16V 8 VDD R34 6 VCC 1 R42 PDC 7 5 SS4003 10K/OPEN 0.22u/16V 1K R29 470K R48 R52 U3 8 1 VM 1 BattLow 2 R47 82K VM TP3 BattLow 2 C8 470pF/16V R9 160R 3 VDD R40 160R 27K 3 10K 0.1u/16V R24 2 R30 9 V2 10 V1 13 ADJ2 12 ADJ1 4 Batt_Low 7 LED1 2 LED2 1 LED3 24 LED4 23 LED5 5 CLED 6 CFLED 1 2 U1 14 CCTL 8 I 22 ExtPwr 3 PDC 16 VDD 15 RES 11 VSS 18 OSC2 17 OSC1 20 S2 19 S1 21 DispSel R7 C9 100K 0.01u/16V G C7 D C6 0.1u/16V S R4 27K VDD E VB- 2/01/2005 Rev.1.01 www.SiliconStandard.com 8 of 10 SS4003 PACKAGE DIMENSIONS: SO-24 C1 F D BA E C H ? G Symbol A B C C1 D E F G H ? 2/01/2005 Rev.1.01 0.10mm C SEATING PLANE min. Dimensioninmil nom. max. 394 290 14 590 92 4 32 4 0° 50 - 419 300 20 614 104 38 12 10° www.SiliconStandard.com 9 of 10 SS4003 SSOP-24 C1 F D BA E C H ? G Symbol A B C C1 D E F G H ? 0.10mm C SEATING PLANE min. Dimensioninmil nom. max. 228 150 8 335 54 4 22 7 0° 25 - 244 157 12 346 60 10 28 10 8° Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 2/01/2005 Rev.1.01 www.SiliconStandard.com 10 of 10