SSM2310GN N-channel Enhancement-mode Power MOSFET PRODUCT SUMMARY BVDSS 60V R DS(ON) 90mΩ ID 3A DESCRIPTION The SSM2310GN acheives fast switching performance with low gate charge without a complex drive circuit. It is suitable for low voltage applications such as DC/DC converters and general load-switching circuits. The SSM2310GN is supplied in an RoHS-compliant SOT-23-3 package, which is widely used for lower power commercial and industrial surface mount applications. Pb-free; RoHS-compliant SOT-23-3 D S SOT-23-3 G ABSOLUTE MAXIMUM RATINGS Symbol Parameter VDS Drain-source voltage VGS Gate-source voltage ID IDM PD Continuous drain current Pulsed drain current 3 , Value Units 60 V ± 20 V T A = 25°C 3 A TA = 70°C 2.3 A 10 A 1.38 W 0.01 W/°C 1,2 3 Total power dissipation , TA = 25°C Linear derating factor TSTG Storage temperature range -55 to 150 °C TJ Operating junction temperature range -55 to 150 °C THERMAL CHARACTERISTICS Symbol RΘJA Parameter Maximum thermal resistance, junction-ambient 3 Value Units 90 °C/W Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 3.Mounted on a square inch of copper pad on FR4 board ; 270°C/W when mounted on the minimum pad area required for soldering. 10/16/2005 Rev.3.1 www.SiliconStandard.com 1 of 5 SSM2310GN ELECTRICAL CHARACTERISTICS Symbol (at Tj = 25°C, unless otherwise specified) Parameter Test Conditions Min. Typ. Max. Units 60 - - V BVDSS Drain-source breakdown voltage VGS=0V, ID=250uA ∆ BV DSS/∆ Tj Breakdown voltage temperature coefficient Reference to 25°C, ID=1mA - 0.05 - V/°C RDS(ON) Static drain-source on-resistance VGS=10V, ID=3A - - 90 mΩ VGS=4.5V, ID=2A - - 120 mΩ VDS=VGS, ID=250uA 1 - 3 V VGS(th) Gate threshold voltage gfs Forward transconductance VDS=5V, ID=3A - 5 - S IDSS Drain-source leakage current VDS=60V, VGS=0V - - 10 uA VDS=48V ,VGS=0V, Tj = 70°C - - 25 uA VGS=±20V - - ±100 nA ID=3A - 6 10 nC IGSS Gate-source leakage current 2 Qg Total gate charge Qgs Gate-source charge VDS=48V - 1.6 - nC Qgd Gate-drain ("Miller") charge VGS=4.5V - 3 - nC VDS=30V - 6 - ns 2 td(on) Turn-on delay time tr Rise time ID=1A - 5 - ns td(off) Turn-off delay time RG=3.3Ω , VGS=10V - 16 - ns tf Fall time RD=30Ω - 3 - ns Ciss Input capacitance VGS=0V - 490 780 pF Coss Output capacitance VDS=25V - 55 - pF Crss Reverse transfer capacitance f=1.0MHz - 40 - pF Min. Typ. IS=1.2A, VGS=0V - - 1.2 V Source-Drain Diode Symbol Parameter 2 Test Conditions Max. Units VSD Forward voltage trr Reverse-recovery time IS=3A, VGS=0V, - 25 - ns Qrr Reverse-recovery charge dI/dt=100A/µs - 26 - nC Notes: 1.Pulse width must be limited to avoid exceeding the maximum junction temperature of 150°C. 2.Pulse width <300us, duty cycle <2%. 10/16/2005 Rev.3.1 www.SiliconStandard.com 2 of 5 SSM2310GN 10 10 8 ID , Drain Current (A) ID , Drain Current (A) 8 10V 7.0V 5.0V 4.5V T A = 150 o C 10V 7.0V 5.0V 4.5V o T A =25 C 6 V G = 3.0 V 4 2 6 V G = 3.0 V 4 2 0 0 0 1 2 3 4 0 5 1 2 3 4 5 V DS , Drain-to-Source Voltage (V) V DS , Drain-to-Source Voltage (V) Fig 1. Typical output characteristics Fig 2. Typical output characteristics 105 2.0 ID=2A 99 ID=3A V G =10V 1.8 o T A =25 C Normalized R DS(ON) RDS(ON) (mΩ ) 1.6 93 87 1.4 1.2 1.0 81 0.8 0.6 75 2 4 6 8 -50 10 0 50 100 150 T j , Junction Temperature ( o C) V GS , Gate-to-Source Voltage (V) Fig 3. On-resistance vs. gate voltage Fig 4. Normalized on-resistance vs. junction temperature 1.4 3 Normalized VGS(th) (V) 1.2 IS(A) 2 T j =150 o C T j =25 o C 1 1.0 0.8 0.6 0.4 0 0 0.2 0.4 0.6 0.8 1 V SD , Source-to-Drain Voltage (V) Fig 5. Forward characteristics of the reverse diode 10/16/2005 Rev.3.1 1.2 -50 0 50 100 150 o T j , Junction Temperature ( C) Fig 6. Gate threshold voltage vs. junction temperature www.SiliconStandard.com 3 of 5 SSM2310GN f=1.0MHz 1000 ID=3A 12 C iss V DS = 30 V V DS =38V V DS =48V 10 C (pF) VGS , Gate to Source Voltage (V) 14 8 100 6 C oss C rss 4 2 10 0 0 3 6 9 12 1 15 5 Q G , Total Gate Charge (nC) 9 13 17 21 25 29 V DS , Drain-to-Source Voltage (V) Fig 7. Gate charge characteristics Fig 8. Typical capacitance characteristics 1 100.000 Normalized Thermal Response (Rthja) Duty factor=0.5 10.000 100us 1.000 ID (A) 1ms 10ms 0.100 100ms 1s DC T A =25 o C Single Pulse 0.010 0.2 0.1 0.1 0.05 PDM 0.01 t T Single Pulse 0.01 Duty factor = t/T Peak Tj = PDM x Rthja + Ta Rthja = 270°C/W 0.001 0.0001 0.001 0.1 1 10 100 0.001 0.01 1 10 100 1000 t , Pulse Width (s) V DS , Drain-to-Source Voltage (V) Fig 9. Maximum safe operating area 0.1 1000 Fig 10. Effective transient thermal impedance VG VDS 90% QG 4.5V QGS QGD 10% VGS td(on) tr td(off) tf Fig 11. Switching time waveform 10/16/2005 Rev.3.1 Charge Q Fig 12. Gate charge waveform www.SiliconStandard.com 4 of 5 SSM2310GN PHYSICAL DIMENSIONS SOT-23-3 SOT-23-3 SYMBOL MILLIMETERS MIN. MAX. A 0.89 1.45 A1 0 0.15 A2 0.70 1.30 b 0.30 0.50 c 0.08 0.25 D 2.65 3.10 E 2.10 3.00 E1 1.19 2.30 e 0.95BSC e1 1.90BSC L 0.30 L1 Θ 0.60 0.60REF 0° 8° *Dimensions do not include mold protrusions. PART MARKING PART NUMBER CODE: ND = SSM2310GN NDXX XX = DATE/LOT CODE For a detailed explanation of these codes, please contact SSC directly. PACKING: Moisture sensitivity level MSL3 3000 pcs in antistatic tape on a reel packed in a moisture barrier bag (MBB). Information furnished by Silicon Standard Corporation is believed to be accurate and reliable. However, Silicon Standard Corporation makes no guarantee or warranty, express or implied, as to the reliability, accuracy, timeliness or completeness of such information and assumes no responsibility for its use, or for infringement of any patent or other intellectual property rights of third parties that may result from its use. Silicon Standard reserves the right to make changes as it deems necessary to any products described herein for any reason, including without limitation enhancement in reliability, functionality or design. No license is granted, whether expressly or by implication, in relation to the use of any products described herein or to the use of any information provided herein, under any patent or other intellectual property rights of Silicon Standard Corporation or any third parties. 10/16/2005 Rev.3.1 www.SiliconStandard.com 5 of 5