STM8L101xx 8-bit ultralow power microcontroller with up to 8 Kbytes Flash, multifunction timers, comparators, USART, SPI, I2C Preliminary data Features ■ Main microcontroller features – Supply voltage range 1.65 V to 3.6 V – Low power consumption (Halt: 0.3 µA, Active-halt: 0.8 µA, Dynamic Run: 150 µA/MHz) – STM8 Core with up to 16 CISC MIPS throughput – Temp. range: -40 to 85 °C and 125 °C ■ Memories – Up to 8 Kbytes of Flash program including up to 2 Kbytes of data EEPROM – Error correction code (ECC) – Flexible write and read protection modes – In-application and in-circuit programming – Data EEPROM capability – 1.5 Kbytes of static RAM ■ Clock management – Internal 16 MHz RC with fast wakeup time (typ. 4 µs) – Internal low consumption 38 kHz RC driving both the IWDG and the AWU ■ ■ ■ LQFP32 WFQFPN32 WFQFPN28 UFQFPN20 TSSOP20 ■ Peripherals – Two 16-bit general purpose timers (TIM2 and TIM3) with up and down counter and 2 channels (used as IC, OC, PWM) – One 8-bit timer (TIM4) with 7-bit prescaler – Infrared remote control (IR) – Independent watchdog – Auto-wakeup unit – Beeper timer with 1, 2 or 4 kHz frequencies – SPI synchronous serial interface – Fast I2C Multimaster/slave 400 kHz – USART with fractional baud rate generator – 2 comparators with 4 inputs each Reset and supply management – Ultralow power, ultrasafe power-on-reset /power down reset – Three low power modes: Wait, Active-halt, Halt ■ Development support – Hardware single wire interface module (SWIM) for fast on-chip programming and non intrusive debugging – In-circuit emulation (ICE) Interrupt management – Nested interrupt controller with software priority control – Up to 29 external interrupt sources ■ 96-bit unique ID I/Os – Up to 30 I/Os, all mappable on external interrupt vectors – I/Os with prog. input pull-ups, high sink/source capability and one LED driver infrared output September 2009 Table 1. Reference STM8L101xx Device summary Part number STM8L101F2, STM8L101F3, STM8L101G2, STM8L101G3 STM8L101K3 Doc ID 15275 Rev 7 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/77 www.st.com 1 Contents STM8L101xx Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3.1 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.3 Single wire data interface (SWIM) and debug module . . . . . . . . . . . . . . . 10 3.4 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.5 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.6 Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.7 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.8 Clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.9 Independent watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.10 Auto-wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.11 General purpose and basic timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.12 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.13 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.14 Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.15 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.16 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.17 I²C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 2/77 Doc ID 15275 Rev 7 STM8L101xx 9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.4 10 Contents 9.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.3.2 Power-up / power-down operating conditions . . . . . . . . . . . . . . . . . . . . 41 9.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.3.6 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9.3.7 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3.8 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 9.3.9 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.1 ECOPACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 Device ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 12 STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.1 Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 72 12.2 Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.3 13 12.2.1 STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 12.2.2 C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Doc ID 15275 Rev 7 3/77 List of tables STM8L101xx List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. 4/77 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 STM8L101xx pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 I/O Port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 HSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 52 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data . . . . . . . . 67 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 UFQFPN20 3 x 3 mm 0.6 mm mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 20-lead thin shrink small package, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Doc ID 15275 Rev 7 STM8L101xx List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. STM8L101 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Standard 20-pin UFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 20-pin TSSOP package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standard 28-pin WFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 32-pin package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 IDD(RUN) vs. VDD@ fCPU = 2 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 IDD(RUN) vs. VDD@ fCPU = 16 MHz @4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . 41 IDD(WAIT) vs. VDD@ fCPU = 2 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 IDD(WAIT) vs. VDD@ fCPU = 16 MHz @4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . 42 Typ. IDD(Halt) vs. VDD @ fCPU = 2 MHz and 16 MHz @4 temperatures. . . . . . . . . . . . . 43 Typical HSI frequency vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Typical HSI accuracy at VDD = 3 V vs temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Typical HSI accuracy at VDD = 1.65 V to 3.6 V vs temperature. . . . . . . . . . . . . . . . . . . . . 46 Typical LSI RC frequency vs. VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Typical VIL and VIH vs VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical VIL and VIH vs VDD (true open drain I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Typical pull-up resistance RPU vs VDD @ 4 temperatures with VIN=VSS . . . . . . . . . . . . . 50 Typical pull-up current Ipu vs VDD @ 4 temperatures with VIN=VSS . . . . . . . . . . . . . . . . . 51 Typ. VOL @ VDD = 3.0 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 1.8 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VDD - VOH @ VDD = 3.0 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typ. VDD - VOH @ VDD = 1.8 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . 54 Typical NRST pull-up current Ipu vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . 55 Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) . 65 WFQFPN32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LQFP32 - 32-pin low profile quad flat package outline (7 x 7) . . . . . . . . . . . . . . . . . . . . . . 67 LQFP32 recommended footprint(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) . 68 WFQFPN28 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 UFQFPN20 3 x 3 mm 0.6 mm package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 UFQFPN20 recommended footprint (1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Doc ID 15275 Rev 7 5/77 List of figures Figure 45. Figure 46. Figure 47. 6/77 STM8L101xx TSSOP20 - 20-lead thin shrink small package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TSSOP20 recommended footprint (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 STM8L101xx ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Doc ID 15275 Rev 7 STM8L101xx 1 Introduction Introduction This datasheet provides the STM8L101xx pinout, ordering information, mechanical and electrical device characteristics. For complete information on the STM8L101xx microcontroller memory, registers and peripherals, please refer to the STM8L reference manual. 2 Description The STM8L101xx devices are members of the STM8L low power 8-bit family. All devices of the SM8L product line provide the following benefits: ● ● ● ● Reduced system cost – Up to 8 Kbytes of embedded Flash program memory including up to 2 Kbytes of data EEPROM – High system integration level with internal clock oscillators and watchdogs. – Smaller battery and cheaper power supplies. Low power consumption and advanced features – Up to 16 MIPS at 16 MHz CPU clock frequency – less than 150 µA/MH, 0.8 µA in Active-halt mode, and 0.3 µA in Halt mode – Clock gated system and optimized power management Short development cycles – Application scalability across a common family product architecture with compatible pinout, memory map and modular peripherals. – Full documentation and a wide choice of development tools Product longevity – Advanced core and peripherals made in a state-of-the art technology – Product family operating from 1.65 V to 3.6 V supply The STM8L101xx low power family features the enhanced STM8 CPU core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the advantages of a CISC architecture with improved code density, a 24-bit linear addressing space and an optimized architecture for low power operations. The family includes an integrated debug module with a hardware interface (SWIM) which allows non-intrusive In-Application debugging and ultrafast Flash programming. All STM8L101xx microcontrollers feature low power low-voltage single-supply program Flash memory. The 8-Kbyte devices embed data EEPROM. The STM8L101xx low power family is based on a generic set of state-of-the-art peripherals. The modular design of the peripheral set allows the same peripherals to be found in different ST microcontroller families including 32-bit families. This makes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. Doc ID 15275 Rev 7 7/77 Description STM8L101xx All STM8L low power products are based on the same architecture with the same memory mapping and a coherent pinout. Table 2. Device features Features Flash 8/77 STM8L101xx 4 Kbytes of Flash program memory 8 Kbytes of Flash program memory including up to 2 Kbytes of Data EEPROM RAM 1.5 Kbytes Peripheral functions Independent watchdog (IWDG), Auto-wakeup unit (AWU), Beep, Serial peripheral interface (SPI), Inter-integrated circuit (I²C), Universal synchronous / asynchronous receiver / transmitter (USART), 2 comparators, Infrared (IR) interface Timers Two 16-bit timers, one 8-bit timer Operating voltage 1.65 to 3.6 V Operating temperature -40 to +85 °C -40 to +85 °C or -40 to +125 °C Packages WFQFPN28 4x 4 UFQFPN20 3x3 TSSOP20 4.4 x 6.4 WFQFPN28 4x4 UFQFPN20 3x3 WFQFPN32 LQFP32 Doc ID 15275 Rev 7 STM8L101xx 3 Product overview Product overview Figure 1. STM8L101 device block diagram @VDD VDD18 16 MHz int RC 38 kHz int RC Clock controller Clocks to core and peripherals Infrared interface PA[6:0] Port A PB[7:0] Port B PC[6:0] PD[7:0] COMP1_CH[4:1] 1.5 Kbytes SRAM USART RX, TX, CK I²C1 multimaster SDA, SCL SPI MOSI, MISO, SCK, NSS 16-bit Timer 2 TIM2_CH[2:1] TIM2_TRIG Port C 16-bit Timer 3 TIM3_CH[2:1] TIM3_TRIG Port D 8-bit Timer 4 COMP1 IWDG COMP2 Beeper COMP_REF COMP2_CH[4:1] NRST Up to 8 Kbytes Flash memory (including up to 2 Kbytes data EEPROM) Address and data bus IR_TIM VDD =1.65 V to 3.6 V VSS POR/PDR Nested interrupt controller up to 29 external interrupts Debug module (SWIM) Volt. reg. Reset STM8 Core up to 16 MHz SWIM Power AWU BEEP Legend: AWU: Auto-wakeup unit Int. RC: internal RC oscillator I²C: Inter-integrated circuit multimaster interface POR/PDR: Power on reset / power down reset SPI: Serial peripheral interface SWIM: Single wire interface module USART: Universal synchronous / asynchronous receiver / transmitter IWDG: Independent watchdog Doc ID 15275 Rev 7 9/77 Product overview 3.1 STM8L101xx Central processing unit STM8 The 8-bit STM8 core is designed for code efficiency and performance. It features 21 internal registers, 20 addressing modes including indexed, indirect and relative addressing, and 80 instructions. 3.2 Development tools Development tools for the STM8 microcontrollers include: ● The STice emulation system offering tracing and code profiling ● The STVD high-level language debugger including C compiler, assembler and integrated development environment ● The STVP Flash programming software The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit debugging/programming tools. 3.3 Single wire data interface (SWIM) and debug module The debug module with its single wire data interface (SWIM) permits non-intrusive real-time in-circuit debugging and fast memory programming. The Single wire interface is used for direct access to the debugging module and memory programming. The interface can be activated in all device operation modes. The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers. 3.4 Interrupt controller The STM8L101xx features a nested vectored interrupt controller: 10/77 ● Nested interrupts with 3 software priority levels ● 26 interrupt vectors with hardware priority ● Up to 29 external interrupt sources on 10 vectors ● Trap and reset interrupts Doc ID 15275 Rev 7 STM8L101xx 3.5 Product overview Memory The STM8L101xx devices have the following main features: ● 1.5 Kbytes of RAM ● The EEPROM is divided into two memory arrays (see the STM8L reference manual for details on the memory mapping): – Up to 8 Kbytes of embedded Flash program including up to 2 Kbytes of data EEPROM. Data EEPROM and Flash program areas can be write protected independently by using the memory access security mechanism (MASS). – 64 option bytes (one block) of which 5 bytes are already used for the device. Error correction code is implemented on the EEPROM. 3.6 Low power modes To minimize power consumption, the product features three low power modes: 3.7 ● Wait mode: CPU clock stopped, selected peripherals at full clock speed. ● Active-halt mode: CPU and peripheral clocks are stopped. The programmable wakeup time is controlled by the AWU unit. ● Halt mode: CPU and peripheral clocks are stopped, the device remains powered on. Wakeup is triggered by an external interrupt. Voltage regulators The STM8L101xx embeds an internal voltage regulator for generating the 1.8 V power supply for the core and peripherals. This regulator has two different modes: main voltage regulator mode (MVR) and low power voltage regulator mode (LPVR). When entering Halt or Active-halt modes, the system automatically switches from the MVR to the LPVR in order to reduce current consumption. 3.8 Clock control The STM8L101xx embeds a robust clock controller. It is used to distribute the system clock to the core and the peripherals and to manage clock gating for low power modes. This system clock is a 16-MHz High Speed Internal RC oscillator (HSI RC), followed by a programmable prescaler. In addition, a 38 kHz low speed internal RC oscillator is used by the independent watchdog (IWDG) and Auto-wakeup unit (AWU). 3.9 Independent watchdog The independent watchdog (IWDG) peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 38 kHZ LSI internal RC clock source, and thus stays active even in case of a CPU clock failure. Doc ID 15275 Rev 7 11/77 Product overview 3.10 STM8L101xx Auto-wakeup counter The auto-wakeup (AWU) counter is used to wakeup the device from Active-halt mode. 3.11 General purpose and basic timers STM8L101xx devices contain two 16-bit general purpose timers (TIM2 and TIM3) and one 8-bit basic timer (TIM4). 16-bit general purpose timers The 16-bit timers consist of 16-bit up/down auto-reload counters driven by a programmable prescaler. They perform a wide range of functions, including: ● Time base generation ● Measuring the pulse lengths of input signals (input capture) ● Generating output waveforms (output compare, PWM and one pulse Mode) ● Interrupt capability on various events (capture, compare, overflow, break, trigger) ● Synchronization with other timers or external signals (external clock, reset, trigger and enable) 8-bit basic timer The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. It can be used for timebase generation with interrupt generation on timer overflow. 3.12 Beeper The STM8L101xx devices include a beeper function used to generate a beep signal in the range of 1, 2 or 4 kHz when the LSI clock is operating at a frequency of 38 kHz. 3.13 Infrared (IR) interface The STM8L101xx devices contain an infrared interface which can be used with an IR LED for remote control functions. Two timer output compare channels are used to generate the infrared remote control signals. 3.14 Comparators The STM8L101xx features two zero-crossing comparators (COMP1 and COMP2) sharing the same current bias and voltage reference. The voltage reference can be internal (comparison with ground) or external (comparison to a reference pin voltage). Each comparator is connected to 4 channels, which can be used to generate interrupt, timer input capture or timer break. Their polarity can be inverted. 12/77 Doc ID 15275 Rev 7 STM8L101xx 3.15 Product overview USART The USART interface (USART) allows full duplex, asynchronous communications with external devices requiring an industry standard NRZ asynchronous serial data format. It offers a very wide range of baud rates. 3.16 SPI The serial peripheral interface (SPI) provides half/ full duplex synchronous serial communication with external devices. It can be configured as the master and in this case it provides the communication clock (SCK) to the external slave device. The interface can also operate in multi-master configuration. 3.17 I²C The inter-integrated circuit (I2C) Bus Interface is designed to serve as an interface between the microcontroller and the serial I2C bus. It provides multi-master capability, and controls all I²C bus-specific sequencing, protocol, arbitration and timing. It manages standard and fast speed modes. Doc ID 15275 Rev 7 13/77 Pin description Pin description Standard 20-pin UFQFPN package pinout PC1 / I²C_SCL 20 19 18 17 16 PC3 (HS) / USART_TX PC2 (HS) / USART_RX PA0 (HS) / SWIM / BEEP / IR_TIM Figure 2. PC4 (HS) / USART_CK / CCO 4 STM8L101xx 14 PB7 (HS) / SPI_MISO PA3 (HS) 3 13 PB6 (HS) / SPI_MOSI VSS 4 12 PB5 (HS) / SPI_SCK VDD 5 11 PB4 (HS) / SPI_NSS 6 7 8 9 10 PB3 (HS) / TIM2_TRIG / COMP2_CH2 2 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PC0 / I²C_SDA PA2 (HS) PB1 (HS) / TIM3_CH1 /COMP1_CH2 15 PB0 (HS) / TIM2_CH1 / COMP1_CH1 1 PD0 (HS) / TIM3_CH2 / COMP1_CH3 NRST / PA1 (HS) 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: 14/77 The COMP_REF pin is not available in this standard 20-pin UFQFPN package. It is available on Port A6 in the 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers (Figure 3 on page 15). Doc ID 15275 Rev 7 STM8L101xx Pin description PC1 / I²C_SCL 20 19 18 17 16 PC3 (HS) / USART_TX PC2 (HS) / USART_RX PC4 (HS) / USART_CK / CCO 20-pin UFQFPN package pinout for STM8L101F3U6ATR and STM8L101F2U6ATR part numbers PA0 (HS) / SWIM / BEEP / IR_TIM Figure 3. 14 PB7 (HS) / SPI_MISO PA6 (HS) / COMP_REF 3 13 PB6 (HS) / SPI_MOSI VSS 4 12 PB5 (HS) / SPI_SCK VDD 5 11 PB4 (HS) / SPI_NSS 6 7 8 9 10 PB3 (HS) / TIM2_TRIG / COMP2_CH2 2 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PC0 / I²C_SDA PA2 (HS) PB1 (HS) / TIM3_CH1 /COMP1_CH2 15 PB0 (HS) / TIM2_CH1 / COMP1_CH1 1 PD0 (HS) / TIM3_CH2 / COMP1_CH3 NRST / PA1 (HS) 1. Please refer to the warning below. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: For the STM8L101F3U6ATR and STM8L101F2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured . Doc ID 15275 Rev 7 15/77 Pin description STM8L101xx Figure 4. 20-pin TSSOP package pinout PC3 (HS) / USART_TX 1 20 PC2 (HS) / USART_RX PC4 (HS) / USART_CK/ CCO 2 19 PC1 / I²C_SCL PA0 (HS) / SWIM / BEEP / IR_TIM 3 18 PC0 / I²C_SDA NRST / PA1 (HS) 4 17 PB7 (HS) / SPI_MISO PA2 (HS) 5 16 PB6 (HS) / SPI_MOSI PA3 (HS) 6 15 PB5 (HS) / SPI_SCK VSS 7 14 PB4 (HS) / SPI_NSS VDD 8 13 PB3 (HS) /TIM2_TRIG /COMP2_CH2 PD0 (HS) / TIM3_CH2 / COMP1_CH3 9 12 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PB0 (HS) / TIM2_CH1 / COMP1_CH1 10 11 PB1 (HS) / TIM3_CH1 / COMP1_CH2 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). 16/77 Doc ID 15275 Rev 7 STM8L101xx PC4 (HS) / USART_CK / CCO PC3 (HS) / USART_TX PC2 (HS) / USART_RX PC1 / I²C_SCL 27 PC5 (HS) 28 PC6 (HS) Standard 28-pin WFQFPN package pinout PA0 (HS) / SWIM / BEEP / IR_TIM Figure 5. Pin description 26 25 24 23 22 PA3 (HS) 3 19 PB7 (HS) / SPI_MISO PA4 (HS) / TIM2_BKIN 4 18 PB6 (HS) / SPI_MOSI PA5 (HS) / TIM3_BKIN 5 17 PB5 (HS) / SPI_SCK VSS 6 16 PB4 (HS) / SPI_NSS VDD 7 15 PB3 (HS) / TIM2_TRIG / COMP2_CH2 8 9 10 11 12 13 14 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PD4 (HS) PB1 (HS) / TIM3_CH1 / COMP1_CH2 20 PB0 (HS) / TIM2_CH1 / COMP1_CH1 2 / COMP2_CH4 PA2 (HS) PD3(HS) PC0 / I²C_SDA PD2(HS) / COMP2_CH3 21 PD1 (HS) / TIM3_TRIG / COMP1_CH4 1 PD0 (HS) / TIM3_CH2 / COMP1_CH3 NRST / PA1 (HS) 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Note: The COMP_REF pin is not available in this standard 28-pin WFQFPN package. It is available on Port A6 in the 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (Figure 6 on page 18). Doc ID 15275 Rev 7 17/77 Pin description STM8L101xx PC4 (HS) / USART_CK / CCO PC3 (HS) / USART_TX PC2 (HS) / USART_RX PC1 / I²C_SCL 27 PC5 (HS) 28 PC6 (HS) 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers PA0 (HS) / SWIM / BEEP / IR_TIM Figure 6. 26 25 24 23 22 PD4 (HS) PA3 (HS) 3 19 PB7 (HS) / SPI_MISO PA4 (HS) / TIM2_BKIN 4 18 PB6 (HS) / SPI_MOSI PA6 (HS) / COMP_REF 5 17 PB5 (HS) / SPI_SCK VSS 6 16 PB4 (HS) / SPI_NSS VDD 7 15 PB3 (HS) / TIM2_TRIG / COMP2_CH2 8 9 10 11 12 13 14 PB2 (HS) / TIM2_CH2 / COMP2_CH1 20 PB1 (HS) / TIM3_CH1 / COMP1_CH2 2 PB0 (HS) / TIM2_CH1 / COMP1_CH1 PA2 (HS) PD2(HS) / COMP2_CH3 PC0 / I²C_SDA PD3(HS) / COMP2_CH4 21 PD1 (HS) / TIM3_TRIG / COMP1_CH4 1 PD0 (HS) / TIM3_CH2 / COMP1_CH3 NRST / PA1 (HS) 1. HS corresponds to 20 mA high sink/source capability. 2. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Warning: 18/77 For the STM8L101G3U6ATR and STM8L101G2U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured . Doc ID 15275 Rev 7 STM8L101xx PC0 / I²C_SDA PC1 / I²C_SCL PC2 (HS) / USART_RX PC3 (HS) / USART_TX 31 30 29 28 PC4 (HS) / USART_CK / CCO PC6 (HS) 32 PC5 (HS) PA0 (HS) / SWIM / BEEP / IR_TIM 32-pin package pinout 27 26 25 PD7 (HS) PA2 (HS) 2 23 PD6 (HS) PA3 (HS) PA4 (HS) / TIM2_BKIN 3 22 PD5 (HS) 4 21 PA5 (HS) / TIM3_BKIN 5 20 PD4 (HS) PB7 (HS) / SPI_MISO PA6 (HS) / COMP_REF VSS 6 19 PB6 (HS) / SPI_MOSI 7 18 PB5 (HS) / SPI_SCK VDD 8 17 PB4 (HS) / SPI_NSS PB3 (HS) / TIM2_TRIG / COMP2_CH2 PB2 (HS) / TIM2_CH2 / COMP2_CH1 PB0 (HS) / TIM2_CH1 / COMP1_CH1 14 15 16 PD3 (HS) / COMP2_CH4 10 11 12 13 PD2 (HS) / / COMP2_CH3 9 PB1 (HS) / TIM3_CH1 / COMP1_CH2 24 PD0 (HS) / TIM3_CH2 / COMP1_CH3 1 NRST / PA1 (HS) PD1 (HS) / TIM3_TRIG / COMP1_CH4 Figure 7. Pin description 1. Example given for the WFQFPN32 package. The pinout is the same for the LQFP32 package. 2. HS corresponds to 20 mA high sink/source capability. 3. High sink LED driver capability available on PA0. Refer to the description of the IR_CR register in the STM8L reference manual (RM0013). Doc ID 15275 Rev 7 19/77 Pin description STM8L101xx Table 3. Legend/abbreviation for table 4 Type I= input, O = output, S = power supply Input CM = CMOS Output HS = high sink/source (20 mA) Level Port and control Input configuration Output float = floating, wpu = weak pull-up T = true open drain, OD = open drain, PP = push pull Reset state is shown in bold. STM8L101xx pin description 1 1 4 1 1 1 NRST/PA1(2) I/O 2 2 5 2 2 2 PA2 I/O X X 3 - 6 3 3 3 PA3 I/O X - - - 4 4 4 PA4/TIM2_BKIN - - - 5 - 5 - 3 - - 5 4 4 7 6 5 5 8 6 6 - Main function (after reset) PP OD High sink/source Output Ext. interrupt floating Pin name Type Input WFQFPN32 or LQFP32 WFQFPN28 with COMP_REF(1) standard WFQFPN28 TSSOP20 UFQFPN20 with COMP_REF(1) standard UFQFPN20 Pin number wpu Table 4. Alternate function HS X X Reset X HS X X Port A2 X X HS X X Port A3 I/O X X X HS X X Port A4 Timer 2 - break input PA5/TIM3_BKIN I/O X X X HS X X Port A5 Timer 3 - break input 6 PA6/COMP_REF I/O X X X HS X X Port A6 Comparator external reference 6 7 VSS S Ground 7 7 8 VDD S Power supply 9 8 8 9 PD0/TIM3_CH2/ COMP1_CH3 I/O X X X HS X X Port D0 Timer 3 - channel 2 / Comparator 1 channel 3 - - 9 9 10 PD1/TIM3_TRIG/ COMP1_CH4 I/O X X X HS X X Port D1 Timer 3 - trigger / Comparator 1 channel 4 - - - 10 10 11 PD2/ COMP2_CH3 I/O X X X HS X X Port D2 Comparator 2 channel 3 - - - 11 11 12 PD3/ COMP2_CH4 I/O X X X HS X X Port D3 Comparator 2 channel 4 7 7 10 12 12 13 PB0/TIM2_CH1/ COMP1_CH1 I/O X X X HS X X Port B0 Timer 2 - channel 1 / Comparator 1 channel 1 20/77 Doc ID 15275 Rev 7 PA1 STM8L101xx Table 4. Pin description STM8L101xx pin description (continued) Input Output X HS X X Port B1 Timer 3 - channel 1 / Comparator 1 channel 2 9 9 12 14 14 15 PB2/ TIM2_CH2/ COMP2_CH1/ I/O X X X HS X X Port B2 Timer 2 - channel 2 / Comparator 2 channel 1 10 10 13 15 15 16 PB3/TIM2_TRIG/ COMP2_CH2 I/O X X X HS X X Port B3 Timer 2 - trigger / Comparator 2 channel 2 11 11 14 16 16 17 PB4/SPI_NSS I/O X X X HS X X Port B4 SPI master/slave select 12 12 15 17 17 18 PB5/SPI_SCK I/O X X X HS X X Port B5 SPI clock 13 13 16 18 18 19 PB6/SPI_MOSI I/O X X X HS X X Port B6 SPI master out/ slave in 14 14 17 19 19 20 PB7/SPI_MISO I/O X X X HS X X Port B7 SPI master in/ slave out - - - 20 20 21 PD4 I/O X X X HS X X Port D4 - - - - - 22 PD5 I/O X X X HS X X Port D5 - - - - - 23 PD6 I/O X X X HS X X Port D6 - - - - - 24 PD7 I/O X X X HS X X Port D7 15 15 18 21 21 25 PC0/I2C_SDA I/O X X X PP X OD I/O X High sink/source PB1/TIM3_CH1/ COMP1_CH2 Ext. interrupt 11 13 13 14 wpu 8 floating 8 Pin name Type Alternate function TSSOP20 Main function (after reset) WFQFPN32 or LQFP32 WFQFPN28 with COMP_REF(1) standard WFQFPN28 UFQFPN20 with COMP_REF(1) standard UFQFPN20 Pin number T (3) Port C0 I2C data (3) Port C1 I2C clock 16 16 19 22 22 26 PC1/I2C_SCL I/O X X X T 17 17 20 23 23 27 PC2/USART_RX I/O X X X HS X X Port C2 USART receive 18 18 1 24 24 28 PC3/USART_TX I/O X X X HS X X Port C3 USART transmit 19 19 2 25 25 29 PC4/USART_CK/ I/O X CCO X X HS X X Port C4 USART synchronous clock / Configurable clock output - - - 26 26 30 PC5 X X HS X X Port C5 I/O X Doc ID 15275 Rev 7 21/77 Pin description STM8L101xx pin description (continued) - 20 - 20 - 3 27 27 31 PC6 I/O X 28 28 32 PA0/SWIM/BEEP/ I/O X IR_TIM (4) X X X X HS X HS( 4) X X X Main function (after reset) PP OD High sink/source Output Ext. interrupt floating Pin name Type WFQFPN32 or LQFP32 Input WFQFPN28 with COMP_REF(1) standard WFQFPN28 TSSOP20 UFQFPN20 with COMP_REF(1) standard UFQFPN20 Pin number wpu Table 4. STM8L101xx Alternate function Port C6 Port A0 SWIM input and output /Beep output/Timer Infrared output 1. Please refer to the warning below. 2. When the PA1/NRST pin is used as general purpose (PA1), it can be configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section 7.1.2: Configuring NRST/PA1 pin as general purpose output. 3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not implemented). 4. High sink LED driver capability available on PA0. Warning: 22/77 For the STM8L101F2U6ATR, STM8L101F3U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers (devices with COMP_REF pin), all ports available on 32-pin packages must be considered as active ports. To avoid spurious effects, you have to configure them as input pull-up. A small increase in consumption (typ. < 300 µA) may occur during the power up and reset phase until these ports are properly configured . Doc ID 15275 Rev 7 STM8L101xx 5 Memory and register map Memory and register map Figure 8. Memory map 0x00 0000 0x00 05FF 0x00 0600 RAM (1.5 Kbytes) (1) including Stack (up to 513 bytes) (1) Reserved 0x00 47FF 0x00 4800 Option bytes 0x00 48FF 0x 004900 Reserved 0x00 49FF 0x00 5000 GPIO and peripheral registers(2) 0x00 57FF 0x00 5800 Reserved 0x00 7EFF 0x00 7F00 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 CPU/SWIM/Debug/ITC Registers Interrupt vectors Flash program memory (up to 8 Kbytes) (1) including Data EEPROM (up to 2 Kbytes) 0x00 9FFF 1. Table 5 lists the boundary addresses for each memory size. The top of the stack is at the RAM end address. 2. Refer to Table 7 for an overview of hardware register mapping, to Table 6 for details on I/O port hardware registers, and to Table 8 for information on CPU/SWIM/debug module controller registers. Doc ID 15275 Rev 7 23/77 Memory and register map Table 5. STM8L101xx Flash and RAM boundary addresses Memory area Size Start Address End address RAM 1.5 Kbytes 0x00 0000 0x00 05FF 4 Kbytes 0x00 8000 0x00 8FFF 8 Kbytes 0x00 8000 0x00 9FFF Flash program memory Table 6. Register label Register name Reset status 0x00 5000 PA_ODR Port A data output latch register 0x00 0x00 5001 PA_IDR Port A input pin value register 0xxx PA_DDR Port A data direction register 0x00 0x00 5003 PA_CR1 Port A control register 1 0x00 0x00 5004 PA_CR2 Port A control register 2 0x00 0x00 5005 PB_ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register 0xxx PB_DDR Port B data direction register 0x00 0x00 5008 PB_CR1 Port B control register 1 0x00 0x00 5009 PB_CR2 Port B control register 2 0x00 0x00 500A PC_ODR Port C data output latch register 0x00 0x00 500B PC_IDR Port C input pin value register 0xxx PC_DDR Port C data direction register 0x00 0x00 500D PC_CR1 Port C control register 1 0x00 0x00 500E PC_CR2 Port C control register 2 0x00 0x00 500F PD_ODR Port D data output latch register 0x00 0x00 5010 PD_IDR Port D input pin value register 0xxx PD_DDR Port D data direction register 0x00 0x00 5012 PD_CR1 Port D control register 1 0x00 0x00 5013 PD_CR2 Port D control register 2 0x00 Address 0x00 5002 0x00 5007 0x00 500C 0x00 5011 24/77 I/O Port hardware register map Block Port A Port B Port C Port D Doc ID 15275 Rev 7 STM8L101xx Memory and register map Table 7. General hardware register map Register label Register name Reset status 0x00 5050 FLASH_CR1 Flash control register 1 0x00 0x00 5051 FLASH_CR2 Flash control register 2 0x00 FLASH _PUKR Flash Program memory unprotection register 0x00 0x00 5053 FLASH _DUKR Data EEPROM unprotection register 0x00 0x00 5054 FLASH _IAPSR Flash in-application programming status register 0xX0 Address 0x00 5052 Block Flash 0x00 5065 to 0x00 509F Reserved area (59 bytes) 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00 EXTI_CR3 External interrupt control register 3 0x00 0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00 0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00 0x00 50A5 EXTI_CONF External interrupt port select register 0x00 WFE_CR1 WFE control register 1 0x00 WFE_CR2 WFE control register 2 0x00 0x00 50A2 ITC-EXTI 0x00 50A6 WFE 0x00 50A7 0x00 50A8 to 0x00 50AF Reserved area (8 bytes) 0x00 50B0 RST_CR Reset control register 0x00 RST_SR Reset status register 0x01 RST 0x00 50B1 0x00 50B4 to 0x00 50BF Reserved area (12 bytes) 0x00 50C0 0x00 50C1 to 0x00 50C2 0x00 50C3 CLK_CKDIVR Clock divider register Reserved area (2 bytes) CLK CLK_PCKENR Peripheral clock gating register 0x00 50C4 0x00 50C5 0x00 50C7 to 0x00 50DF 0x03 0x00 Reserved (1 byte) CLK_CCOR Configurable clock control register 0x00 Reserved area (18 bytes) Doc ID 15275 Rev 7 25/77 Memory and register map Table 7. Address STM8L101xx General hardware register map (continued) Block 0x00 50E0 0x00 50E1 IWDG 0x00 50E2 Register label Register name Reset status IWDG_KR IWDG Key register 0xXX IWDG_PR IWDG Prescaler register 0x00 IWDG_RLR IWDG Reload register 0xFF 0x00 50E3 to 0x00 50EF Reserved area (13 bytes) 0x00 50F0 0x00 50F1 AWU 0x00 50F2 0x00 50F3 BEEP AWU_CSR AWU control/status register 0x00 AWU_APR AWU asynchronous prescaler buffer register 0x3F AWU_TBR AWU timebase selection register 0x00 BEEP_CSR BEEP control/status register 0x1F 0x00 50F4 to 0x00 50FF Reserved area (12 bytes) 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 SPI_ICR SPI interrupt control register 0x00 0x00 5203 SPI_SR SPI status register 0x02 0x00 5204 SPI_DR SPI data register 0x00 0x00 5202 SPI 0x00 5205 to 0x00 520F Reserved area (11 bytes) 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C_CR2 I2C control register 2 0x00 0x00 5212 I2C_FREQR I2C frequency register 0x00 0x00 5213 I2C_OARL I2C Own address register low 0x00 0x00 5214 I2C_OARH I2C Own address register high 0x00 0x00 5215 Reserved area (1 byte) 0x00 5216 I2C_DR I2C data register 0x00 0x00 5217 I2C_SR1 I2C status register 1 0x00 0x00 5218 I2C_SR2 I2C status register 2 0x00 0x00 5219 I2C_SR3 I2C status register 3 0x00 0x00 521A I2C_ITR I2C interrupt control register 0x00 0x00 521B I2C_CCRL I2C Clock control register low 0x00 0x00 521C I2C_CCRH I2C Clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 I2C 26/77 Doc ID 15275 Rev 7 STM8L101xx Memory and register map Table 7. Address General hardware register map (continued) Block Register label 0x00 521E to 0x00 522F Register name Reset status Reserved area (18 bytes) 0x00 5230 USART_SR USART Status Register 0xC0 0x00 5231 USART_DR USART Data Register 0xXX 0x00 5232 USART_BRR1 USART Baud Rate Register 1 0x00 USART_BRR2 USART Baud Rate Register 2 0x00 0x00 5234 USART_CR1 USART Control Register 1 0x00 0x00 5235 USART_CR2 USART Control Register 2 0x00 0x00 5236 USART_CR3 USART Control Register 3 0x00 0x00 5237 USART_CR4 USART Control Register 4 0x00 0x00 5233 USART 0x00 523B to 0x00 524F Reserved area (21 bytes) Doc ID 15275 Rev 7 27/77 Memory and register map Table 7. STM8L101xx General hardware register map (continued) Register label Register name Reset status 0x00 5250 TIM2_CR1 TIM2 Control register 1 0x00 0x00 5251 TIM2_CR2 TIM2 Control register 2 0x00 0x00 5252 TIM2_SMCR TIM2 Slave Mode Control register 0x00 0x00 5253 TIM2_ETR TIM2 external trigger register 0x00 0x00 5254 TIM2_IER TIM2 Interrupt enable register 0x00 0x00 5255 TIM2_SR1 TIM2 Status register 1 0x00 0x00 5256 TIM2_SR2 TIM2 Status register 2 0x00 0x00 5257 TIM2_EGR TIM2 Event Generation register 0x00 0x00 5258 TIM2_CCMR1 TIM2 Capture/Compare mode register 1 0x00 0x00 5259 TIM2_CCMR2 TIM2 Capture/Compare mode register 2 0x00 TIM2_CCER1 TIM2 Capture/Compare enable register 1 0x00 0x00 525B TIM2_CNTRH TIM2 Counter high 0x00 0x00 525C TIM2_CNTRL TIM2 Counter low 0x00 0x00 525D TIM2_PSCR TIM2 Prescaler register 0x00 0x00 525E TIM2_ARRH TIM2 Auto-reload register high 0xFF 0x00 525F TIM2_ARRL TIM2 Auto-reload register low 0xFF 0x00 5260 TIM2_CCR1H TIM2 Capture/Compare register 1 high 0x00 0x00 5261 TIM2_CCR1L TIM2 Capture/Compare register 1 low 0x00 0x00 5262 TIM2_CCR2H TIM2 Capture/Compare register 2 high 0x00 0x00 5263 TIM2_CCR2L TIM2 Capture/Compare register 2 low 0x00 0x00 5264 TIM2_BKR TIM2 Break register 0x00 0x00 5265 TIM2_OISR TIM2 Output idle state register 0x00 Address Block 0x00 525A TIM2 0x00 5256 to 0x00 527F 28/77 Reserved area (42 bytes) Doc ID 15275 Rev 7 STM8L101xx Memory and register map Table 7. General hardware register map (continued) Register label Register name Reset status 0x00 5280 TIM3_CR1 TIM3 Control register 1 0x00 0x00 5281 TIM3_CR2 TIM3 Control register 2 0x00 0x00 5282 TIM3_SMCR TIM3 Slave Mode Control register 0x00 0x00 5283 TIM3_ETR TIM3 external trigger register 0x00 0x00 5284 TIM3_IER TIM3 Interrupt enable register 0x00 0x00 5285 TIM3_SR1 TIM3 Status register 1 0x00 0x00 5286 TIM3_SR2 TIM3 Status register 2 0x00 0x00 5287 TIM3_EGR TIM3 Event Generation register 0x00 0x00 5288 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00 0x00 5289 TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00 TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00 0x00 528B TIM3_CNTRH TIM3 Counter high 0x00 0x00 528C TIM3_CNTRL TIM3 Counter low 0x00 0x00 528D TIM3_PSCR TIM3 Prescaler register 0x00 0x00 528E TIM3_ARRH TIM3 Auto-reload register high 0xFF 0x00 528F TIM3_ARRL TIM3 Auto-reload register low 0xFF 0x00 5290 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00 0x00 5291 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00 0x00 5292 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00 0x00 5293 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00 0x00 5294 TIM3_BKR TIM3 Break register 0x00 0x00 5295 TIM3_OISR TIM3 Output idle state register 0x00 Address Block 0x00 528A TIM3 0x00 5296 to 0x00 52DF Reserved area (74 bytes) 0x00 52E0 TIM4_CR1 TIM4 Control register 1 0x00 0x00 52E1 TIM4_CR2 TIM4 Control register 2 0x00 0x00 52E2 TIM4_SMCR TIM4 Slave Mode Control Register 0x00 0x00 52E3 TIM4_IER TIM4 Interrupt enable register 0x00 TIM4_SR1 TIM4 Status register 1 0x00 0x00 52E5 TIM4_EGR TIM4 Event Generation register 0x00 0x00 52E6 TIM4_CNTR TIM4 Counter 0x00 0x00 52E7 TIM4_PSCR TIM4 Prescaler register 0x00 0x00 52E8 TIM4_ARR TIM4 Auto-reload register low 0xFF 0x00 52E4 TIM4 Doc ID 15275 Rev 7 29/77 Memory and register map Table 7. Address STM8L101xx General hardware register map (continued) Block Register label 0x00 52E9 to 0x00 52FE 0x00 52FF IR COMP 0x00 5302 Table 8. IR_CR Infra-red control register 0x00 COMP_CR Comparator control register 0x00 COMP_CSR Comparator status register 0x00 COMP_CCS Comparator channel selection register 0x00 CPU/SWIM/debug module/interrupt controller registers Register label Register name Reset status 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x80 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x05 0x00 7F09 SPL Stack pointer low 0xFF 0x00 7F0A CC Condition code register 0x28 Address 0x00 7F05 Block CPU 0x00 7F0B to 0x00 7F5F 0x00 7F60 Reserved area (85 bytes) CFG CFG_GCR 0x00 7F61 0x00 7F6F Global configuration register 0x00 Reserved area (15 bytes) 0x00 7F70 ITC_SPR1 Interrupt Software priority register 1 0xFF 0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF 0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF ITC_SPR4 Interrupt Software priority register 4 0xFF ITC_SPR5 Interrupt Software priority register 5 0xFF 0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF 0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF 0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF 0x00 7F73 0x00 7F74 30/77 Reset status Reserved area (23 bytes) 0x00 5300 0x00 5301 Register name ITC-SPR (1) Doc ID 15275 Rev 7 STM8L101xx Memory and register map Table 8. Address CPU/SWIM/debug module/interrupt controller registers (continued) Block Register label 0x00 7F78 to 0x00 7F79 0x00 7F80 Register name Reset status Reserved area (2 bytes) SWIM SWIM_CSR 0x00 7F81 to 0x00 7F8F SWIM control status register 0x00 Reserved area (15 bytes) 0x00 7F90 DM_BK1RE Breakpoint 1 register extended byte 0xFF 0x00 7F91 DM_BK1RH Breakpoint 1 register high byte 0xFF 0x00 7F92 DM_BK1RL Breakpoint 1 register low byte 0xFF 0x00 7F93 DM_BK2RE Breakpoint 2 register extended byte 0xFF 0x00 7F94 DM_BK2RH Breakpoint 2 register high byte 0xFF DM_BK2RL Breakpoint 2 register low byte 0xFF 0x00 7F96 DM_CR1 Debug module control register 1 0x00 0x00 7F97 DM_CR2 Debug module control register 2 0x00 0x00 7F98 DM_CSR1 Debug module control/status register 1 0x10 0x00 7F99 DM_CSR2 Debug module control/status register 2 0x00 0x00 7F9A DM_ENFCTR Enable function register 0xFF 0x00 7F95 DM 1. Refer to Table 7: General hardware register map on page 25 (addresses 0x00 50A0 to 0x00 50A5) for a list of external interrupt registers. Doc ID 15275 Rev 7 31/77 Interrupt vector mapping STM8L101xx 6 Interrupt vector mapping Table 9. Interrupt mapping IRQ No. Source block RESET TRAP 0 1 Reset Software interrupt Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode) Yes Yes Yes Yes 0x00 8000 - - - - 0x00 8004 Reserved FLASH 2-3 4 Description Wakeup from Halt mode AWU 5 Vector address 0x00 8008 Yes (1) 0x00 800C EOP/WR_PG_DIS - - Yes Reserved - - - - 0x00 8010 -0x00 8017 Auto wakeup from Halt - Yes Yes Yes(1) 0x00 8018 Reserved - - - - 0x00 801C 6 EXTIB External interrupt port B Yes Yes Yes Yes 0x00 8020 7 EXTID External interrupt port D Yes Yes Yes Yes 0x00 8024 8 EXTI0 External interrupt 0 Yes Yes Yes Yes 0x00 8028 9 EXTI1 External interrupt 1 Yes Yes Yes Yes 0x00 802C 10 EXTI2 External interrupt 2 Yes Yes Yes Yes 0x00 8030 11 EXTI3 External interrupt 3 Yes Yes Yes Yes 0x00 8034 12 EXTI4 External interrupt 4 Yes Yes Yes Yes 0x00 8038 13 EXTI5 External interrupt 5 Yes Yes Yes Yes 0x00 803C 14 EXTI6 External interrupt 6 Yes Yes Yes Yes 0x00 8040 15 EXTI7 External interrupt 7 Yes Yes Yes Yes 0x00 8044 16 Reserved 0x00 8048 17 Reserved - - - - 0x00 804C -0x00 804F Comparators - - Yes Yes(1) 0x00 8050 18 COMP 19 TIM2 Update /Overflow/Trigger/Break - - Yes Yes 0x00 8054 20 TIM2 Capture/Compare - - Yes Yes 0x00 8058 Yes Yes(1) 0x00 805C (1) 0x00 8060 21 22 TIM3 TIM3 2324 25 26 32/77 TIM4 SPI Update /Overflow/Break - - Capture/Compare - - Yes Reserved - - - - 0x00 80640x00 806B Update /Trigger - - Yes Yes(1) 0x00 806C Yes Yes(1) 0x00 8070 End of Transfer Yes Yes Doc ID 15275 Rev 7 Yes STM8L101xx Table 9. Interrupt vector mapping Interrupt mapping (continued) IRQ No. Source block 27 USART 28 USART 29 I2C Wakeup from Halt mode Wakeup from Active-halt mode Wakeup from Wait (WFI mode) Wakeup from Wait (WFE mode) Transmission complete/transmit data register empty - - Yes Yes(1) 0x00 8074 Receive Register DATA FULL/overrun/idle line detected/parity error - - Yes Yes(1) 0x00 8078 Yes Yes Yes Yes(1) 0x00 807C Description I2C interrupt(2) Vector address 1. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes back to WFE mode. Section : Wait for event (WFE) mode on page 70. 2. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address. Doc ID 15275 Rev 7 33/77 Option bytes 7 STM8L101xx Option bytes Option Bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory. All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures. Table 10. Addr. Option bytes Option name Option byte No. Option bits 7 6 5 4 3 2 1 0 Factory default setting 0x4800 Read-out protection (ROP) OPT1 ROP[7:0] 0x00 0x4807 - - Must be programmed to 0x00 0x00 0x4802 UBC(User Boot code size) OPT2 UBC[7:0] 0x00 0x4803 DATASIZE OPT3 DATASIZE[7:0] 0x00 0x4808 Independent watchdog option OPT4 [1:0] Table 11. 34/77 Reserved IWDG _HALT IWDG _HW 0x00 Option byte description OPT1 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable Readout protection (write access via SWIM protocol) Refer to Read-out protection section in the STM8L reference manual (RM0013) for details. OPT2 UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01-0x02: UBC contains only the interrupt vectors. 0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected ... 0x7F - Page 0 to 126 reserved for UBC, memory is write protected Refer to User boot area (UBC) section in the STM8L reference manual (RM0013) for more details. OPT3 DATASIZE[7:0] Size of the data EEPROM area 0x00: no data EEPROM area (1) 0x01 - 1 page reserved for data storage.(1) ... (1) 0x20 - 32 pages reserved for data storage.(1) Refer to Data EEPROM (DATA) section in the STM8L reference manual (RM0013) for more details. Doc ID 15275 Rev 7 STM8L101xx Option bytes Table 11. Option byte description (continued) IWDG_HW: Independent watchdog 0: Independent watchdog activated by software 1: Independent watchdog activated by hardware OPT4 IWDG_HALT: Independent window watchdog reset on Halt/Active-halt 0: Independent watchdog continues running in Halt/Active-halt mode 1: Independent watchdog stopped in Halt/Active-halt mode 1. 0x00 is the only allowed value for 4 Kbyte STM8L101xx devices. Caution: After a device reset, read access to the program memory is not guaranteed if address 0x4807 is not programmed to 0x00. Doc ID 15275 Rev 7 35/77 Unique ID 8 STM8L101xx Unique ID devices feature a 96-bit unique device identifier which provides a reference number that is unique for any device and in any context. The 96 bits of the identifier can never be altered by the user. The unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. The unique device identifier is ideally suited: ● For use as serial numbers ● For use as security keys to increase the code security in the program memory while using and combining this unique ID with software crytograhic primitives and protocols before programming the internal memory. ● To activate secure boot processes Table 12. Address 0x4925 0x4926 0x4927 Content description Unique ID bits 7 6 5 4 3 U_ID[7:0] X co-ordinate on the wafer U_ID[15:8] U_ID[23:16] 0x4928 Y co-ordinate on the wafer 0x4929 Wafer number U_ID[39:32] U_ID[31:24] 0x492A U_ID[47:40] 0x492B U_ID[55:48] 0x492C U_ID[63:56] 0x492D 36/77 Unique ID registers (96 bits) Lot number U_ID[71:64] 0x492E U_ID[79:72] 0x492F U_ID[87:80] 0x4930 U_ID[95:88] Doc ID 15275 Rev 7 2 1 0 STM8L101xx Electrical parameters 9 Electrical parameters 9.1 Parameter conditions Unless otherwise specified, all voltages are referred to VSS. 9.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by the selected temperature range). Note: The values given at 85 °C <TA ≤ 125 °C are only valid for suffix 3 versions. Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean±3Σ). 9.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given only as design guidelines and are not tested. 9.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 9. Figure 9. Pin loading conditions STM8L PIN 50 pF Doc ID 15275 Rev 7 37/77 Electrical parameters 9.1.5 STM8L101xx Pin input voltage The input voltage measurement on a pin of the device is described in Figure 10. Figure 10. Pin input voltage STM8L PIN VIN 9.2 Absolute maximum ratings Stresses above those listed as “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 13. Voltage characteristics Symbol VDD- VSS VIN VESD Ratings Min Max -0.3 4.0 Input voltage on true open drain pins (PC0 and PC1) VSS-0.3 5.25 Input voltage on any other pin (1) VSS-0.3 4.6 External supply voltage Electrostatic discharge voltage Unit V see Absolute maximum ratings (electrical sensitivity) on page 62 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected. 38/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Table 14. Current characteristics Symbol Ratings Max. IVDD Total current into VDD power line (source) 80 IVSS Total current out of VSS ground line (sink) 80 Output current sunk by IR_TIM pin (with high sink LED driver capability) 80 Output current sunk by any other I/O and control pin 25 Output current source by any I/Os and control pin -25 IIO IINJ(PIN) (1) ΣIINJ(PIN) Injected current on any pin (1) (2) Total injected current (sum of all I/O and control pins) Unit mA ±5 (2) ±25 1. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads, there is no positive injection current, and the corresponding VIN maximum must always be respected. 2. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. Table 15. Symbol TSTG TJ Thermal characteristics Ratings Storage temperature range Min Unit -65 to +150 °C Maximum junction temperature Doc ID 15275 Rev 7 150 39/77 Electrical parameters 9.3 STM8L101xx Operating conditions Subject to general operating conditions for VDD, and TA. 9.3.1 General operating conditions Table 16. General operating conditions Symbol fMASTER(1) VDD Parameter Master clock frequency PD(2) Max Unit 1.65 V ≤VDD < 3.6 V 2 16 MHz 1.65 3.6 V LQFP32 - 288 WFQFPN32 - 288 WFQFPN28 - 286 TSSOP20 - 181 UFQFPN20 - 196 LQFP32 - 83 WFQFPN32 - 227 WFQFPN28 - 71 TSSOP20 - 45 UFQFPN20 - 49 1.65 V ≤VDD < 3.6 V (6 suffix version) − 40 85 1.65 V ≤VDD < 3.6 V (3 suffix version) − 40 125 -40 °C ≤TA ≤85 °C (6 suffix version) - 40 105 °C -40 °C ≤TA ≤125 °C (3 suffix version) − 40 130 °C mW Power dissipation at TA= 125 °C for suffix 3 devices TJ Min Standard operating voltage Power dissipation at TA= 85 °C for suffix 6 devices TA Conditions Temperature range Junction temperature range °C 1. fMASTER = fCPU 2. To calculate PDmax(TA) use the formula given in thermal characteristics PDmax=(TJmax -TA)/ΘJA with TJmax in this table and ΘJA in table “Thermal characteristics” 40/77 Doc ID 15275 Rev 7 STM8L101xx 9.3.2 Electrical parameters Power-up / power-down operating conditions Table 17. Operating conditions at power-up / power-down Symbol Parameter Conditions tVDD VDD rise time rate tTEMP Reset release delay Min Typ 20 - 1300 µs/V - 1 TBD ms VDD rising Max Unit VPOR(1) Power on reset threshold 1.35 - 1.65(2) V VPDR(1) Power down reset threshold 1.40 - 1.60 V 1. Data based on characterization results, not tested in production. 2. Data guaranteed, each individual device tested in production. 9.3.3 Supply current characteristics Total current consumption The MCU is placed under the following conditions: ● All I/O pins in input mode with a static value at VDD or VSS (no load) ● All peripherals are disabled except if explicitly mentioned. Subject to general operating conditions for VDD and TA. Figure 12. IDD(RUN) vs. VDD@ fCPU = 16 MHz @4 temperatures 1 3 0.9 2.9 0.8 2.8 0.7 2.7 0.6 0.5 0.4 -40°C 0.3 25°C 0.2 85°C 0.1 125°C IDD(RUN)HSI [mA] IDD(RUN)HSI [mA] Figure 11. IDD(RUN) vs. VDD@ fCPU = 2 MHz @4 temperatures 2.6 -40°C 2.5 25°C 2.4 85°C 2.3 125°C 2.2 2.1 0 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 2 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 VDD [V] VDD [V] ai17017 ai17018 1. Typical current consumption measured with code executed from Flash. Doc ID 15275 Rev 7 41/77 Electrical parameters Table 18. STM8L101xx Total current consumption in Run mode (1) Symbol Parameter Conditions(2) Typ Max(3) fMASTER = 2 MHz 0.39 0.6 fMASTER = 4 MHz 0.55 0.7 fMASTER = 8 MHz 0.9 1.2 fMASTER = 16 MHz 1.6 2.1(5) fMASTER = 2 MHz 0.55 0.7 fMASTER = 4 MHz 0.88 1.8 fMASTER = 8 MHz 1.5 2.5 fMASTER = 16 MHz 2.7 3.5 Code executed from RAM Supply current in IDD (Run) Run mode(4) Code executed from Flash Unit mA 1. Based on characterization results, unless otherwise specified. 2. All peripherals off, VDD from 1.65 V to 3.6 V, HSI internal RC osc. , fCPU=fMASTER 3. Maximum values are given for TA = − 40 to 125 °C. 4. CPU executing typical data processing. 5. Data guaranteed, each individual device tested in production. Table 19. Symbol Total current consumption in Wait mode(1) Parameter IDD (Wait) Supply current in Wait mode Typ Max(2) fMASTER = 2 MHz 245 400 fMASTER = 4 MHz 300 450 fMASTER = 8 MHz 380 600 fMASTER = 16 MHz 510 800 Conditions CPU not clocked, all peripherals off, HSI internal RC osc. Unit µA 1. Based on characterization results, unless otherwise specified. 2. Maximum values are given for TA = -40 to 125 °C. Figure 13. IDD(WAIT) vs. VDD@ fCPU = 2 MHz @4 temperatures Figure 14. IDD(WAIT) vs. VDD@ fCPU = 16 MHz @4 temperatures 600 300 550 250 -40°C 25°C 150 85°C 100 125°C IDD(WFI)HSI [µA] IDD(RUN)HSI [µA] 500 200 450 25°C 350 50 300 0 250 1.6 1.7 1.8 1.9 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 -40°C 400 85°C 125°C 200 1.6 VDD [V] 2.6 3.1 3.6 VDD [V] ai17015 1. Typical current consumption measured with code executed from Flash. 42/77 2.1 Doc ID 15275 Rev 7 ai17016 STM8L101xx Electrical parameters Table 20. Symbol Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V (1)(2) Parameter Conditions Typ Max Unit 0.8 2 μA TA = 55 °C 1 2.5 μA TA = 85 °C 1.4 3.2 μA TA = 105 °C 2.9 7.5 μA TA = 125 °C 5.8 13 μA 2 - mA 4 6.5 μs TA = -40 °C to 25 °C 0.35 1.2(4) μA TA = 55 °C 0.6 1.8 μA TA = 85 °C 1 2.5(4) μA TA = 105 °C 2.5 6.5 μA 5.4 12(4) μA TA = -40 °C to 25 °C IDD(AH) Supply current in Active-halt mode LSI RC osc. (at 37 kHz) Supply current during IDD(WUFAH) wakeup time from Active-halt mode tWU(AH)(3) IDD(Halt) Wakeup time from Activehalt mode to run mode Supply current in Halt mode fCPU= 16 MHz TA = 125 °C IDD(WUFH) Supply current during wakeup time from Halt mode 2 - mA tWU(Halt)(3) Wakeup time from Halt mode fCPU = 16 MHz to run mode 4 6.5 μs 1. TA = -40 to 125 °C, no floating I/O, unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. Measured from interrupt event to interrupt vector fetch. To get tWU for another CPU frequency use tWU(FREQ) = tWU(16 MHz) + 1.5 (TFREQ-T16 MHz). The first word of interrupt routine is fetched 5 CPU cycles after tWU. 4. Data guaranteed, each individual device tested in production. Figure 15. Typ. IDD(Halt) vs. VDD @ fCPU = 2 MHz and 16 MHz @4 temperatures 7 6 IDD(HALT) [µA] -40°C 5 25°C 4 85°C 125°C 3 2 1 0 1.6 2.1 2.6 3.1 3.6 VDD [V] ai17014b 1. Typical current consumption measured with code executed from Flash. Doc ID 15275 Rev 7 43/77 Electrical parameters STM8L101xx Current consumption of on-chip peripherals Measurement made for fMASTER = from 2 MHz to 16 MHz Table 21. Symbol Peripheral current consumption Parameter (1) IDD(TIM2) TIM2 supply current IDD(TIM3) TIM3 supply current (1) IDD(TIM4) TIM4 timer supply current IDD(USART) USARTsupply current IDD(SPI) SPI supply current (2) IDD(I²C1) I2C supply current (2) IDD(COMP) Typ. VDD = 3.0 V Unit 9 9 (1) Comparator supply current 4 µA/MHz (2) 7 4 4 (2) 20 µA 1. Data based on a differential IDD measurement between all peripherals off and a timer counter running at 16 MHz. The CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pin toggling. Not tested in production. 2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and not clocked and the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pin toggling. Not tested in production. 44/77 Doc ID 15275 Rev 7 STM8L101xx Clock and timing characteristics Internal clock sources Subject to general operating conditions for VDD, and TA. High speed internal RC oscillator (HSI) Table 22. Symbol fHSI HSI oscillator characteristics (1) Parameter Conditions Frequency ACCHSI Accuracy of HSI oscillator (factory calibrated) IDD(HSI) Min Typ VDD = 3.0 V - 16 VDD = 3.0 V, TA = 25 °C (2) -1 Max Unit - MHz (2) 1 % VDD = 3.0 V, -10 °C ≤TA ≤ 85 °C -2.5(2) 2(2) % VDD = 3.0 V, -10 °C ≤TA ≤ 125 °C -4.5(2) 2(2) % -1.5(2)(3) 1.5(2)(3) % VDD = 3.0 V, -10 °C ≤TA ≤ 70 °C -2(2)(3) 2(2)(3) % 1.65 V ≤ VDD ≤ 3.6 V, -40 °C ≤ TA ≤125 °C -4.5(3) 3(3) % 100(3) µA VDD = 3.0 V, 0 °C ≤TA ≤ 55 °C HSI oscillator power consumption - 70 1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified. 2. Further characterization results expected. 3. Data based on characterization results, not tested in production. Figure 16. Typical HSI frequency vs VDD @ 4 temperatures 17 HSI frequency [MHz] 9.3.4 Electrical parameters 16.8 -40°C 16.6 25°C 16.4 85°C 16.2 125°C 16 15.8 15.6 15.4 15.2 15 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai17013 Doc ID 15275 Rev 7 45/77 Electrical parameters STM8L101xx Figure 17. Typical HSI accuracy at VDD = 3 V vs temperature 3.5% 3.0% 3V min 3V typical 3V max 2.5% 2.0% 1.5% 1.0% 0.5% RC accuracy 0.0% -0.5% -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 -1.0% -1.5% -2.0% -2.5% -3.0% -3.5% -4.0% -4.5% -5.0% ai17021 Temperature (°C) Figure 18. Typical HSI accuracy at VDD = 1.65 V to 3.6 V vs temperature 3.5% Min 1.65V-3.6V Max 1.65V-3.6V 3V typical 3.0% 2.5% 2.0% 1.5% 1.0% 0.5% RC accuracy 0.0% -0.5% -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 -1.0% -1.5% -2.0% -2.5% -3.0% -3.5% -4.0% -4.5% -5.0% ai17019 Temperature (°C) Low speed internal RC oscillator (LSI) Table 23. Symbol fLSI LSI oscillator characteristics (1) Parameter Conditions Frequency tsu(LSI) LSI oscillator wakeup time fdrift(LSI) LSI oscillator frequency drift(2) 0 °C ≤TA ≤ 85°C Min Typ Max Unit 26 38 56 kHz - TBD - µs -12 - 11 % 1. VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified. 2. For each individual part, this value is the frequency drift from the initial measured frequency. 46/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 19. Typical LSI RC frequency vs. VDD @ 4 temperatures 45 43 LSI frequency [MHz] 41 39 37 35 33 -40°C 31 25°C 29 85°C 27 125°C 25 1.6 2.1 2.6 3.1 3.6 VDD [V] ai17012b Doc ID 15275 Rev 7 47/77 Electrical parameters 9.3.5 STM8L101xx Memory characteristics TA = -40 to 125 °C unless otherwise specified. Table 24. RAM and hardware registers Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode (1) Halt mode (or Reset) 1.4 - - V 1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware registers (only in Halt mode). Guaranteed by characterization, not tested in production. Flash memory Table 25. Symbol VDD tprog Iprog tRET Flash program memory Parameter Conditions Min Typ fMASTER = 16 MHz 1.65 Programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte) Programming time for 1 to 64 bytes (block) write cycles (on erased byte) Operating voltage (all modes, read/write/erase) Unit - 3.6 V - - 6 ms - - 3 ms - TA=+25 °C, VDD = 1.8 V - Data retention (program memory) after 10k erase/write cycles at TA = +85 °C TRET = 55 °C 20(1) - - Data retention (data memory) after 10k erase/write cycles at TA = +85 °C TRET = 55 °C 20(1) - - Data retention (data memory) after 300k erase/write cycles at TA = +125 °C TRET = 85 °C 1(1) - - See notes (1)(2) 10(1) - - 300(1)(4) - - Erase/write cycles (data memory) See notes (1)(3) 1. Data based on characterization results, not tested in production. 2. Retention guaranteed after cycling is 10 years @ 55 °C. 3. Retention guaranteed after cycling is 1 year @ 55 °C. 4. Data based on characterization performed on the whole data memory (2 Kbytes). 48/77 (1) TA=+25 °C, VDD = 3.0 V Programming/ erasing consumption Erase/write cycles (program memory) NRW Max Doc ID 15275 Rev 7 0.7 mA - years kcycles STM8L101xx 9.3.6 Electrical parameters I/O port pin characteristics General characteristics Subject to general operating conditions for VDD and TA unless otherwise specified. All unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or an external pull-up or pull-down resistor. Table 26. I/O static characteristics (1) Symbol Parameter VIL Input low level voltage(2) VIH Input high level voltage (2) Vhys Schmitt trigger voltage hysteresis (3) Ilkg RPU CIO (7) Input leakage current (4) Weak pull-up equivalent resistor(6) Conditions Min Typ Max Unit Standard I/Os VSS-0.3 - 0.3 x VDD V True open drain I/Os VSS-0.3 - 0.3 x VDD Standard I/Os 0.70 x VDD - VDD+0.3 True open drain I/Os 0.70 x VDD - 5.25 Standard I/Os - 200 - True open drain I/Os - 250 - VSS≤VIN≤VDD Standard I/Os - - 50 (5) VSS≤VIN≤VDD True open drain I/Os - - 200(5) VSS≤VIN≤VDD PA0 with high sink LED driver capability - - 200(5) 30 45 60 kΩ - 5 - pF V mV VIN=VSS I/O pin capacitance nA 1. VDD = 3.0 V, TA = -40 to 85 °C unless otherwise specified. 2. Data based on characterization results, not tested in production. 3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Not tested in production. 6. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in Figure 22). 7. Data guaranteed by Design, not tested in production. Doc ID 15275 Rev 7 49/77 Electrical parameters STM8L101xx Figure 20. Typical VIL and VIH vs VDD (standard I/Os) 3 3 VIL and VIH [V] VIL and VIH [V] 2.5 2.5 2 -40°C -40°C 25°C 25°C 85°C 85°C 125°C 125°C 2 1.5 1.5 1 1 0.5 0.5 0 0 1.6 1.6 2.1 2.1 2.6 2.6 VDD [V] VDD [V] 3.1 3.1 3.6 3.6 ai17011 Figure 21. Typical VIL and VIH vs VDD (true open drain I/Os) 3 -40°C 25°C 2.5 VIL and VIH [V] 85°C 125°C 2 1.5 1 0.5 0 1.6 2.1 2.6 VDD [V] 3.1 3.6 ai17010 Figure 22. Typical pull-up resistance RPU vs VDD @ 4 temperatures with VIN=VSS 60 -40°C 25°C Pull-Up resistance [k ] 55 50 85°C 125°C 45 40 35 30 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai17009 50/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 23. Typical pull-up current Ipu vs VDD @ 4 temperatures with VIN=VSS 120 Pull-Up current [µA] 100 80 -40°C 25°C 85°C 125°C 60 40 20 0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 VDD [V] 3 3.15 3.3 3.45 3.6 ai17008 Doc ID 15275 Rev 7 51/77 Electrical parameters STM8L101xx Output driving current Subject to general operating conditions for VDD and TA unless otherwise specified. Table 27. Output driving current (standard ports) I/O Symbol Type Output low level voltage for an I/O pin Standard VOL (1) Parameter Conditions Min Max Unit IIO = +2 mA, VDD = 3.0 V - 0.45 V IIO = +2 mA, VDD = 1.8 V - 0.45 V IIO = +10 mA, VDD = 3.0 V - 1.2 V VDD-0.45 - V IIO = -1 mA, VDD = 1.8 V VDD-0.45 - V IIO = -10 mA, VDD = 3.0 V VDD-1.2 - V IIO = -2 mA, VDD = 3.0 V VOH (2) Output high level voltage for an I/O pin 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. The IIO current sourced must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. Table 28. Output driving current (true open drain ports) Open drain I/O Symbol Type VOL (1) Parameter Output low level voltage for an I/O pin Conditions Min Max Unit IIO = +3 mA, VDD = 3.0 V - 0.45 V IIO = +1 mA, VDD = 1.8 V - 0.45 V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. Table 29. Output driving current (PA0 with high sink LED driver capability) IR I/O Symbol Type VOL (1) Parameter Output low level voltage for an I/O pin Conditions Min Max Unit IIO = +20 mA, VDD = 2.0 V - 0.9 V 1. The IIO current sunk must always respect the absolute maximum rating specified in Table 14 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 52/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 24. Typ. VOL @ VDD = 3.0 V (standard ports) Figure 25. Typ. VOL @ VDD = 1.8 V (standard ports) -40°C 0.5 1.5 25°C -40°C 1.25 85°C 0.4 125°C 25°C 1 85°C 0.3 D B T VOL [V] 125°C 0.75 0.2 0.5 0.1 0.25 0 0 0 5 10 15 20 0 25 1 2 3 4 5 6 7 IOL [mA] IOL [mA] ai17004 ai17005 Figure 26. Typ. VOL @ VDD = 3.0 V (true open drain ports) Figure 27. Typ. VOL @ VDD = 1.8 V (true open drain ports) 0.5 0.5 -40°C 25°C 0.4 0.4 -40°C 85°C 25°C 125°C 0.3 85°C VOL [V] VOL [V] 0.3 0.2 125°C 0.2 0.1 0.1 0 D B T 0 0 1 2 3 4 5 6 0 0.5 1 IOL [mA] 1.5 2 2.5 3 IOL [mA] ai17002 ai17003 Figure 28. Typ. VDD - VOH @ VDD = 3.0 V (standard ports) Figure 29. Typ. VDD - VOH @ VDD = 1.8 V (standard ports) 2 -40°C -40°C 1.5 25°C 25°C 85°C 0.3 85°C 1.25 125°C VDD - VOH [V] VDD - VOH [V] 0.4 1.75 1 0.75 125°C 0.2 0.5 0.1 0.25 0 0 2 4 6 8 10 12 14 16 18 20 22 24 0 0 IOH [mA] 1 2 3 IOH [mA] 4 5 6 ai17001 Doc ID 15275 Rev 7 53/77 Electrical parameters STM8L101xx NRST pin The NRST pin input driver is CMOS. A permanent pull-up is present which is the same as as RPU (see Table 26 on page 49) Subject to general operating conditions for VDD and TA unless otherwise specified. Table 30. NRST pin characteristics Symbol VIL(NRST) Parameter Conditions NRST input low level voltage (1) (1) VIH(NRST) NRST input high level voltage VOL(NRST) NRST output low level voltage RPU(NRST) NRST pull-up equivalent resistor (2) VF(NRST) NRST input filtered pulse tOP(NRST) NRST output pulse width VNF(NRST) NRST input not filtered IOL = 2 mA (3) pulse (3) Min Typ (1) Max VSS - 0.8 1.4 - VDD - - VDD-0.8 30 45 60 kΩ - - 50 ns 20 - - 300 - - Unit V ns 1. Data based on characterization results, not tested in production. 2. The RPU pull-up equivalent resistor is based on a resistive transistor (Figure 30). Corresponding IPU current characteristics are described in Figure 31. 3. Data guaranteed by design, not tested in production. Figure 30. Typical NRST pull-up resistance RPU vs VDD @ 4 temperatures 60 -40°C 25°C Pull-Up resistance [k ] 55 85°C 125°C 50 45 40 35 30 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai17007 54/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 31. Typical NRST pull-up current Ipu vs VDD @ 4 temperatures 120 -40°C 25°C 100 Pull-Up current [µA] 85°C 125°C 80 60 40 20 0 1.65 1.8 1.95 2.1 2.25 2.4 2.55 2.7 2.85 3 3.15 3.3 3.45 3.6 VDD [V] ai17006 The reset network shown in Figure 32 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below the VIL max. level specified in Table 30. Otherwise the reset is not taken into account internally. Figure 32. Recommended NRST pin configuration VDD RPU RSTIN EXTERNAL RESET CIRCUIT 0.01μF Filter INTERNAL RESET STM8L Doc ID 15275 Rev 7 55/77 Electrical parameters 9.3.7 STM8L101xx Communication interfaces Serial peripheral interface (SPI) Unless otherwise specified, the parameters given in Table 31 are derived from tests performed under ambient temperature, fMASTER frequency and VDD supply voltage conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 31. Symbol fSCK 1/tc(SCK) tr(SCK) tf(SCK) tsu(NSS)(2) th(NSS) (2) SPI characteristics Parameter Min Max Master mode 0 8 Slave mode 0 8 - 30 SPI clock frequency SPI clock rise and fall time Capacitive load: C = 30 pF NSS setup time Slave mode 4 x TMASTER - NSS hold time Slave mode 80 - SCK high and low time Master mode, fMASTER = 8 MHz, fSCK= 4 MHz 105 145 Master mode 30 - Slave mode 3 - Master mode 15 - Slave mode 0 - (2) tw(SCKH) tw(SCKL)(2) Conditions(1) tsu(MI) (2) tsu(SI)(2) Data input setup time th(MI) (2) th(SI)(2) Data input hold time ta(SO)(2)(3) Data output access time Slave mode - 3x TMASTER tdis(SO)(2)(4) 30 - Data output disable time Slave mode (2) Data output valid time Slave mode (after enable edge) - 60 tv(MO)(2) Data output valid time Master mode (after enable edge) - 20 Slave mode (after enable edge) 15 - Master mode (after enable edge) 1 - tv(SO) th(SO)(2) th(MO)(2) Data output hold time Unit MHz ns 1. Parameters are given by selecting 10 MHz I/O output frequency. 2. Values based on design simulation and/or characterization results, and not tested in production. 3. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data. 4. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z. 56/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Figure 33. SPI timing diagram - slave mode and CPHA = 0 NSS input SCK Input tSU(NSS) CPHA= 0 CPOL=0 tc(SCK) th(NSS) tw(SCKH) tw(SCKL) CPHA= 0 CPOL=1 tv(SO) ta(SO) MISO OUT P UT tr(SCK) tf(SCK) th(SO) MS B O UT BI T6 OUT tdis(SO) LSB OUT tsu(SI) MOSI I NPUT B I T1 IN M SB IN LSB IN th(SI) ai14134 Figure 34. SPI timing diagram - slave mode and CPHA = 1(1) NSS input SCK Input tSU(NSS) CPHA=1 CPOL=0 CPHA=1 CPOL=1 tc(SCK) tw(SCKH) tw(SCKL) tv(SO) ta(SO) MISO OUT P UT MS B O UT tsu(SI) MOSI I NPUT th(NSS) th(SO) BI T6 OUT tr(SCK) tf(SCK) tdis(SO) LSB OUT th(SI) M SB IN B I T1 IN LSB IN ai14135 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Doc ID 15275 Rev 7 57/77 Electrical parameters STM8L101xx Figure 35. SPI timing diagram - master mode(1) High NSS input SCK Input SCK Input tc(SCK) CPHA= 0 CPOL=0 CPHA= 0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tsu(MI) MISO INP UT tw(SCKH) tw(SCKL) MS BIN tr(SCK) tf(SCK) BI T6 IN LSB IN th(MI) MOSI OUTUT M SB OUT tv(MO) B I T1 OUT LSB OUT th(MO) ai14136 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 58/77 Doc ID 15275 Rev 7 STM8L101xx Electrical parameters Inter IC control interface (I2C) Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified. The STM8L I2C interface meets the requirements of the Standard I2C communication protocol described in the following table with the restriction mentioned below: Refer to I/O port characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 32. Symbol I2C characteristics Standard mode I2C Parameter Min(2) Max (2) Fast mode I2C(1) Unit Min (2) Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - - (4) (3) (2) μs 900 (3) th(SDA) SDA data hold time tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) START condition hold time 4.0 - 0.6 - tsu(STA) Repeated START condition setup time 4.7 - 0.6 - tsu(STO) STOP condition setup time 4.0 - 0.6 - μs STOP to START condition time (bus free) 4.7 - 1.3 - μs - 400 - 400 pF tw(STO:STA) Cb 0 Capacitive load for each bus line 1. fSCK must be at least 8 MHz to achieve max fast I 2C 0 ns μs speed (400 kHz). 2. Data based on standard I2C protocol requirement, not tested in production. 3. The maximum hold time of the START condition has only to be met if the interface does not stretch the low period of SCL signal. 4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL). Note: For speeds around 200 kHz, achieved speed can have ± 5% tolerance For other speed ranges, achieved speed can have ± 2% tolerance The above variations depend on the accuracy of the external components used. Doc ID 15275 Rev 7 59/77 Electrical parameters STM8L101xx Figure 36. Typical application with I2C bus and timing diagram 1) VDD 4.7kΩ I 2C VDD 4.7kΩ BUS 100Ω SDA 100Ω SCL STM8L REPEATED START START tsu(STA) tw(STO:STA) START SDA tr(SDA) tf(SDA) tsu(SDA) STOP th(SDA) SCL th(STA) tw(SCKH) tw(SCKL) tr(SCK) tsu(STO) tf(SCK) 1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD 9.3.8 Comparator characteristics Table 33. Comparator characteristics Symbol Parameter Conditions Min (1) Typ Max(1) Unit VIN(COMP_REF) Comparator external reference -0.1 - VDD-1.25 V VIN Comparator input voltage range -0.25 - VDD+0.25 V Comparator offset error - - ± 20 mV Startup time (after BIAS_EN) - - 3(1) µs Analog comparator consumption - - 25(1) µA Analog comparator consumption during power-down - - 60(1) nA - - 2(1) µs Voffset(2) tSTART IDD(COMP) tpropag(2) Comparator propagation delay 100 mV input step with 5 mV overdrive, input rise time = 1 ns 1. Data guaranteed by design, not tested in production. 2. The comparator accuracy depends on the environment. In particular, the following cases may reduce the accuracy of the comparator and must be avoided: – Negative injection current on the I/Os close to the comparator inputs – Switching on I/Os close to the comparator inputs – Negative injection current on not used comparator input. – Switching with a high dV/dt on not used comparator input. These phenomena are even more critical when a big external serial resistor is added on the inputs. 60/77 Doc ID 15275 Rev 7 STM8L101xx 9.3.9 Electrical parameters EMC characteristics Susceptibility tests are performed on a sample basis during product characterization. Functional EMS (electromagnetic susceptibility) Based on a simple running application on the product (toggling 2 LEDs through I/O ports), the product is stressed by two electromagnetic events until a failure occurs (indicated by the LEDs). ● ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard. ● FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Prequalification trials: Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Table 34. Symbol EMS data Parameter Conditions VFESD Voltage limits to be applied on any I/O pin to LQFP32, VDD = 3.3 V induce a functional disturbance VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance Doc ID 15275 Rev 7 Level/ Class 3B LQFP32, VDD = 3.3 V, fHSI 3B LQFP32, VDD = 3.3 V, fHSI/2 4A 61/77 Electrical parameters STM8L101xx Electromagnetic interference (EMI) Based on a simple application running on the product (toggling 2 LEDs through the I/O ports), the product is monitored in terms of emission. This emission test is in line with the norm SAE J 1752/3 which specifies the board and the loading of each pin. Table 35. Symbol SEMI EMI data (1) Parameter Peak level Monitored frequency band Conditions VDD = 3.6 V, TA = +25 °C, LQFP32 conforming to IEC61967-2 Max vs. Unit 16 MHz 0.1 MHz to 30 MHz -3 30 MHz to 130 MHz -6 130 MHz to 1 GHz -5 SAE EMI Level 1 dBμV - 1. Not tested in production. Absolute maximum ratings (electrical sensitivity) Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). One model can be simulated: Human Body Model. This test conforms to the JESD22-A114A/A115A standard. Table 36. Symbol ESD absolute maximum ratings Ratings VESD(HBM) Electrostatic discharge voltage (human body model) VESD(CDM) Electrostatic discharge voltage (charge device model) Conditions Doc ID 15275 Rev 7 Unit 2000 TA = +25 °C 1. Data based on characterization results, not tested in production. 62/77 Maximum value (1) V 1000 STM8L101xx Electrical parameters Static latch-up ● LU: 2 complementary static tests are required on 10 parts to assess the latch-up performance. A supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable I/O pin) are performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181. Table 37. Electrical sensitivities Symbol LU 9.4 Parameter Static latch-up class Class II Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 16: General operating conditions on page 40. The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated using the following equation: TJmax = TAmax + (PDmax x ΘJA) Where: ● TAmax is the maximum ambient temperature in ° C ● ΘJA is the package junction-to-ambient thermal resistance in ° C/W ● PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax) ● PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. ● PI/Omax represents the maximum power dissipation on output pins Where: PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH), taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application. Doc ID 15275 Rev 7 63/77 Electrical parameters Table 38. Symbol ΘJA STM8L101xx Thermal characteristics(1) Parameter Value Unit Thermal resistance junction-ambient UFQFPN 20 - 3 x 3 mm - 0.6 mm 102 °C/W Thermal resistance junction-ambient LQFP 32 - 7 x 7 mm 60 °C/W Thermal resistance junction-ambient WFQFPN 32 - 5 x 5 mm 22 °C/W Thermal resistance junction-ambient WFQFPN 28 - 4 x 4 mm 70 °C/W Thermal resistance junction-ambient TSSOP 20 110 °C/W 1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection environment. 64/77 Doc ID 15275 Rev 7 STM8L101xx Package characteristics 10 Package characteristics 10.1 ECOPACK In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 10.2 Package mechanical data Figure 37. WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5)(1)(2) Figure 38. WFQFPN32 recommended footprint(1)(3) Seating plane C ddd C A A1 A3 D e 16 9 17 8 E2 E b 24 1 L 32 Pin # 1 ID R = 0.30 D2 L Bottom view A0A3_ME 1. Drawing is not to scale. 2. The exposed pad must be soldered to the PCB. It is recommended to connect it to VSS. 3. Dimensions are in millimeters. Table 39. WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data(1) inches(2) mm Dim. Min Typ Max Min Typ Max A(1) 0.70 0.75 0.80 0.0276 0.0295 0.0315 A1 0.00 0.02 0.05 0 0.0008 0.0020 b 0.18 0.23 0.28 0.0071 0.0091 0.0110 D 4.90 5.00 5.10 0.1929 0.1969 0.2008 D2 3.50 0.1378 Doc ID 15275 Rev 7 65/77 Package characteristics Table 39. STM8L101xx WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data(1) (continued) inches(2) mm Dim. Min Typ Max Min Typ Max E 4.90 5.00 5.10 0.1929 0.1969 0.2008 E2 3.20 3.45 3.70 0.1260 0.1358 0.1457 e L ddd 0.500 0.30 0.40 0.0197 0.50 0.0118 0.08 0.0157 0.0197 0.0031 Number of pins N 32 1. Thickness valid for the WFQFPN32 package in the sampling phase. In the production phase, the UFQFPN32 package will be used with a thickness equal to 0.6 mm. 2. Values in inches are converted from mm and rounded to 4 decimal digits. 66/77 Doc ID 15275 Rev 7 STM8L101xx Package characteristics Figure 39. LQFP32 - 32-pin low profile quad flat package outline (7 x 7)(1) Figure 40. LQFP32 recommended footprint(1)(2) Seating plane C A A2 24 A1 c b ccc C 17 16 25 0.25 mm Gage plane D D1 L A1 24 K L1 D3 17 16 25 32 9 8 1 E3 32 Pin 1 identification E1 E 9 1 8 5V_FT e 5V_ME 1. Drawing is not to scale. 2. Dimensions are in millimeters. Table 40. LQFP32- 32-pin low profile quad flat package (7x7), package mechanical data inches(1) mm Dim. Min Typ A Max Min Typ 1.6 A1 0.05 A2 1.35 b 0.3 c 0.09 D 8.8 D1 6.8 D3 Max 0.063 0.15 0.002 1.4 1.45 0.0531 0.0551 0.0571 0.37 0.45 0.0118 0.0146 0.0177 0.2 0.0035 9 9.2 0.3465 0.3543 0.3622 7 7.2 0.2677 0.2756 0.2835 5.6 0.0059 0.0079 0.2205 E 8.8 9 9.2 0.3465 0.3543 0.3622 E1 6.8 7 7.2 0.2677 0.2756 0.2835 E3 5.6 0.2205 e 0.8 0.0315 L 0.45 L1 K ccc 0.6 0.75 0.0177 1 0.0° 3.5° 0.0236 0.0295 0.0394 7.0° 0.0° 0.1 3.5° 7.0° 0.0039 Number of pins N 32 1. Values in inches are converted from mm and rounded to 4 decimal digits. Doc ID 15275 Rev 7 67/77 Package characteristics STM8L101xx Figure 41. WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) A A3 Figure 42. WFQFPN28 recommended footprint(1)(2) ddd A1 D e 14 15 7 e b E 1 21 L2 L1 28 22 DG_ME b 1. Drawing is not to scale 2. Dimensions are in millimeters Table 41. WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package (4 x 4), package mechanical data(1) inches(2) mm Dim. Min Typ Max Min Typ Max A(1) 0.7 0.75 0.8 0.0276 0.0295 0.0315 A1 0 0.02 0.05 0 0.0008 0.002 A3 b 0.2 0.18 0.25 0.0079 0.3 0.0071 0.0098 D 4 0.1575 E 4 0.1575 e 0.5 0.0197 0.0118 L1 0.25 0.35 0.45 0.0098 0.0138 0.0177 L2 0.3 0.4 0.5 0.0118 0.0157 0.0197 ddd 0.08 0.0031 Number of pins N 28 1. Thickness valid for the WFQFPN28 package in the sampling phase. In the production phase, the UFQFPN28 package will be used with a thickness equal to 0.6 mm. 2. Values in inches are converted from mm and rounded to 4 decimal digits. 68/77 Doc ID 15275 Rev 7 STM8L101xx Package characteristics Figure 43. UFQFPN20 3 x 3 mm 0.6 mm package outline (1) Figure 44. UFQFPN20 recommended footprint (1)(2) L1 D ddd L4 e 10 A3 L2 5 11 e b E 1 15 20 16 L3 A1 A BJ A0A5_ME 1. Drawing is not to scale 2. Dimensions are in millimeters Table 42. UFQFPN20 3 x 3 mm 0.6 mm mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ D 2.900 3.000 3.100 0.1181 E 2.900 3.000 3.100 0.1181 A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0 0.020 0.050 0 0.0008 0.002 A3 0.152 0.006 e 0.500 0.0197 Max L1 0.500 0.550 0.600 0.0197 0.0217 0.0236 L2 0.300 0.350 0.400 0.0118 0.0138 0.0157 L3 0.150 0.0059 L4 0.200 0.0079 b ddd 0.180 0.250 0.300 0.050 0.0071 0.0098 0.0118 0.002 1. Values in inches are rounded to 4 decimal digits Doc ID 15275 Rev 7 69/77 Package characteristics STM8L101xx Figure 45. TSSOP20 - 20-lead thin shrink small package outline (1) Figure 46. TSSOP20 recommended footprint (1)(2) D 20 11 c E1 1 E 10 α A1 A L A2 L1 CP b e TSSOP20-M BJ 1. Drawing is not to scale 2. Dimensions are in millimeters Table 43. 20-lead thin shrink small package, mechanical data inches(1) mm Dim. Min Typ A Max Min 1.2 A1 0.05 A2 0.8 b 0.19 1 CP c 0.09 D 6.4 E Max 0.0472 0.15 0.002 1.05 0.0315 0.3 0.0075 0.0059 0.0394 0.0413 0.0118 0.1 0.0039 0.2 0.0035 6.5 6.6 0.252 0.2559 0.2598 6.2 6.4 6.6 0.2441 0.252 0.2598 E1 4.3 4.4 4.5 0.1693 0.1732 0.1772 e - 0.65 - 0.1693 0.0256 - L 0.45 0.6 0.75 0.1693 0.0236 0.0295 L1 a 1 0° N 0.0079 0.0394 8° 0° Number of pins 20 1. Values in inches are converted from mm and rounded to 4 decimal digits. 70/77 Typ Doc ID 15275 Rev 7 8° STM8L101xx 11 Device ordering information Device ordering information Figure 47. STM8L101xx ordering information scheme Example: STM8 L 101 F 3 U 6 A TR Product class STM8 microcontroller Family type L = Low power Sub-family type 101 = sub-family Pin count K = 32 pins G = 28 pins F = 20 pins Program memory size 2 = 4 Kbytes 3 = 8 Kbytes Package U = VFQFPN, WFQFPN or UFQFPN T = LQFP P = TSSOP Temperature range 3 = -40 °C to 125 °C 6 = -40 °C to 85 °C COMP_REF availability on UFQFPN20 A = COMP_REF available Blank = COMP_REF not available Shipping TR = Tape and reel Blank = Tray 1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to you. Doc ID 15275 Rev 7 71/77 STM8 development tools 12 STM8L101xx STM8 development tools Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer. 12.1 Emulation and in-circuit debugging tools The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and future ST microcontrollers. STice key features 72/77 ● Occurrence and time profiling and code coverage (new features) ● Program and data trace recording up to 128 KB records ● Read/write on the fly of memory during emulation ● In-circuit debugging/programming via SWIM protocol ● 8-bit probe analyzer ● Power supply follower managing application voltages between 1.62 to 5.5 V ● Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements ● Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8. Doc ID 15275 Rev 7 STM8L101xx 12.2 STM8 development tools Software tools STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8, which are available in a free version that outputs up to 16 Kbytes of code. 12.2.1 STM8 toolset STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com/mcu. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring ● Seamless integration of C and ASM toolsets ● Full-featured debugger ● Project management ● Syntax highlighting editor ● Integrated programming interface ● Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences. 12.2.2 C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of your application directly from an easy-to-use graphical interface. Available toolchains include: 12.3 ● Cosmic C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.cosmic-software.com. ● Raisonance C compiler for STM8 – Available in a free version that outputs up to 16 Kbytes of code. For more information, see www.raisonance.com. ● STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows you to assemble and link your application source code. Programming tools During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on your application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming your STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family. Doc ID 15275 Rev 7 73/77 Revision history 13 STM8L101xx Revision history Table 44. Document revision history Date Revision 19-Dec-2008 1 Intitial release. 2 Added TSSOP28 package Modified packages on first page COMPx_OUT pins removed Added Figure 6: 28-pin TSSOP package pinout on page 17 Modified Section 9: Electrical parameters on page 37. Updated UBC[7:0] description in Section 7: Option bytes. Updated low power current consumption on cover page. Updated Table 13: Voltage characteristics, Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V, Table 26: I/O static characteristics, Table 30: NRST pin characteristics, and Section 9.3.9: EMC characteristics. Updated PA1/NRST, PC0 and PC1 in Table 4: STM8L101xx pin description. Added ECC feature. Changed internal RC frequency to 38 kHz. Updated electrical characteristics in Table 16, Table 18, Table 19, Table 20, Table 22, Table 23, and Table 26. 3 Corrected title on cover page. Changed VFQFPN32 to WFQFPN32 and updated Table 39: WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data. Updated Table 13, Table 26, and Table 33. 14-May-2009 4 Replaced WFQFPN20 3 x 3 mm 0.8 mm package by UFQFPN20 3 x 3 mm 0.6 mm package (first page, Table 16: General operating conditions on page 40, Table 38: Thermal characteristics on page 64, Section 10.2: Package mechanical data on page 65) Added one UFQFPN20 version with COMP_REF Modified Figure 40: LQFP32 recommended footprint(1) on page 67 Added IPROG values in Table 25: Flash program memory on page 48 Updated Table 31: SPI characteristics on page 56 15-May-2009 5 Added STM8L101F3U6ATR part number in Section 4: Pin description on page 14 and in Figure 47: STM8L101xx ordering information scheme on page 71 22-Apr-2009 24-Apr-2009 74/77 Changes Doc ID 15275 Rev 7 STM8L101xx Revision history Table 44. Document revision history (continued) Date 12-Jun-2009 Revision Changes 6 Removed TSSOP28 package Modified consumption value on first page Added BEEP_CSR (address 00 50F3h) in Table 7: General hardware register map on page 25 TIM2_PSCRL replaced with TIM2_PSCR and CLK_PCKEN replaced with CLK_PCKENR in Table 7: General hardware register map on page 25 Added graphs in Section 9: Electrical parameters on page 37 Added tWU(AH) and tWU(Halt) max values in Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 43 Modified Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 43 Updated Table 22: HSI oscillator characteristics on page 45, Table 23: LSI oscillator characteristics on page 46 and Table 24: RAM and hardware registers on page 48 Modified Table 27: Output driving current (standard ports) on page 52 Removed note 1 in Table 37: Electrical sensitivities on page 63 Added note to Table 39: WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package (5 x 5), package mechanical data on page 65 and Table 41: WFQFPN28 - 28-lead very very thin fine pitch quad flat nolead package (4 x 4), package mechanical data on page 68 Doc ID 15275 Rev 7 75/77 Revision history STM8L101xx Table 44. Document revision history (continued) Date 07-Sep-2009 76/77 Revision Changes 7 Added STM8L101F2U6ATR, STM8L101G2U6ATR and STM8L101G3U6ATR part numbers Modified Section 2: Description on page 7. Modified Table 2: Device features on page 8 (Flash) Modifiied Figure 1: STM8L101 device block diagram on page 9 Modified Section 3.5: Memory on page 11 Added note below Figure 2: Standard 20-pin UFQFPN package pinout on page 14 and Figure 5: Standard 28-pin WFQFPN package pinout on page 17 Added Figure 6: 28-pin WFQFPN package pinout for STM8L101G3U6ATR and STM8L101G2U6ATR part numbers on page 18 Modified reset values for Px_IDR registers in Table 6: I/O Port hardware register map on page 24 Added Section 6: Interrupt vector mapping on page 32 Modified OPT numbers in Section 7: Option bytes on page 34 Modified OPT2 in Table 10: Option bytes on page 34 Added Section 8: Unique ID on page 36 TIM_IR pin replaced with IR_TIM pin Modified Table 20: Total current consumption and timing in Halt and Active-halt mode at VDD = 1.65 V to 3.6 V on page 43 Modified Figure 15: Typ. IDD(Halt) vs. VDD @ fCPU = 2 MHz and 16 MHz @4 temperatures on page 43 and Figure 19: Typical LSI RC frequency vs. VDD @ 4 temperatures on page 47 Modified Table 27: Output driving current (standard ports) on page 52 Updated Table 29: Output driving current (PA0 with high sink LED driver capability) on page 52 Modified : Functional EMS (electromagnetic susceptibility) on page 61 Modified conditions in Table 35: EMI data on page 62 Added note to Figure 37: WFQFPN32 - 32-lead very very thin fine pitch quad flat no-lead package outline (5 x 5) on page 65 Modified Figure 41: WFQFPN28 - 28-lead very very thin fine pitch quad flat no-lead package outline (4 x 4) on page 68 Added Figure 44: UFQFPN20 recommended footprint (1) on page 69 Added Figure 46: TSSOP20 recommended footprint (1) on page 70 CMP replaced with COMP Doc ID 15275 Rev 7 STM8L101xx Please Read Carefully: Information in this document is provided solely in connection with ST products. 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The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. © 2009 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com Doc ID 15275 Rev 7 77/77