STMICROELECTRONICS STS5PF30L_07

STS5PF30L
P-channel 30V - 0.045Ω - 5A SO-8
STripFET™ Power MOSFET
General features
Type
VDSS
RDS(on)
ID
STS5PF30L
30V
<0.055Ω
5A
■
Conduction losses reduced
■
Switching losses reduced
■
Low threshold drive
■
Standard outline for easy automated surface
mount assembly
S0-8
Description
This Power MOSFET is the latest development of
STMicroelectronics unique “single feature size™”
strip-based process. The resulting transistor
shows extremely high packing density for low onresistance, rugged avalanche characteristics and
less critical alignment steps therefore a
remarkable manufacturing reproducibility.
Internal schematic diagram
Applications
■
Switching application
Order code
Part number
Marking
Package
Packaging
STS5PF30L
S5PF30L
SO-8
Tape & reel
February 2007
Rev 4
1/12
www.st.com
12
Contents
STS5PF30L
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1
Electrical characteristics (curves)
............................. 6
3
Test circuit
4
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2/12
................................................ 8
STS5PF30L
1
Electrical ratings
Electrical ratings
Table 1.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
VDS
Drain-source voltage (vgs = 0)
30
V
VGS
Gate- source voltage
±16
V
ID
Drain current (continuous) at TC = 25°C
5
A
ID
Drain current (continuous) at TC = 100°C
4
A
Drain current (pulsed)
20
A
Total dissipation at TC = 25°C dual operating
2.5
W
-55 to 150
°C
150
°C
IDM
(1)
PTOT
TJ
Junction temperature
Storage temperature range
Tstg
1. Pulse width limited by safe operating area
Note:
For the p-channel Power MOSFET actual polarity of voltages and current has
to be reversed
Table 2.
Rthj-a
TL
Thermal data
(1)
Thermal resistance junction-ambient Max
Maximum lead temperature for soldering purpose
50
°C/W
300
°C
1. Mounted on FR-4 board (t≤10sec)
3/12
Electrical characteristics
2
STS5PF30L
Electrical characteristics
(TCASE=25°C unless otherwise specified)
Table 3.
Symbol
V(BR)DSS
On/off states
Parameter
Drain-source
breakdown voltage
Test conditions
ID = 250 µA, VGS = 0
30
Unit
V
µA
VDS=Max rating,
TC=125°C
10
µA
±100
nA
1.6
2.5
V
0.045
0.065
0.055
0.075
Ω
Ω
IGSS
Gate-body leakage
current (VDS = 0)
VGS = ± 16V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250µA
RDS(on)
Static drain-source on
resistance
VGS = 10V, ID = 2.5A
VGS = 4.5V, ID = 2.5A
1
Dynamic
Parameter
gfs(1)
Forward transconductance
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer
capacitance
Qg
Total gate charge
Qgs
Gate-source charge
Qgd
Gate-drain charge
Test conditions
VDS= 15V, ID =2.5A
VDS = 25V, f = 1 MHz,
VGS = 0
VDD = 24V, ID = 5A,
VGS = 5V
(see Figure 14)
1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5.
4/12
Max.
1
Zero gate voltage
Drain current (VGS = 0)
Symbol
Typ.
VDS = Max rating
IDSS
Table 4.
Min.
Min.
Typ.
Max.
Unit
10
S
1350
pF
490
pF
130
pF
12.5
16
nC
5
nC
3
nC
STS5PF30L
Electrical characteristics
Table 5.
Symbol
Switching times
Parameter
Test conditions
Min.
Typ.
Max.
Unit
td(on)
tr
Turn-on delay time
Rise time
VDD=15 V, ID=2.5A,
RG=4.7Ω, VGS= 4.5V
(see Figure 13)
25
35
ns
ns
td(off)
tf
Turn-off Delay Time
Fall Time
VDD=15 V, ID=2.5A,
RG=4.7Ω, VGS= 4.5V
(see Figure 13)
125
35
ns
ns
Table 6.
Symbol
ISD
Source drain diode
Parameter
Test conditions
Min
Typ.
Max
Unit
Source-drain current
5
A
ISDM
(1)
Source-drain current (pulsed)
20
A
VSD
(2)
Forward on voltage
ISD = 5A, VGS = 0
1.2
V
Reverse recovery time
Reverse recovery charge
Reverse recovery current
ISD = 5A, VDD = 15V
di/dt = 100A/µs,
Tj = 150°C
(see Figure 15)
trr
Qrr
IRRM
45
36
1.6
ns
nC
A
1. Pulse width limited by safe operating area.
2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%
5/12
Electrical characteristics
STS5PF30L
2.1
Electrical characteristics (curves)
Figure 1.
Safe operating area
Figure 2.
Thermal impedance
Figure 3.
Output characteristics
Figure 4.
Transfer characteristics
Figure 5.
Transconductance
Figure 6.
Static drain-source on resistance
6/12
STS5PF30L
Electrical characteristics
Figure 7.
Gate charge vs gate-source voltage Figure 8.
Figure 9.
Normalized gate threshold voltage
vs temperature
Figure 11. Source-drain diode forward
characteristics
Capacitance variations
Figure 10. Normalized on resistance vs
temperature
Figure 12. Normalized BVDSS vs temperature
7/12
Test circuit
3
Test circuit
Figure 13. Switching times test circuit for
resistive load
Figure 15. Test circuit for diode recovery
behavior
8/12
STS5PF30L
Figure 14. Gate charge test circuit
STS5PF30L
4
Package mechanical data
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second level interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com
9/12
Package mechanical data
STS5PF30L
SO-8 MECHANICAL DATA
DIM.
mm.
MIN.
TYP
A
a1
inch
MAX.
TYP.
1.75
0.1
MAX.
0.068
0.25
a2
0.003
0.009
1.65
0.064
a3
0.65
0.85
0.025
0.033
b
0.35
0.48
0.013
0.018
b1
0.19
0.25
0.007
0.010
C
0.25
0.5
0.010
0.019
D
4.8
5.0
0.188
0.196
E
5.8
6.2
0.228
c1
45 (typ.)
1.27
e
e3
3.81
0.150
3.8
4.0
0.14
L
0.4
1.27
0.015
S
0.244
0.050
F
M
10/12
MIN.
0.6
0.157
0.050
0.023
8 (max.)
STS5PF30L
5
Revision history
Revision history
Table 7.
Revision history
Date
Revision
06-Feb-2007
4
Changes
The document has been reformatted
11/12
STS5PF30L
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