STS8DNF3LL Dual N-channel 30V - 0.017Ω - 8A SO-8 Low gate charge STripFET™ II Power MOSFET General features Type VDSS RDS(on) ID STS8DNF3LL 30V <0.020Ω 8A ■ Optimal RDS(on) x Qg trade-off @ 4.5V ■ Conduction losses reduced ■ Switching losses reduced S0-8 Description This application specific Power MOSFET is the second generation of STMicroelectronics unique "Single Feature Size™" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. Internal schematic diagram Applications ■ Switching application Order codes Part number Marking Package Packaging STS8DNF3LL S8DNF3LL SO-8 Tape & reel January 2007 Rev 10 1/12 www.st.com 12 Contents STS8DNF3LL Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) ............................ 6 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/12 ................................................ 8 STS8DNF3LL 1 Electrical ratings Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (vgs = 0) 30 V VGS Gate- source voltage ±16 V ID Drain current (continuos) at TC = 25°C single operating 8 A ID Drain current (continuos) at TC = 100°C single operating 5 A IDM (1) Drain current (pulsed) 32 A PTOT Total dissipation at TC = 25°C dual operating Total dissipation at TC = 25°C single operating 2 1.6 W W 1. Pulse width limited by safe operating area Table 2. Thermal data (1)Thermal Rthj-a TJ Tstg resistance junction-ambient single operating Thermal resistance junction-ambient dual operating 78 62.5 °C/W °C/W Thermal operating junction-ambient 150 °C -55 to 150 °C Storage temperature 1. Mounted on FR-4 board with 0.5 in2 pad of Cu. 3/12 Electrical characteristics 2 STS8DNF3LL Electrical characteristics (TCASE=25°C unless otherwise specified) Table 3. On/off states Symbol Parameter V(BR)DSS Drain-source Breakdown voltage Test conditions ID = 250 µA, VGS = 0 30 Unit V µA VDS=Max rating, TC=125°C 10 µA ±100 nA IGSS Gate-body leakage current (VDS = 0) VGS = ± 16V VGS(th) Gate threshold voltage VDS = VGS, ID = 250µA RDS(on) Static drain-source on resistance VGS = 10V, ID = 4A VGS = 4.5V, ID = 4A gfs (1) Max. 1 Zero gate voltage Drain current (VGS = 0) Symbol Typ. VDS = Max rating IDSS Table 4. Min. 1 V 0.017 0.020 0.020 0.024 Ω Ω Dynamic Parameter Forward transconductance Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions Min. VDS = 15V, ID= 4 A VDS = 25V, f = 1 MHz, VGS = 0 Typ. Unit 12.5 S 800 pF 250 pF 60 pF 12.5 VDD = 15V, ID = 8A, VGS = 5V (see Figure 14) Max. 17 nC 3.2 nC 4.5 nC 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5. Table 5. Symbol 4/12 Switching times Parameter Test conditions Min. Typ. Max. Unit td(on) tr Turn-on delay time Rise time VDD=15 V, ID=4A, RG=4.7Ω, VGS= 4.5V (see Figure 13) 18 32 ns ns td(off) tf Turn-off Delay Time Fall Time VDD=15 V, ID=4A, RG=4.7Ω, VGS= 4.5V (see Figure 13) 21 11 ns ns STS8DNF3LL Electrical characteristics Table 6. Symbol ISD Source drain diode Parameter Test conditions Min. Typ. Max Unit Source-drain current 8 A ISDM (1) Source-drain current (pulsed) 32 A VSD (2) Forward on voltage ISD = 8A, VGS = 0 1.2 V Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 8A, VDD = 15V di/dt = 100A/µs, Tj = 150°C (see Figure 15) trr Qrr IRRM 23 17 1.5 ns nC A 1. Pulse width limited by safe operating area. 2. Pulsed: Pulse duration = 300 µs, duty cycle 1.5% 5/12 Electrical characteristics STS8DNF3LL 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characteristics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance 6/12 STS8DNF3LL Electrical characteristics Figure 7. Gate charge vs. gate-source voltage Figure 8. Figure 9. Normalized gate threshold voltage vs. temperature Figure 11. Source-drain diode forward characteristics Capacitance variations Figure 10. Normalized on resistance vs. temperature Figure 12. Normalized breakdown voltage vs. temperature 7/12 Test circuit 3 STS8DNF3LL Test circuit Figure 13. Switching times test circuit for resistive load Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test switching and diode recovery times circuit Figure 17. Unclamped inductive waveform 8/12 Figure 18. Switching time waveform STS8DNF3LL 4 Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at : www.st.com 9/12 Package mechanical data STS8DNF3LL SO-8 MECHANICAL DATA DIM. mm. MIN. TYP A a1 inch MAX. TYP. 1.75 0.1 MAX. 0.068 0.25 a2 0.003 0.009 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.25 0.5 0.010 0.019 D 4.8 5.0 0.188 0.196 E 5.8 6.2 0.228 c1 45 (typ.) 1.27 e e3 3.81 0.150 3.8 4.0 0.14 L 0.4 1.27 0.015 S 0.244 0.050 F M 10/12 MIN. 0.6 0.157 0.050 0.023 8 (max.) STS8DNF3LL 5 Revision history Revision history Table 7. Revision history Date Revision Changes 11-Sep-2006 8 Complete document 15-Nov-2006 9 The document has been reformatted 30-Jan-2007 10 Typo mistake on Table 1. 11/12 STS8DNF3LL Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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