STMICROELECTRONICS STV5345

STV5345
STV5345/H - STV5345/T
TELETEXT DECODER WITH 8 INTEGRATED PAGES
COMPLETE TELETEXT DECODER INCLUDING ON-CHIP 8 PAGES MEMORY, REDUCING EMC RADIATIONS
UPWARD SOFTWARE AND HARDWARE
COMPATIBLE WITH PREVIOUS SGS-THOMSON’s DECODER SDA5243
DIRECT INTERFACE TO AN EXTERNAL
STATIC RAM OF 8kBYTES FOR UP TO 16
PAGES APPLICATION
AUTOMATIC SELECTION OF UP TO SIX NATIONAL LANGUAGES
FOUR SIMULTANEOUS PAGE REQUESTS
DISPLAY OF THE 25TH STATUS ROW
MICROPROCESSOR CONTROL VIA AN I2C
BUS (SLAVE ADDRESS 0010001 R/W)
DATA ACQUISITION AVAILABLE FROM
LINES 2 TO 22 OR FROM A COMPLETE
FIELD
HIGH QUALITY DISPLAY USING A CHARACTER MATRIX OF 12 x 10 DOTS
SINGLE + 5V SUPPLY VOLTAGE
ON-CHIP MASK PROGRAMMABLE ROM
CHARACTER GENERATORS
HCMOS PROCESS
DESCRIPTION
The STV5345 is a HCMOS integrated circuit which
performs all the processing of logical data within a
625 lines system teletext decoder. It is designed to
operate in conjunction with one-chip : the SAA5231
integrated chip which extracts Teletext information
embedded in a composite video signal. Up to 8
pages of display data can be stored in internal
memory. Using 8Kbytes of external memory leads
to a 16 pages application. A complete system also
comprises a microprocessor controlling the
STV5345 via a 2-wires serial bus. An on-chip ROM
memory contains the character sets. The STV5345
performs automatic selection of one of up to six
natural languages. Data bytes may be decoded in
either 7-Bit plus parity or in full 8-Bit formats. The
chip set also supports facilities for reception and
display of higher-level protocol data.
April 1994
DIP40
(Plastic Package)
ORDER CODE : STV5345
STV5345/H
STV5345/T
West European
East European
Turkish & European
PIN CONNECTIONS
VDD
1
40
A10
A11
2
39
A9
A12
3
38
A8
OE
4
37
A7
WE
5
36
A6
TTD
6
35
A5
TTC
7
34
A4
ODD/EVEN
8
33
A3
F6
9
32
A2
VCS
10
31
A1
SAN D
11
30
A0
TCS/SCS
12
29
D7
R
13
28
D6
G
14
27
D5
B
15
26
D4
COR
16
25
D3
B LA N
17
24
D2
Y
18
23
D1
SCL
19
22
D0
SDA
20
21
V SS
5345-01.EPS
.
.
.
.
..
.
.
.
..
.
1/25
STV5345 - STV5345/H - STV5345/T
PIN DESCRIPTION
Symbol
Function
Description
1
VDD
+5V
2,3,40 *
A11, A12, A10
Chapter address
Positive supply voltage
4*
OE
Output enable
5*
WE
Write enable
Active-low external static RAM write enable control
signal. It supports write-cycles interleaved with
read-cycles.
6
TTD
Teletext data input
An A.C. coupled teletext data input supplied by the
SAA5231 chip is latched to VSS between 4 and 8µs
after each TV line.
7
TTC
Teletext clock input
A 6.9375MHz clock signal, supplied by the SAA5231
chip, is internally A.C. coupled, clamped and
buffered.
8
ODD/EVEN
Interlaced mode state output
High for even numbered and low for odd-numbered
frames. The value is valid 2µs before the end of
lines 311 and 624.
9
F6
Character display clock signal
The 6MHz clock signal, supplied by the SAA5231
chip is internally A.C. coupled, clamped and buffered.
10
VCS
Video composite
synchronization input signal
11
SAND
Sandcastle
Three level output pulse to the SAA5231 device.
Phase lock, blanking signal, and color burst
components are contained in this signal.
12
TCS/SCS
Input / output composite
synchronization signal
Scan composite input signal (SCS) for the display
synchronization or Text composite sync. (TCS)
output signal to the SAA5231. Both signals are
active low.
13,14,15
RGB
Red, green, blue
16
COR
Contrast reduction
17
BLAN
Blanking signal output
18
Y
Foreground output
19
SCL
Serial clock
20
SDA
Serial data input / output
21
VSS
0 Volt
22-29 *
D0-D7
Parallel data input / output
30-39 *
A0-A9
Address signals
Address selection outputs for 1 of 8 external static
RAM chapters each of 1 kBytes.
Active-low external static RAM output enable control
signal.
Active high VCS input.
Character and background colors active-high
open-drain outputs.
Open-drain active-low output supporting optimal
display of characters in ”mixed mode” operation.
Open-drain active high output for TV-image blanking
in normal and mixed-mode operation.
Open-drain active-high output with foreground
information. Can be used for printer command.
Microprocessor clock input via serial bus.
Open-drain microprocessor serial data input/output
via serial bus.
Ground.
Eight tri-state input/output for data read/write from/to
an external static RAM.
Ten addresses output pins for accessing to
individual Bytes of a 1 kByte chapter stored in an
external Static RAM.
* Pins only activated when 8KBytes of external memory are addressed, otherwise pins OE and WE remain high, and others remain low.
2/25
5345-01.TBL
Pin
STV5345 - STV5345/H - STV5345/T
BLOCK DIAGRAM
TCS/
SAND
SCS
10
11
12
A11 - A12 / 2 - 3
D0 ... D7
*
SCL 19
WE
13 RED
DISPLAY &
CONTROL
INTERFACE
I 2 C BUS
INTERFACE
SDA 20
STV5345
5
CTRL
6
OE
8 PAGES
INTERNAL
MEMORY
ADDRESS
TTD
DATA ACQUISITION
&
DATA PROCESSING
4
CTRL
DATA
7
DATA
TTC
ADDRESS
EXTERNAL
MEMORY
INTERFACE
CLOC K
TIME BASE
9
D0 ... D7 / 22 ... 29
*
*
DATA
F6
A0 ... A10 / 30 ... 40
*
A0 ... A12
1
21
V DD
V SS
18
Y
17
BLAN
16
14 GREEN
15 BLUE
8
5345-02.EPS
VCS
COR ODD/
EVEN
ABSOLUTE MAXIMUM RATINGS
Symbol
VDD
Parameter
Power Supply Range
Value
Unit
-0.3, +6.0
V
INPUT VOLTAGE RANGE :
VI
VCS,SDA,SCL,D0-D7
-0.3, VDD + 0.5
V
VI
TTD,F6,TCS/SCS,TT C
-0.3, +10
V
V
VO
SAND,A0-A12,OE,WE,D0-D7,SDA,ODD/E VEN,R,G,B
-0.3 , VDD
VO
BLAN,COR, Y, TCS/SCS
-0.3 , VDD
V
Tstg
Storage Temperature Range
-20, +125
o
-20, +70
o
TA
Operating Ambient Temperature Range
C
C
5345-02.TBL
OUTPUT VOLTAGE RANGE :
Symbol
Parameter
VDD
Supply Voltage (Pin 1)
IDD
Supply Current (operating mode)
Min
4.5
Typ
Max
Unit
5
5.5
V
15
40
mA
3/25
5345-03.TBL
ELECTRICAL CHARACTERISTICS
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
STV5345 - STV5345/H - STV5345/T
ELECTRICAL CHARACTERISTICS (continued)
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol
Parameter
Min
Typ
Max
Unit
INPUTS
TTD (Pin 6)
CEXT
Ext. Coupling Capacitor
50
nF
VI(p-p)
Input Voltage p-p
2
7
V
tr , tf
Input Rise / Fall Times
10
80
ns
tDS
Input Set-up Time
40
ns
tDH
Input Hold Time
40
ns
II(L)
Input Leakage Current (VI = 0 to VDD)
-10
CI
Input capacitance
+10
µA
7
pF
TTC, F6 (Pins 7,9)
DC Input Voltage
- 0.3
+10
V
VI(p-p)
AC Input Voltage F6
AC Input Voltage TTC
1
1.5
7
7
V
V
± VP
Input Peak Rel. 50 % Duty
0.2
3.5
V
fTTC
TTC Clock Frequency
fF6
F6 Clock Frequency
tr , tf
Clock Rise / Fall Times
10
80
II(L)
Input Leakage Current (VI = 0 to 10V)
-10
+10
µA
CI
Input Capacitance
10
pF
VI
6.9375
MHz
6
MHz
ns
VCS (Pin 10)
VIL
Low Level Input Voltage
0
0.8
V
VIH
High Level Input Voltage
2
VDD
V
tr , tf
Input Rise / Fall Times
500
ns
II(L)
Input Leakage Current (VI = 0 to VDD)
-10
+10
µA
CI
Input Capacitance
7
pF
V
SCL (Pin 19)
VIL
Low Level Input Voltage
0
1.5
3
VIH
High Level Input Voltage
VDD
V
fSCL
SCL Clock Frequency
100
kHz
tr , tf
Input Rise / Fall Times
2
µs
II(L)
Input Leakage Current (VI = 0 to VDD)
CI
Input Capacitance
-10
+10
µA
7
pF
V
INPUT/OUTPUTS
Low Level Input Voltage
0
1.5
VIH
High Level Input Voltage
3
8
V
tr , tf
Input Rise / Fall Times
500
ns
II(L)
Input Leakage Current
(VI = 0 to VDD and output in high impedance state)
-10
+10
µA
CI
Input Capacitance
7
pF
0
0.4
V
2.4
VOL
Low Level Output Voltage (IOL = 0.4mA)
VOH
High Level Output Voltage (-IOH = 0.2mA)
VDD
V
tr , tf
Output Rise / Fall Times between 0.6V and 2.2V
100
ns
Load Capacitance
50
pF
CL
4/25
5345-04.TBL
TCS(output), SCS(input) (Pin12)
VIL
STV5345 - STV5345/H - STV5345/T
ELECTRICAL CHARACTERISTICS (continued)
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol
Parameter
Min
Typ
Max
Unit
V
INPUT/OUTPUTS (continued)
SDA (Pin 20)
VIL
Low Level Input Voltage
0
1.5
3
VDD
V
2
µs
+10
µA
7
pF
VIH
High Level Input Voltage
tr , tf
Input Rise / Fall Times
II(L)
Input Leakage Current (VI = 0 to VDD and output in high impedance state)
CI
Input Capacitance
VOL
tf
CL
Low Level Output Voltage (IOL = 3mA)
-10
0.5
V
Output Fall Time between 3.0V and 1.0V
0
200
ns
Load Capacitance
400
pF
D0-D7 (Pins 22-29)
VIL
Low Level Input Voltage
0
0.8
V
VIH
High Level Input Voltage
2
VDD
V
II(L)
Input Leakage Current (VI = 0 to VDD and output in high impedance state)
-10
+10
µA
CI
Input Capacitance
7
pF
0
0.4
V
2.4
VDD
V
VOL
Low Level Output Voltage (IOL = 1.6mA)
VOH
High Level Output Voltage (-I OH = 0.2mA)
tr , tf
Output Rise / Fall Times between 0.6V and 2.2V
50
ns
CL
Load Capacitance
120
pF
0
0.4
V
2.4
VDD
V
OUTPUTS
A0-A12, OE, WE (Pins 30-40,2,3,4,5,)
VOL
Low Level Output Voltage (IOL = 1.6mA)
VOH
High Level Output Voltage (-I OH = 0.2mA)
tr , tf
Output Rise / Fall Times between 0.6V and 2.2V
50
ns
Load Capacitance
120
pF
0
0.4
V
2.4
VDD
V
CL
ODD/EVEN (Pin 8)
VOL
Low Level Output Voltage (IOL = 0.4mA)
VOH
High Level Output Voltage (-I OH = 0.2mA)
tr , tf
Output Rise / Fall Times between 0.6V and 2.2V
100
ns
Load Capacitance
50
pF
CL
SAND (Pin 11)
Low Level Output Voltage (IOL = 0.2mA)
VOI
Middle Level Output Voltage (IOL = ± 10 µA)
VOH
High Level Output Voltage (-IOH = 0 to 10µA)
0
-
0.25
V
1.1
-
2.9
V
4
VDD
V
tr1
tr2
Output Rise Time :
VOL to VOI from 0.4 to 1.1V
VOI to VOH from 2.9 to 4.0V
-
-
400
200
tf
Output Fall Time V OH to VOl from 4.0 to 0.4V
-
-
50
ns
Load Capacitance
-
-
30
pF
CL
ns
5/25
5345-05.TBL
VOL
STV5345 - STV5345/H - STV5345/T
ELECTRICAL CHARACTERISTICS (continued)
VDD = 5V, VSS = 0V, TA = - 20 to + 70oC
Symbol
Parameter
Min
Typ
Max
Low Level Output Voltage :
IOL = 2mA
IOL = 5mA
0
0
-
0.4
1
Pull-up Voltage (with R = 1kΩ to VDD)
-
-
VDD
Unit
OUTPUTS (continued)
R, G, B, COR, BLAN, Y (Pins 13-18)
VOL
VPU
V
V
Output Fall Time from 4.5 to 1.5V (with R = 1kΩ to VDD)
-
-
20
ns
tSK
Skew Delay on Falling Edges
(at 3V with R = 1kΩ connected to VDD)
-
-
20
ns
CL
Load Capacitance
-
-
25
pF
ILO
Output Leakage Current (V PU = 0 to VDD output off)
-
-
20
µA
4
-
-
µs
tf
TIMING
SERIAL BUS (referred to VIH = 3V, VIL = 1.5V) (see Fig. 6)
tLOW
Low Period Clock
tHIGH
High Period Clock
4
-
-
µs
tSU , DAT
Data Set-up Time
250
-
-
ns
170
-
-
ns
4
-
-
µs
tHD , DAT
Data Hold Time
tSU , sTO
Stop Set-up Time from Clock High
tBUF
Start Set-up Time Following a Stop
4
-
-
µs
Start Hold Time
4
-
-
µs
Start Set-up Time Following Clock Low to High Transition
4
-
-
µs
tHD , STA
tSU , STA
tCY
Cycle Time
-
500
-
ns
tOE
Adress Change to OE Low
60
-
-
ns
tADDR
Address Active Time
450
500
-
ns
tOEW
OE Pulse Duration
320
-
-
ns
tACC
Access Time from OE to Data Valid
-
-
200
ns
tDH
Data Hold Time from OE High or Address Change
0
-
-
ns
tWE
Address Change to WE Low
40
-
-
ns
WE Pulse Duration
200
-
-
ns
tDS
Data Set-up Time to WE High
100
-
-
ns
tDHWE
Data Hold Time from WE High
20
-
-
ns
Write Recovery Time
25
-
-
ns
tWEW
tWR
6/25
5345-06.TBL
MEMORY INTERFACE referred to VIL = 1.5V (see Fig. 7)
STV5345 - STV5345/H - STV5345/T
Figure 1 : F6, TTC, TTD Input Internal Connections
F6
character display clock input
to timing chain
9
50%
duty cycle
level
V
TTC
teletex t clock input
to data acquistion circuit
7
VP
VI(p-p)
VP
teletext data input
to data acquisition circuit
C EXT
0
clamping pulses from timing circuit
from time 4µs to 8µs of each television
line to maintain correct D.C. level
following external A.C. coupling
t
shaded regions equal in area
F6, TTC, TTD INPUT CIRCUITRY
INPUT WAVEFORM PARAMETERS
5345-03.EPS
6
TTD
Figure 2 : Teletext Data Input Timing
t CY
90%
TTC
90%
10%
10%
tr
tf
40ns min. 40ns min.
80ns max.
80ns max.
Data Stable
Data Stable
t DS
TTD
data may change
t DH
data may change
5345-04.EPS
144ns typ.
data may change
Data Stable : 1 if ≥ 2V , 0 if ≤ 0.8V
Figure 3 : Synchronization Timing
continuous internal 1MHz clock
F1
64
0
TCS
4.67
Phase lock
SAND
Phase lock off
8.5
33.5
5345-05.EPS
1.5
All timings in µs
7/25
STV5345 - STV5345/H - STV5345/T
Figure 4 : Composite Sync. Waveforms
LSP
0
4.66
64
EP
0 2.33
32 34.33
64
BP
0
27.33 32
59.33 64
All timings in µs
TCS
(interlaced)
621
(308)
622
(309)
623
(310)
624
(311)
625
(312)
1
309
310
311
312
313
314
(1)
308
309
311
312
1
2
3
4
5
6
316
(3)
317
(4)
318
(5)
319
(6)
3
4
5
6
TCS
(interlaced)
315
(2)
310
2
The number positions indicate the end of lines.
The Teletext composite synchronization signal (TCS), whether interlacing is present or not, comprise
three components.
a) the line-synchronization pulses (LSP).
b) the equalization pulses (EP)
c) the frame-synchronization pulses (BP).
The timing reference is specified by the descending edge of the signal LSP, with a tolerance spread of ± 100ns.
5345-06.EPS
TCS
(non-interlaced)
Figure 5 : Display Output Timing
A) LINE RATE
LSP (TCS)
0
4.66
64
40µs
R.G.B.Y (1)
display period
0
16.67
B) FIELD RATE
lines 42 to 291 inclusive
(and 355 to 604 inclusive interlaced)
0
41
(1) Also BLAN in charac ter and box bla nking
291 312
Line numbers
Horizontal directio n(line ) - Vertical direc tion (frame)
5345-07.EPS
display period
R.G.B.Y (1)
8/25
56.67
All timings in µs
STV5345 - STV5345/H - STV5345/T
Figure 6 : Serial Bus Timing
SDA
t BUF
t LOW
tf
SCL
t HD,STA
tr
t HD,DAT
t HIGH
t SU,DAT
SDA
t SU,STA
5345-08.EPS
t SU,STO
VIH = 3V , VIL = 1.5V
Figure 7 : Memory Interface Timing
A) READ
t CY
ADDRESS
A0 - A12
valid
t ADDR
t OE
OE
t OEW
t ACC
t DH
DATA
FROM
RAM
valid data output
B) WRITE
t CY
ADDRESS
A0 - A12
valid
t WR
t WE
WE
t WEW
DATA
TO
RAM
t DHWE
5345-09.EPS
t DS
valid data output
9/25
10/25
5345-10.EPS
VS or
SAA5231
Pin 28
Voltage
Sensor
70µA
Phase
Detector
6MHz
Oscillator
28
25
22
17
DATA SLICER
Sync. Output
1.2kΩ
1
Sync.
Separator
Switch in this position
TCS ON
Teletext
Data
and
Clock
Separator
27
CVBS
F6
9
12
10
TCS/SCS
Scan
Composite
Sync.
VCS
Video
Composite
Sync.
15.625kHz
11
SAND
6MHz
TCS
ENABLE
TCS
Outputs
Buffer
Vertical
Sync.
Integrator
Signal
Quality
Detector
6
I 2 C-Register 1
TCS ON Mode
(D2 = 1) (D1/D0)
Composite
Sync.
Generator
64
VIDEOTEXT CONTROLLER
STV5345
DISPLAY
FIELD SYNC.
ENABLE
ACQUISITION
SYSTEM
CLOCK
ACQUISITION
FIELD SYNC.
LINE
SYNC
STV5345 - STV5345/H - STV5345/T
Figure 8 : Master Synchronization Mode
5345-11.EPS
Videotext
Data
and
Clock
Separator
27
CVBS
18
Phase
Detector
6MHz
Oscillator
20
28
25
22
17
SAA5231
DATA SLICER
Not connected for
External synchronization
1
Determines F6 and line sync.
Sync.
Separator
C
L
F6
9
SCS
TCS
Composite
Sync.
Generator
64
I 2 C-Register 1
DISABLE TCS OFF EXT-SYNC
(D2=0)
(D1=D0=1)
TCS
Outputs
Buffer
Sync.
Integrator
Signal
Quality
Detector
6
SCS
Field
Sync.
I C - Register 1, Bit D2=0 to disable TCS output buffer
and D1=D0=1 to enable external sync.
Acquisition only works when external sync. signal is
phase synchronous with CBVS input.
2
12
TCS/SCS
Scan
Composite
Sync.
Video
Composite
Sync.
10
VCS
15.625kHz
11
SAND
6MHz
VIDEOTEXT CONTROLLER
STV5345
DISPLAY
FIELD SYNC.
ENABLE
ACQUISITION
INTERNAL
CLOCK
FIELD
SYNC.
LINE
SYNC.
STV5345 - STV5345/H - STV5345/T
Figure 9 : Slave Synchronization Mode
11/25
5345-12.EPS
SDA
SCL
TS
+5V
22µH
10kΩ
0.1µF
470Ω
470Ω
21
1
20
19
10kΩ
7 10
6 12 11 9
3
STV5345
5
6
8
9
1
24
8 16 18
6
5
4
MK48H64
8K x 8 SRAM
(for 16 pages applications)
7
10µF
+5V
26
28
3 25 24 21 23 2
5
8
3
4 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 2
20 27 22 11 12 13 15 16 17 18 19 10 9
14
4
10
26
1
47nF 47nF 15pF 1nF 470pF 22nF 270pF100pF 220pF 68nF
560pF
1k Ω
19
7
470Ω
7
5
13
15
14
13
17
27
TEA2014A
8
47µF
10µF
10Ω
WE
+12V 10nF
21
SAA5231
11
13.875MHz
+12V
OE
BC558B
2
D5
15 28 22 17 14 25
D6
16
18
A0
20
D7
23
A1
12
7 - 36
15pF
A2
10pF
390Ω
A3
+12V
D1
6MHz
A4
68kΩ
A5
27pF
A6
15µH
A7
23nF
D3
820Ω
A8
4.7µF
D0
CS
A9
A11
22µH
D2
VSS
A10
A12
12/25
D4
10kΩ
1
3
2
1kΩ
10µF
1k Ω
1N4148
3.7kΩ
2.2µF
6
1kΩ
1kΩ
22µF
BC548B
BC548B
BC548B
GND
3
1.2kΩ
6.8kΩ
L7805
2 V0
100Ω
150pF
BC548B
2.7kΩ
+5V
1kΩ
4.7kΩ
82Ω
82Ω
82Ω
82Ω
V1 1
+12V
GND
B
G
R
BLK
GND
+12V
VIDEO
SYNC
STV5345 - STV5345/H - STV5345/T
APPLICATION DIAGRAM
STV5345 - STV5345/H - STV5345/T
APPLICATION NOTES
ORGANIZATION OF A PAGE-MEMORY
white ; when it is ”green” the operational state
corresponds to ”search mode” and the header
appears green. The following twenty-four characters give the header of the requested page when
the system is in search mode. The last eight characters display the time of day.
Row number twenty-four is used by the microprocessor for the display of information.
Row twenty-five comprises ten bytes of control
data concerning the received page (see Table 1)
and fourteen free bytes which can be used by the
microprocessor.
The organization of a page-memory is shown in
Figure 10.
The STV5345 chip provides a display format of 25
rows of 40 characters per row.
The organizationis as follows :
Row zero contains the page header.
The first seven characters (0 - 6) are used for
messages regarding the operational status.
The eighth character is an alphanumeric control
character either ”white” or ”green” defining the
”search” status of the page. When it is ”white” the
operational state is normal and the header appears
PAGE MEMORY ORGANISATION
Figure 10
7 Status
Characters
Fixed characters
Alphanumerics white
for normal,
green on searc h
7
24 characters from page header
rolling on page search
1
8 scrolling
time characters
ROW
8
0
24
1
2
3
4
5
6
7
8
9
10
11
MAIN PAGE DISPLAY AREA
12
13
14
15
16
17
18
19
20
21
22
23
10
14
10 bytes for received
page information
14 bytes free
for use by µC
24
25
5345-13.EPS
this row always free for status
13/25
STV5345 - STV5345/H - STV5345/T
GHOST ROW STORAGE ORGANIZATION
Designation
Code
0
0 0
0
0
0 0
1
0
0 1
0
0
0 1
1
0
1 0
0
0
1 0
1
0
1 1
0
0
1 1
1
1
0 0
0
1
0 0
1
1
0 1
0
1
0 1
1
1
1 0
0
1
1 0
1
1
1 1
0
0
0 1
0
0
0 0
0
0
0 0
1
0
0 1
0
0
0 1
1
0
X
0
X
0
X
Row (Packet)
Number
X / 26
Function
Enhanced display facilities
Page related data
stored in chapter
corresponding to
level 1 data,
i.e. For 0 goes in 4
” 1 ” ” 5
” 2 ” ” 6
” 3 ” ” 7
X / 28
Page related character set
X / 27
Linked pages
X / 24
X / 25
X / 28
8 / 30
0
X
Page extension
Page extension
Magazine related character set
Broadcasting service data packet
Not used
Not used
Stored in chapter 4
only
5345-07.TBL
Row Address
of Stored Data
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
D0
PU0
PT0
MU0
MT0
HU0
HT0
C7
C11
MAG0
0
D1
PU1
PT1
MU1
MT1
HU1
HT1
C8
C12
MAG1
0
D2
PU2
PT2
MU2
MT2
HU2
C5
C9
C13
MAG2
0
D3
PU3
PT3
MU3
C4
HU3
C6
C10
C14
0
0
D4
HAM
HAM
HAM
HAM
HAM
HAM
HAM
HAM
FOUND
0
D5
0
0
0
0
0
0
0
0
0
PBLF
D6
0
0
0
0
0
0
0
0
0
0
D7
0
0
0
0
0
0
0
0
0
0
COLUMN
0
1
2
3
4
5
6
7
8
9
Page number : - MAG = magazine, PU = page units, PT = page tens.
Page sub-code : - MU = minutes units, MT = minutes tens, HU = hours units, HT = hours tens.
PBLF = page being looked for, FOUND = low for page found, HAM = hamming error in byte, C4-14 = control bits.
14/25
5345-08.TBL
Table 1 : Row 25 received page control data format
STV5345 - STV5345/H - STV5345/T
REGISTER MAP (see Table 2)
Registers R0 to R10 and R12 are write only whilst
R11A is a read/write and R11B is a read only
register respect to the microprocessor.
The automatic succession on a byte basis is indicated by the arrows in Table 2.
In the normal operating mode TA, TB and TC
should be set to logic level 0.
After power-up the contents of the registers are as
follows : all bits in registers R0 to R12 are cleared
to zero with the exception of bits D0 and D1 in
registers R5 and R6 which are set to logical one.
After power-up all the memory bytes are preset to
hexadecimalvalue 20 H (space) with the exception
of the byte corresponding to row 0 of column 7 of
chapter 0 which is set to the value corresponding
to ”alpha white” hexadecimal value 07 H.
D7
D6
D5
D4
D3
D2
D1
D0
*
*
*
*
*
EVEN
OFF
TC
SEL11B
TA
7 + P/
8 BIT
ACQ.
ON/OFF
GHOST
ROW
ENABLE
DEW/
FULL
FIELD
TCS
ON
T1
T0
BLOCK
SELECT
A3
BANK
SELECT
A2
ACQ.
CCT
A1
ACQ.
CCT
A0
TB
START
COLUMN
SC2
START
START
COLUMN COLUMN
SC0
SC1
*
*
*
PRD4
PRD3
PRD2
PRD1
*
*
*
*
A3
A2
A1
A0
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
BKGND
OUT
BKGND
IN
COR
OUT
COR
IN
TEXT
OUT
TEXT
IN
PON
OUT
PON
IN
STATUS
ROW
BTM/TOP
CURSOR
ON
CONCEAL/
REVEAL
TOP/
BOTTOM
SINGLE/
DOUBLE
HEIGHT
BOX ON
24
BOX ON
1-23
BOX ON
0
*
*
*
A3
CLEAR
MEM.
A2
A1
A0
*
*
*
R4
R3
R2
R1
R0
*
*
C5
C4
C3
C2
C1
C0
D7
(R/W)
D6
(R/W)
D5
(R/W)
D4
(R/W)
D3
(R/W)
D2
(R/W)
D1
(R/W)
D0
(R/W)
60Hz
0
0
0
0
0
0
VCS
signal
quality
*
*
*
EROD
A1
A0
*
*
PRD0
↵
↵
↵
↵
↵
↵
↵
↵
R0
Mode 0
R1
Mode 1
R2
Page request adress
R3
Page request data
R4
Display chapter
R5
Display control (normal)
R6
Display control
(newsflash / subtitle)
R7
Display mode
R8
Active chapter
R9
Active row
R10
Active column
R11A
Active data
R11B
Status
R12
Page request address
5345-09.TBL
Table 2 : Register specification
* Reserved register bits : must be set to 0
REFRESH ON DISPLAY FUNCTION
This function allows independently to fill the memory using 3 acquisition circuits when the 4th one
refreshes the displayed page.
When EROD (D5 of Reg. 12) is 0, refresh on display
function is not active. Four teletext pages are filled
into memory corresponding to addresses of acquisition registers.
Two blocks of 8 pages are selected with A3 (D7of
Reg. 2)
Upper or lower bank of 4 pages is selected with A2
(D6 of Reg. 2).
Acquisition circuits are selected with A1/A0 (D5/D4
of Reg. 2). This 2 bits also determine the 1KByte of
RAM (the chapter) allocated to each acquisition
circuit.
When EROD = 1, refresh on display function is
active.
3 acquisition circuits store pages as described
above. The 4th one stores data into the current
displayed chapter. The chapter is selected with
addresses A3/A2/A1/A0 (D3/D2/D1/D0 of Reg. 4).
Notice that A1/A0 (D1/D0 of Reg. 4) give the circuit
number to be used to refresh this displayed chapter. That means A1/A0of refresh ondisplay function
(D4/D3 of Reg. 12) have to be written identical to
A1/A0 (D1/D0 of Reg. 4), as A2 of acquisition circuit
(D6 of Reg. 2) has to be identical to A2 of displayed
chapter (D2 of Reg. 4).
15/25
STV5345 - STV5345/H - STV5345/T
REGISTER FUNCTIONS
Register
Function
R0
Address
00H
R11 adressing
and pin functions
control
Bit(s)
Description
SEL 11B (D0)
TC (D1)
EVEN OFF (D2)
T1
0
0
1
1
T0
0
1
0
1
TCS ON (D2)
R1
Address
01H
Operating mode
controls
Selection of register 11B (D0 = 1) or 11A(D0 = 0)
Test bit, must be cleared in the normal working mode
DEW / FULLFIELD
(D3)
Control of ODD/EVEN pin : EVEN signal output (D2 = 0) or
grounded (D2 = 1)
312/313 line MIX - mode with interlace
312/313 line TEXT - mode without interlace
312/312 line Terminal mode without interlace
External synchronization TCS/SCS is an input
D2 = 1, TCS output on Pin TCS/SCS
D2 = 0, SCS input on Pin TCS/SCS
Selection of field flyback mode or full channel mode
(D3 = 1)
GHOST ROW
ENABLE (D4)
Selection of ghost row mode (D4 = 1)
ACQUISITION
ON / OFF (D5)
Control of acquisition operation (D5 = 0 enables acquisition)
7 bits + parity or 8
Selection of received data format either 7 bits with parity
bits without parity (D6) (D6 = 0) or 8 bits without parity (D6 = 1).
TB (D3)
R2
Address
02H
Addressing
information for
a page request
A0, A1 (D4, D5)
Test bit, must be cleared in the normal working mode
Address the first column of the on chip page request RAM
to be written.
Test bit, must be cleared in the normal working mode.
Address a group of four consecutive pages currently used
for data acquisition;
A2 (D6)
Address of one of the two groups of four pages for
acquisition in normal mode.
A3 (D7)
Block select: D7 = 0 internal memory, D7 = 1 external
memory
R3
Address
03H
Data relative to
the requested
page (see Table 3)
PRD0 - PRD4
(D0 - D4)
Written data in the page request RAM, starting with the
columns addressed by SC0,SC1,SC2.
R4
Address
04H
Selection of one
of 16 pages to
display
A0, ... A3
(D0, ... D3)
These 4 bits correspond to the logical states of the 4
address lines (A10, ... A13) during memory read cycles.
R5
Address
05H
R6
Address
06H
Display control for
normal operation
Display control for
news-flash
subtitle generation
PON (D0, D1)
Picture on (IN: D0, OUT: D1)
TEXT (D2, D3)
Text on (IN: D2, OUT: D3)
COR (D4, D5)
Contrast reduction on (IN: D4, OUT: D5)
BKGND (D6, D7)
Background colour on (IN: D6, OUT: D7)
IN / OUT
Enable inside/outside the box
See R5
See R5
BOX ON 0, 1-23,24
(D0, D1, D2)
R7
Address
07H
16/25
Display mode
The ”boxing” function is enabled on row 0,1-23 and 24 by
D0, D1 and D2 set to one.
TOP/BOTTOM
Single/Double Height
(D4/D3)
X0 = Normal
01 = double height Rows 0 to 11
11 = double height Rows 12 to 23
Conceal/Reveal (D5)
Conceal Reveal Function
Cursor ON/OFF (D6)
Cursor position given by row/column value of R9/R10
STATUS ROW
BTM / TOP (D7)
The 25th row is displayed before the ”Main text Area”
(lines 0-23) or after (D7 = 0).
5345-10.TBL
TA (D7)
SC0, SC1, SC2
(D0, D1, D2)
STV5345 - STV5345/H - STV5345/T
REGISTER FUNCTIONS (continued)
Function
Bit(s)
Description
Active chapter address (R8), active row address (R9), active column address (R10).
Data contained in R11A read (written) from (to) memory by microprocessor via I2C.
VCS Signal Quality
(D0)
60Hz (D7)
R11B
Address
0BH*
Status
R12
Address
0CH
Page request
address
Good VCS quality signal detected (D0 = 1) or disturbed
(D0 = 0)
VCS received with 60Hz frequency (D7 = 1) or 50Hz (D7
= 0). Only valid when VCS is good (D0 = 1)
A0, A1 addresses of displayed page to refresh when using
refresh on display function
Enable refresh on displayed page function when = 1
normal acquisition storage if EROD = 0
A0, A1 (D3, D4)
EROD (D5)
5345-11.TBL
Register
R8 to R11A
Address
08H to 0BH*
* Reading of R11A or R11B is determined by register 0, bit D0. Nevertheless, write operation is always performed on R11A register.
START
COLUMN
PRD4
PRD3
PRD2
PRD1
PRD0
0
Do care magazine
HOLD
MAG2
MAG1
MAG0
1
Do care page tens
PT3
PT2
PT1
PT0
2
Do care page units
PU3
PU2
PU1
PU0
3
Do care hours tens
X
X
HT1
HT0
4
Do care hours units
HU3
HU2
HU1
HU0
5
Do care minutes tens
X
MT2
MT1
MT0
6
Do care minutes units
MU3
MU2
MU1
MU0
5345-12.TBL
Table 3 : Register R3
The abbreviations have the same significance as in Table 1 with the exception of the ”DO CARE” entries. It is only
when this bit is ”1” that the corresponding digit is taken into consideration on page request. For example, a page
defined as ”normal” or one defined as ”timed” may be selected.
If ”HOLD” is low the page is held. The addressing of successive bytes via the I2C bus is automatic.
CHARACTER SETS
The complete character set with 8-bit decoding is
given in Tables 4a, 4b and 4c.
Characters in columns 0 and 1 are normally displayed as blanks. Black dots represent the character shape whereas white dots represent the
background.
Each character can be identified by a pair of corre-
sponding row and column integers : for example
the character ”3” may be indicated by 3/3.
A rectangle may be represented as follows :
The characters 8/6, 8/7, 9/5, 9/7 are used as special characters, always in conjunction with 8/5.
The 13 national characters are placed in columns
with bit 8 = 0.
17/25
*
**
18/25
Case using C12 C13 C14 = 001 (German Set)
These control characters are reserved for compatibility with other data codes.
These control characters are presumed before each row begins
5345-14.EPS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
B
I
T
S
b4 b 3 b 2 b 1
b6
b5
b8
b7
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
cyan
cyan
SI
*
*
graphics
release
graphics
hold
height
SO
new
background
double
black
ESC
graphics
separated
graphics
continuous
display
background
**
**
**
conceal
white
1
normal
height
start box
end box
steady
flash
white
alphanumerics
graphics
graphics
alphanumerics
**
graphics
magenta
blue
blue
magenta
graphics
alphanumerics
alphanumerics
yellow
yellow
alphanumerics
green
red
graphics
red
graphics
graphics
alphanumerics
green
black
alphanumerics
graphics
0
black
0
0
alphanumerics
0
0
1
0
2
column
10
r
o
w
0
**
**
**
*
**
2
1
0 or 1
0
0
0
1
2a
0
0
3
1
0 or 1
0
0
0
1
3a
0
0
0
1
4
0
0
0
1
5
0
1
6
0
1
1
6a
0
7
0
1
1
7a
1
1
0
8
0
0
1
0
9
0
1
1
0
12
1
0
1
0
13
1
1
1
1
14
1
0
1
1
15
1
1
STV5345 - STV5345/H - STV5345/T
Table 4a : Complete character set (with 8 bit codes) - West European Languages (STV5345)
*
**
Case using C12 C13 C14 = 111 (Rumanian Set)
These control characters are reserved for compatibility with other data codes.
These control characters are presumed before each row begins
5345-15.EPS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
b 4 b3 b2 b 1
B
I
T
S
b8
b7
b6
b5
15
14
13
12
11
graphics
blue
graphics
magenta
graphics
cyan
graphics
white
alphanumerics
blue
alphanumerics
magenta
alphanumerics
cyan
**
alphanumerics
white
SI
SO
double
height
normal
height
start box
end box
steady
*
*
**
**
**
graphics
yellow
alphanume rics
yellow
*
**
release
graphics
hold
graphics
**
**
new
background
**
black
background
ESC
separated
graphics
continuous
graphics
conceal
display
graphics
green
alphanumerics
green
flash
graphics
red
1
alphanumerics
red
0
graphics
black
0
0
alphanumerics
black
0
0
1
0
2
column
10
9
8
7
6
5
4
3
2
1
0
r
o
w
0
2
0 or 1
0
1
0
0
1
2a
0
0
3
0 or 1
0
1
0
0
1
3a
0
0
0
1
4
0
0
0
1
5
0
1
6
0
1
1
6a
0
7
0
1
1
7a
1
1
0
8
0
0
1
0
9
0
1
1
0
12
1
0
1
0
13
1
1
1
1
14
1
0
1
1
15
1
1
STV5345 - STV5345/H - STV5345/T
Table 4b : Complete character set (with 8 bit codes) - East European Languages (STV5345/H)
19/25
*
**
20/25
Case using C12 C13 C14 = 001 (German Set)
These control characters are reserved for compatibility with other data codes.
These control characters are presumed before each row begins
5345-16.EPS
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
B
I
T
S
b4 b3 b 2 b1
b8
b7
b6
b5
9
8
7
6
5
4
3
2
1
0
15
14
13
12
11
cyan
cyan
SI
*
*
graphics
release
graphics
hold
height
SO
new
background
double
black
ESC
graphics
separated
graphics
continuous
display
background
**
**
**
conceal
white
1
normal
height
start box
end box
steady
flash
white
alphanumerics
graphics
graphics
alphanumerics
**
graphics
magenta
blue
blue
magenta
graphics
alphanumerics
alphanumerics
yellow
yellow
graphics
alphanumerics
green
red
red
graphics
graphics
alphanumerics
alphanumerics
black
green
graphics
0
black
0
0
alphanumerics
0
0
1
0
2
column
10
r
o
w
0
**
**
**
*
**
0
2
1
0 or 1
0
0
1
2a
0
0
0
3
1
0 or 1
0
0
1
3a
0
0
0
1
4
0
0
0
1
5
0
1
6
0
1
1
6a
0
7
0
1
1
7a
1
1
0
8
0
0
1
0
9
0
1
1
0
12
1
0
1
0
13
1
1
1
1
14
1
0
1
1
15
1
1
STV5345 - STV5345/H - STV5345/T
Table 4c : Complete character set (with 8 bit codes) - Turkish European Languages (STV5345/T)
STV5345 - STV5345/H - STV5345/T
The basic set of the 96 characters is shown in
Table 5.The location of the 13 national characters
are shown in Table 5 whilst full national character
sets are depicted in Tables 6, 7 and 8.
Table 5 : Basic character set.
3/0
4/0
2/1
3/1
2/2
National
National
5/0
6/0
4/1
5/1
6/1
7/1
3/2
4/2
5/2
6/2
7/2
3/3
4/3
5/3
6/3
7/3
3/4
4/4
5/4
6/4
7/4
2/5
3/5
4/5
5/5
6/5
7/5
2/6
3/6
4/6
5/6
6/6
7/6
2/7
3/7
4/7
5/7
6/7
7/7
2/8
3/8
4/8
5/8
6/8
7/8
2/9
3/9
4/9
5/9
6/9
7/9
2/10
3/10
4/10
5/10
6/10
7/10
2/11
3/11
4/11
5/11
6/11
7/11
2/12
3/12
4/12
5/12
6/12
7/12
2/13
3/13
4/13
5/13
6/13
7/13
2/14
3/14
4/14
5/14
6/14
7/14
2/15
3/15
4/15
5/15
6/15
7/15
2/3
2/4
National
Character
National
Character
Charact er
National
Character
National
Character
National
Character
National
Character
National
Character
Character
7/0
National
Character
National
Character
National
Character
National
Character
5345-17.EPS
2/0
21/25
STV5345 - STV5345/H - STV5345/T
Character Set for STV5345 West
European Languages
Table 7 :
7/13
7/13
7/12
7/12
22/25
Where PHCB are the Page Header Control bits. Other
Combinations de fault to English. Only the ab ove cha racters
change with the PHCB. All others characters in the basic set are
shown in Table 5.
1
RUMANIAM
1
0
1
1
CZECHOSLOVAK
Where PHCB are the Page Header Control bits. Other
Combinations default to German. Only the above cha racters
change with the PHCB. All others characters in the basic set are
shown in Table 5.
5345-19.EPS
1
1
0
1
SERBO-CROAT
0
1
0
SWEDISH
1
0
0
GERMAN
0
0
0
POLISH
C14
C13
PHCB (1)
LANGUAGE
5345-18.EPS
Note 1 :
C12
1
1
SPANISH
0
0
1
FRENCH
0
1
0
ITALIAN
1
0
0
SWEDISH
1
1
0
GERMAN
0
0
ENGLISH
0
0
2/3
2/4
4/0
5/11
5/12
5/13
5/14
5/15
CHARACTER POSITION (COLUMN/ROW)
6/0
7/11
7/11
6/0
5/13
5/14
5/15
CHARACTER POSITION (COLUMN/ROW)
5/12
5/11
4/0
2/4
2/3
C14
C13
PHCB (1)
C12
LANGUAGE
Note 1 :
Character Set for STV5345/H East
European Languages
7/14
7/14
Table 6 :
STV5345 - STV5345/H - STV5345/T
Character Set for STV5345/T Turkish European Languages
Note 1 :
1
5345-20.EPS
1
SPANISH
0
0
1
FRENCH
0
1
0
ITALIAN
1
0
1
TURKISH
1
1
0
GERMAN
0
0
0
0
ENGLISH
LANGUAGE
C12
C13
PHCB (1)
C14
2/3
2/4
4/0
5/11
5/12
5/13
5/14
5/15
CHARACTER POSITION (COLUMN/ROW)
6/0
7/11
7/12
7/13
7/14
Table 8 :
Where PHCB are the Page Header Control bits. Other Combinations de fault to Turkish. Only the above characters change with the PHCB. All oth ers
characters in the basic set are shown in Table 5.
23/25
STV5345 - STV5345/H - STV5345/T
Figure 11 : Character Format
Contiguous
graphics character
7/6
Alphanumerics
character
2/13
Separated
graphics character
7/6
Alphanumerics or
blast-through
alphanumerics
character 4/8
Separated
graphics character
7/15
=
24/25
Background
Color
Alphanumerics
character
7/15
Contiguous
graphics character
7/15
=
Display
Color
5345-21.EPS
Alphanumerics and
Graphics ’space’
characte r
2/0
STV5345 - STV5345/H - STV5345/T
I
L
a1
PACKAGE MECHANICAL DATA
40 PINS - PLASTIC DIP
b1
b
e
b2
E
e3
D
21
1
20
a1
b
b1
b2
D
E
e
e3
F
i
L
Min.
Millimeters
Typ.
0.63
0.45
0.23
Max.
Min.
0.31
0.009
1.27
Max.
0.012
0.050
52.58
16.68
15.2
Inches
Typ.
0.025
0.018
2.070
0.657
0.598
2.54
48.26
0.100
1.900
14.1
4.445
3.3
0.555
DIP40.TBL
Dimensions
PM-DIP40.EPS
F
40
0.175
0.130
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility
for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result
from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics.
Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all
information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life
support devices or systems without express written approval of SGS-THOMSON Microelectronics.
 1994 SGS-THOMSON Microelectronics - All Rights Reserved
Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips
I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to
the I2C Standard Specifications as defined by Philips.
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25/25