T6LE2 TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic T6LE2 Gate Driver for TFT LCD Panels The T6LE2 is a 300 / 263 / 256-channel output gate driver for TFT LCD panels. Unit: mm T6LE2 Features • LCD drive output pins : Switchable 300 / 263 / 256 pins • LCD drive voltage : max 43.5 V • Data transfer method : Bidirectional shift register • Operating temperature : −20 to 75°C • Package : COF User Area Pitch IN OUT Please contact Toshiba or a distributor for the latest COF specification and product line-up. COF (Chip On Film) Application Module for PC monitors, LCDs for TV and Module for amusement 1 2006-09-20 T6LE2 Block Diagram DO/I DI/O CPVL/R Shift register U/D MODE1 Input circuit unit MODE2 OE L/R Control circuit unit XDON VGG Output circuit unit VEE VDD VSS G1 2 G2 G3 G298 G299 G300 2006-09-20 T6LE2 Pin Assignment G300 G299 G298 327 326 325 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 T6LE2 (chip top view) G3 G2 G1 30 29 28 VGG VEE VDD VSS VDD DO/I (VSS) MODE2 (VDD) OE R CPVR VSS XDON (VDD) U/D (VSS) CPVL OE L (VSS) (VDD) MODE1 (VSS) DI/O VSS VDD VEE VGG The above diagram shows the device’s pin configuration only and does not necessarily correspond to the pad layout on the chip. Please contact Toshiba or our distributors for the latest COF specification. 3 2006-09-20 T6LE2 Pin Function Pin Name I/O Function Vertical shift clock, output enable input / output select pin These pins are used to input and output shift data. These pins are switched between input and output by setting the U/D pin as shown below. DI/O DO/I I/O U/D DI/O DO/I H Input Output L Output Input • When set for input This pin is used to feed data into the shift registers at the first stage of the LCD driver. The data is latched into the shift registers at the rising edge of CPVL/R. • When set for output When two or more T6LE2 are cascaded, this pin outputs the data to be fed into the next stage. This data changes state synchronously with the falling edge of CPVL/R. Transfer direction select / vertical shift clock, output enable input / output select pin This pin specifies the direction in which data is transferred through the shift registers. The shift register data is shifted synchronously with the rising edge of CPV as follows: When U/D is high, data is shifted in the direction U/D = “H”: G1 → G2 → G3 → G4 → ··· → G300 When U / D is low, the direction is reversed to give U/D = “L”: G300 → G299 → G298 → G297 → ··· → G1 This pin is used to perform input / output settings for CPVL, CPVR, OE L, OE R. U/DL U/DR I/O U/D L H Input Output CPVR CPVL OE R OE L CPVL CPVR OE L OE R The voltage applied to this pin must be a DC-level voltage that is either high (VDD) or low (VSS). CPVL CPVR OE L OE R I/O I/O Vertical shift clock • When set for input: This is the shift clock for the shift registers. Data is shifted through the shift registers synchronously with the rising edge of CPVL/R. • When set for output: The signal input to CPVL/R is output to CPVR/L asynchronous to other signals. These pins are switched between input and output by setting the U/D pin as below. U/D CPVL CPVR H Input Output L Output Input Output enable pin When set for input: These signals control the data appearing at the LCD panel drive pins (G1 through G300). OE L/R doesn’t synchronize with the CPVL/R. When OE L/R is low : outputs shift data and data contents. When OE L/R is high : controls the LCD panel drive output to VEE level. When set for output: The signal input to OE L/R is output to OE R/L. These pins are switched between input and output by setting the U/D pin as below. U/D OE L OE R H Input Output L Output Input 4 2006-09-20 T6LE2 Pin Name I/O Function Output channels select pins This signal selects 300 / 263 / 256-pin mode for the LCD panel driver. MODE1 MODE2 I MODE1 MODE2 LCD drive output pins Non-output pins H H 300-out ⎯ H L 263-out G133 to G169 (VEE level ) L H 256-out G129 to G172 (VEE level ) L L ⎯ XDON I Display-ON input pin When XDON = low, the VGG voltage is output all output pins irrespective of the shift data and the content of input data. After, the contents of the shift registers becomes unfixed the data. XON operates asynchronously with CPV. This pin is pulled-up to the VDD. Since all LCD drive outputs output (G1 to G300) the VGG level, much current may generate them momentarily. When 263 / 256-pin mode, unapplied LCD panel drive pins fixed VEE. The voltage applied to this pin must be a DC-level voltage that is either high (VDD) or low (VSS). G1 to G300 O LCD panel drive pins These pins output the shift register data or the voltage of VGG or VEE depending on the control signals OE and XDON. VGG ⎯ Power supply for LCD drive VEE ⎯ Power supply for LCD drive VDD ⎯ Power supply for the internal logic The (VDD) is the MODE1, MODE2 and U/D pin for connection. VSS ⎯ Power supply for the internal logic The (VSS) is the MODE1, MODE2 and U/D pin for connection. 5 2006-09-20 T6LE2 Device Operation z Shift data transfer method MODE1 MODE2 Output Mode H H 300-out H L 263-out L H 256-out L L Shift Data U/D Pin Input Output H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G300 L DO/I DI/O G300 → G299 → G298 → ··· → G1 H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G132 → G170 → ··· → G300 L DO/I DI/O G300 → G299 → G298 → ··· → G170 → G132 →··· → G1 H DI/O DO/I G1 → G2 → G3 → G4 → ··· → G128 → G173 → ··· → G300 L DO/I DI/O G300 → G299 → G298 → ··· → G173 → G128 →··· → G1 Data Transfer Method Don't use The input data (DI/O or DO/I) is latched into the internal register synchronously with the rising edge of the shift clock CPV. At the same time that the data is shifted to the next register at the next rise of CPV, new vertical shift data is latched into. In the output operation, the data in the last shift register (G300 or G1) is output synchronously with the falling edge of CPV. (The output high voltage is the VDD level; the output low voltage is the VSS level.) 6 2006-09-20 T6LE2 Timing Diagram 1 (300-out mode, U/D = high level, MODE1 = high level, MODE2 = high level) DI/O (Input) 1 2 3 4 5 300 301 CPVL/R OE L/R XDON G1 G2 G3 G4 G300 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin Timing Diagram 2 (300-out mode, U/D = low level, MODE1 = high level, MODE2 = high level) DO/I (Input) 1 2 3 4 5 300 301 CPVL/R OE L/R high level XDON G300 G299 G298 G297 G1 DI/O (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin 7 2006-09-20 T6LE2 Timing Diagram 3 (263-out mode, U/D = high level, MODE1 = high level, MODE2 = low level) DI/O (Input) 1 2 3 4 5 263 264 CPVL/R OE L/R high level XDON G1 G2 G3 G4 G133 to G169 VEE G300 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin Timing Diagram 4 (256-out mode, U/D = high level, MODE1 = low level, MODE2 = high level) DI/O (Input) 1 2 3 4 5 256 257 CPVL/R OE L/R high level XDON G1 G2 G3 G4 G129 to G172 VEE G300 DO/I (Output) : This part is output which is controlled ( fixed to VEE ) by OE pin 8 2006-09-20 T6LE2 Absolute Maximum Ratings (VSS = 0 V) Parameter Symbol Rating Unit Supply voltage (1) VDD −0.3 to 4.0 Supply voltage (2) VGG −0.3 to 48.0 Supply voltage (3) VEE −20.0 to 0.3 Supply voltage (4) VGG − VEE −0.3 to 45.0 Input voltage VIN −0.3 to VDD + 0.3 Storage temperature Tstg −55 to 125 V °C Recommended Operating Conditions (VSS = 0 V) Parameter Symbol Rating Supply voltage (1) VDD 2.3 to 3.6 Supply voltage (2) VGG 10 to 35 Supply voltage (3) VEE −15 to −5 Supply voltage (4) VGG − VEE 15.0 to 43.5 Operating temperature Topr −20 to 75 °C Operating frequency fCPV 150 (max） kHz CL 300 (max) pF/PIN Output Load capacitance Unit V Electrical Characteristics DC Characteristics (VGG − VEE = 30.0 to 43.5 V, VDD = 2.3 to 3.6 V, VSS = 0 V, Ta = −20 to 75°C) Parameter Low Level Symbol Test Conditions Min Max ⎯ VSS 0.3 × VDD VDD VIL1 ⎯ Input voltage (1) High Level VIH1 ⎯ 0.7 × VDD Low Level VIL2 ⎯ VSS (0.3 × VDD) High Level VIH2 ⎯ (0.7 × VDD) VDD Low Level VOL VSS VSS + 0.4 ⎯ Input voltage (2) IOL = 40 μA ⎯ Output voltage Output resistance Test circuit High Level VOH Low Level ROL High Level ROH Input leakage current IIN1 IIN2 Current consumption (1) IGG Current consumption (2) IDD Current consumption (3) IEE IOH = −40 μA ⎯ ⎯ ⎯ VOUT = VEE + 0.5 V VOUT = VGG − 0.5 V ⎯ VIN = VDD no load (Note2) VDD − 0.4 VDD ⎯ 1000 −1 1 −1 1 ⎯ T.B.D. ⎯ T.B.D. ⎯ T.B.D. Unit Relevant V (Note1) V XDON V DI/O DO/I Ω G1 to G300 μA (Note1) XDON VGG μA VDD VEE Note1: Input pins : DI/O, DO/I, CPVL/R, OE L/R Note2: fCPV = 50kHz, Shift data input : 60Hz, OE = low level, XDON = high level, MODE1 / MODE2 = high level 9 2006-09-20 T6LE2 AC Characteristics VGG − VEE = 30.0 to 43.5 V, VDD = 2.3 to 3.6 V, VSS = 0 V, Ta = −20 to 75°C 、tfIN = 100ns (Max) trIN = 100ns (Max） Symbol Test circuit Test Conditions Min Max Unit tCPV ⎯ ⎯ ⎯ 150 kHz CPV pulse width (H) tCPVH ⎯ ⎯ 500 ⎯ CPV pulse width (L) tCPVL ⎯ ⎯ 500 ⎯ Data set-up time tsDI ⎯ ⎯ 200 ⎯ Data hold time thDI ⎯ ⎯ 200 ⎯ OE enable time twOE ⎯ ⎯ 1 ⎯ Display-ON pulse width twON ⎯ CL = 300 pF 100 ⎯ Output delay time (1) tpdDO ⎯ CL = 30 pF ⎯ 250 Output delay time (2) tpdG ⎯ CL = 300 pF ⎯ 800 Output delay time (3) tpdOE ⎯ CL = 300 pF ⎯ 800 Output delay time (4) tpdON ⎯ CL = 300 pF ⎯ 10 μs Output delay time (5) tdlO ⎯ CL = 30 pF ⎯ 50 ns Parameter Clock frequency 50% 50% 50% 50% tsDI DI/O, DO/I (Input) μs ns tCPVL tCPVH CPVL/R ns 50% thDI 50% 50% tpdG tpdG 50% G1 VGG 50% tpdG G2 to G300 VEE tpdG 50% 50% VGG VEE CPVL/R 50% 50% VGG G300 tpdDO DO/I, DI/O (Output) tpdDO 50% VEE 50% twOE OE 50% 50% tpdOE G1 to G300 tpdOE 50% 50% VGG VEE 10 2006-09-20 T6LE2 twON XDON 50% 50% tpdON G1 to G300 tpdON 50% 50% VGG VEE trIN Input OE L/R, CPVL/R 50% Output OE L/R, CPVL/R 80% 20% 20% 50% tdlO 50% tfIN tdlO 50% Power Supply Sequence Turn power on in the order VDD → VEE → Input signal → VGG. Turn power off in th reverse order. However, if can be turned off at the same time, VGG, VDD, Input signals and VEE under the condition of VEE ≤ VSS ≤ Input signals ≤ VDD ≤ VGG. The T6LE2 has a self Power on reset function. Keep the reset period : TrG ≥ 10μs TrG VGG VDD VSS VEE Instruction for operating circumstances • Light striking a semiconductor device can generate electromotive force due to photoelectric effects. In some cases this may cause the device to malfunction. This is more likely to be affected for the devices in which the surface (back), or side of the chip is exposed. At the design phase, please make sure that devices are protected against incident light from external sources. Please take into account of incident light from external sources during actual operation and during inspection. • Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Please design and manufacture products so that there is no chance of users touching the film after assembly, or if they do that, there is no chance of them injuring themselves. When cutting out the film, please ensure that the film shavings do not cause accidents. After use, please treat the leftover film and reel spacers as industrial waste. 11 2006-09-20 T6LE2 RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice. 021023_D • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc. 021023_A • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. 021023_B • The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • Please use this product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. • The products described in this document are subject to foreign exchange and foreign trade control laws. 021023_E 12 2006-09-20