TC55VEM208ASTN40,55 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 524,288-WORD BY 8-BIT STATIC RAM DESCRIPTION The TC55VEM208ASTN is a 4,194,304-bit static random access memory (SRAM) organized as 524,288 words by 8 bits. Fabricated using Toshiba's CMOS Silicon gate process technology, this device operates from a single 2.3 to 3.6 V power supply. Advanced circuit technology provides both high speed and low power at an operating current of 3 mA/MHz (typ) and a minimum cycle time of 40 ns. It is automatically placed in low-power mode at 0.7 µA standby current (typ) when chip enable ( CE ) is asserted high. There are two control inputs. CE is used to select the device and for data retention control, and output enable ( OE ) provides fast memory access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. The TC55VEM208ASTN is available in a plastic 32-pin thin-small-outline package (TSOP). FEATURES • • • • • • • 3.6 V 10 µA 3.0 V 5 µA Access Times: • Low-power dissipation Operating: 9 mW/MHz (typical) Single power supply voltage of 2.3 to 3.6 V Power down features using CE Data retention supply voltage of 1.5 to 3.6 V Direct TTL compatibility for all inputs and outputs Wide operating temperature range of −40° to 85°C Standby Current (maximum): TC55VEM208ASTN Access Time 40 55 40 ns 55 ns CE Access Time 40 ns 55 ns OE Access Time 25 ns 30 ns Package: TSOPⅠ32-P-0.50 • (Weight:0.22 g typ) PIN ASSIGNMENT (TOP VIEW) PIN NAMES 32 PIN TSOP A0~A18 1 32 16 17 R/W Read/Write Control OE Output Enable CE Chip Enable I/O1~I/O8 (Normal) Address Inputs Data Inputs/Outputs VDD Power GND Ground Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name A11 A9 A8 A13 R/W A17 A15 VDD A18 A16 A14 A12 A7 A6 A5 A4 Pin No. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name A3 A2 A1 A0 I/O1 I/O2 I/O3 GND I/O4 I/O5 I/O6 I/O7 I/O8 CE A10 OE 2002-08-07 1/11 TC55VEM208ASTN40,55 BLOCK DIAGRAM ROW ADDRESS DECODER ROW ADDRESS REGISTER VDD GND MEMORY CELL ARRAY 2,048 × 256 × 8 (4,194,304) 8 SENSE AMP COLUMN ADDRESS DECODER CLOCK GENERATOR I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 DATA CONTROL A7 A8 A9 A11 A12 A13 A14 A15 A16 A17 A18 ROW ADDRESS BUFFER CE COLUMN ADDERSS REGISTER COLUMN ADDRESS BUFFER CE A0 A1 A2 A3 A4 A5 A6 A10 OE R/W CE CE OPERATING MODE MODE CE OE R/W I/O1~I/O8 POWER Read L L H Output IDDO Write L * L Input IDDO Output Deselect L H H High-Z IDDO Standby H * * High-Z IDDS * = don't care H = logic high L = logic low MAXIMUM RATINGS SYMBOL RATING VALUE UNIT −0.3~4.2 V VDD Power Supply Voltage VIN Input Voltage VI/O Input/Output Voltage PD Power Dissipation Tsolder Soldering Temperature (10s) 260 °C Tstg Storage Temperature −55~150 °C Topr Operating Temperature −40~85 °C −0.3*~4.2 V −0.5~VDD + 0.5 V 0.6 W *: −2.0 V when measured at a pulse width of 20ns 2002-08-07 2/11 TC55VEM208ASTN40,55 DC RECOMMENDED OPERATING CONDITIONS (Ta = −40° to 85°C) SYMBOL PARAMETER VDD Power Supply Voltage VIH Input High Voltage VIL Input Low Voltage VDH Data Retention Supply Voltage MIN TYP MAX UNIT 2.3 3.6 V VDD + 0.3 V −0.3* VDD × 0.24 V 1.5 3.6 V VDD = 2.3 V~2.7 V 2.0 VDD = 2.7 V~3.6 V 2.2 *: −2.0 V when measured at a pulse width of 20ns DC CHARACTERISTICS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) SYMBOL PARAMETER TEST CONDITION IIL Input Leakage Current IOH Output High Current VOH = VDD − 0.5 V VIN = 0 V~VDD MIN TYP MAX UNIT ±1.0 µA −0.5 mA IOL Output Low Current VOL = 0.4 V 2.1 mA ILO Output Leakage Current CE = VIH or R/W = VIL or OE = VIH, VOUT = 0 V~VDD ±1.0 µA MIN 35 1 µs 8 MIN 30 1 µs 3 1 10 0.7 VDD =3.0 V Ta = −40~40°C 2 Ta = −40~85°C 5 CE = VIL and R/W = VIH, IOUT = 0 mA, Other Input = VIH/VIL IDDO1 Operating Current IDDO2 mA tcycle CE = 0.2 V and R/W = VDD − 0.2 V, IOUT = 0 mA, Other Input = VDD − 0.2 V/0.2 V mA CE = VIH IDDS1 VDD = Ta = −40~85°C 3.3V± 0.3 V Standby Current Ta = 25°C CE = VDD − 0.2 V IDDS2 mA µA CAPACITANCE (Ta = 25°C, f = 1 MHz) SYMBOL PARAMETER TEST CONDITION MAX UNIT CIN Input Capacitance VIN = GND 10 pF COUT Output Capacitance VOUT = GND 10 pF Note: This parameter is periodically sampled and is not 100% tested. 2002-08-07 3/11 TC55VEM208ASTN40,55 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.7 to 3.6 V) READ CYCLE TC55VEM208ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tRC Read Cycle Time 40 55 tACC Address Access Time 40 55 tCO Chip Enable Access Time 40 55 tOE Output Enable Access Time 25 30 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tOD Chip Enable High to Output High-Z 20 25 tODO Output Enable High to Output High-Z 20 25 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55VEM208ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tWC Write Cycle Time 40 55 tWP Write Pulse Width 30 40 tCW Chip Enable to End of Write 35 45 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 20 25 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 20 25 tDH Data Hold Time 0 0 Note: ns tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-07 4/11 TC55VEM208ASTN40,55 AC CHARACTERISTICS AND OPERATING CONDITIONS (Ta = −40° to 85°C, VDD = 2.3 to 3.6 V) READ CYCLE TC55VEM208ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tRC Read Cycle Time 55 70 tACC Address Access Time 55 70 tCO Chip Enable Access Time 55 70 tOE Output Enable Access Time 30 35 tCOE Chip Enable Low to Output Active 5 5 tOEE Output Enable Low to Output Active 0 0 tOD Chip Enable High to Output High-Z 25 30 tODO Output Enable High to Output High-Z 25 30 tOH Output Data Hold Time 10 10 ns WRITE CYCLE TC55VEM208ASTN SYMBOL PARAMETER 40 UNIT 55 MIN MAX MIN MAX tWC Write Cycle Time 55 70 tWP Write Pulse Width 40 50 tCW Chip Enable to End of Write 45 55 tAS Address Setup Time 0 0 tWR Write Recovery Time 0 0 tODW R/W Low to Output High-Z 25 30 tOEW R/W High to Output Active 0 0 tDS Data Setup Time 25 30 tDH Data Hold Time 0 0 Note: ns tOD, tODO and tODW are specified in time when an output becomes high impedance, and are not judged depending on an output voltage level. 2002-08-07 5/11 TC55VEM208ASTN40,55 AC TEST CONDITIONS PARAMETER TEST CONDITION 0.2 V, VDD × 0.7 V + 0.2 V Input pulse level t R, t F 1V / ns(Fig.1) Timing measurements VDD × 0.5 Reference level VDD × 0.5 30 pF + 1 TTL Gate(Fig.2) Output load Fig.1 : Input rise and fall time Fig.2 : Output load VTM VDD Typ GND 90% 10% 90% 10% 1 V/ns R1 Dout 1 V/ns tR tF R2 30 pF R1 = 810 Ω R2 = 1610 Ω VTM = 2.3 V 2002-08-07 6/11 TC55VEM208ASTN40,55 TIMING DIAGRAMS READ CYCLE (See Note 1) tRC Address A0~A18 tACC tOH tCO CE tOE tOD OE DOUT I/O1~8 tOEE tCOE tODO VALID DATA OUT Hi-Z WRITE CYCLE 1 (R/W CONTROLLED) Hi-Z (See Note 4) tWC Address A0~A18 tAS tWP tWR R/W tCW CE tOEW tODW DOUT I/O1~8 (See Note 2) Hi-Z tDS DIN I/O1~8 (See Note 5) (See Note 3) tDH VALID DATA IN (See Note 5) 2002-08-07 7/11 TC55VEM208ASTN40,55 WRITE CYCLE 2 (CE CONTROLLED) (See Note 4) tWC Address A0~A18 tAS tWP tWR R/W tCW CE tCOE DOUT I/O1~8 tODW Hi-Z Hi-Z tDS DIN I/O1~8 Note: (1) (See Note 5) tDH VALID DATA IN (See Note 5) R/W remains HIGH for the read cycle. (2) If CE goes LOW coincident with or after R/W goes LOW, the outputs will remain at high impedance. (3) If CE goes HIGH coincident with or before R/W goes HIGH, the outputs will remain at high impedance. (4) If OE is HIGH during the write cycle, the outputs will remain at high impedance. (5) Because I/O signals may be in the output state at this time, input signals of reverse polarity must not be applied. 2002-08-07 8/11 TC55VEM208ASTN40,55 DATA RETENTION CHARACTERISTICS (Ta = −40° to 85°C) SYMBOL VDH PARAMETER TYP MAX UNIT 1.5 3.6 V Ta = −40~85°C 10 Ta = −40~40°C 2 Ta = −40~85°C 5 Data Retention Supply Voltage VDH = 3.6 V IDDS2 MIN Standby Current VDH = 3.0 V µA tCDR Chip Deselect to Data Retention Mode Time 0 ns tR Recovery Time 5 ms CE CONTROLLED DATA RETENTION MODE VDD VDD DATA RETENTION MODE 2.3 V (See Note) (See Note) VIH tCDR CE VDD − 0.2 V tR GND Note: When CE is operating at the VIH(min.) level, the operating current is given by IDDS1 during the transition of VDD from 2.3(2.7) to 2.2V(2.4 V). 2002-08-07 9/11 TC55VEM208ASTN40,55 PACKAGE DIMENSIONS Weight:0.22 g (typ) 2002-08-07 10/11 TC55VEM208ASTN40,55 RESTRICTIONS ON PRODUCT USE 000707EBA • TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc.. • The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer’s own risk. • The products described in this document are subject to the foreign exchange and foreign trade laws. • The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. • The information contained herein is subject to change without notice. 2002-08-07 11/11