TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 D D D D D D D D D D D D Supports Both CIS and CCD Sensors 10-Bit, 4 MSPS, A/D Converter Differential Nonlinearity Error: ±0.5 LSB Typ Integral Nonlinearity Error: ±0.6 LSB Typ 8-Bit Offset Correction DAC PGA With 6-Bit Gain Resolution Auto-cycling Gain and Offset Control Single 5-V Supply Operation Very Low Power: 190 mW Typical Control by Parallel and Serial Interface Internal Reference Voltages 32-Pin TSSOP Package description DA PACKAGE (TOP VIEW) OP0 OP1 OP2 OP3 OP4 DIVDD DIGND OP5 OP6 OP7 OP8 OP9 DVDD DGND ADCCLK SCK/RNW 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 RPO RMO RIN GIN BIN AVDD AGND CLAMP SR SV MA0/ACYC MA1 OE NRESET SEN/STB SDI/DNA The TLC8188 is a highly-integrated monolithic analog signal processor/digitizer designed to interface the contact image sensor (CIS) and linear charge-coupled device (CCD) image sensors in scanner applications. The input of the TLC8188 allows direct connection to the CIS and direct ac coupling of the linear CCD. The TLC8188 performs all the analog processing functions necessary to maximize the dynamic range, correct various errors associated with the CIS and the linear CCD sensors, and then digitize the results with an on-chip analog-to-digital converter (ADC). The key components of the TLC8188 include: input clamp circuitry and a correlated double sampler (CDS), a programmable gain amplifier (PGA) with auto-cycling gain control, a programmable offset correction controlled by a digital-to-analog converter (DAC), a 10-bit, 4 MSPS pipeline ADC, a bidirectional parallel bus and a three-wire serial port for easy microprocessor interface, and internal reference voltages. Designed in advanced CMOS process, the TLC8188 operates from a single 5-V power supply and its digital interface is 3 V compatible. The normal power consumption of the TLC8188 is just 190 mW. Fully integrated analog processing circuitry, high throughput rate, single supply operation and low cost make the TLC8188 an ideal CIS/linear CCD sensor interfacing solution for imaging applications such as scanners and multifunctional office equipment (printer/scanner/facsimile/copier). The device is available in a 32-pin TSSOP package and is specified over the 0°C to 70°C operating temperature range. AVAILABLE OPTIONS PACKAGED DEVICE TA SMALL OUTLINE (DA) 0°C to 70°C TLC8188CDA Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1998, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 functional block diagram CLAMP AVDD RPO RMO DVDD DIVDD INTERNAL REFERENCE CLAMP OE RIN GIN CDS (S/H) MUX 8-BIT DAC BIN PGA MUX MUX GRN OS BLUE OS RED GAIN GRN GAIN BLUE GAIN AGND 2 THREE STATE LATCHES OP (0 – 9) 6 8 RED OS 10-BIT ADC POST OFFICE BOX 655303 DGND • DALLAS, TEXAS 75265 Control Logic ADCCLK MA1 MA0/ACYC SV SR NRESET SERIAL PORT SDI/DNA SCK/RNW SEN/STB DIGND TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 Terminal Functions TERMINAL NAME NO. I/O ADCCLK 15 AGND 26 AVDD BIN 27 28 I Blue channel input CLAMP 25 I CCD input clamp signal, active high DGND 14 Digital ground DIGND 7 Digital interface circuit ground DIVDD DVDD 6 Digital interface circuit supply voltage, 3 V to 5 V 13 Digital supply voltage, 5 V GIN I DESCRIPTION ADC conversion clock input. Analog ground Analog supply voltage, 5 V 29 I Green channel input 21, 22 I MA1 and MA0 select the color to which all internal MUX (input, gain, offset) will point. When in auto-cycling mode, the input mux and internal registers are auto-cycled by the ACYC. The ACYC is a control signal such as a line start pulse that defines the start of a current scanning line. NRESET 19 I Power-on reset and Interface mode control. If SEN/STB is 1 when NRESET goes high then the device is in parallel configuration data input mode. If SEN/STB is 0 when NRESET goes high then the device is in serial data input mode. OE 20 I Three-state output enable, active low OP(0–4) 1–5 I/O Three-state bi-directional data bus, OP0 and OP1 are output only. OP(5–9) 8 – 12 I/O Three-state bi-directional data bus. RIN 30 I Red channel input RMO 31 O Ref– output for external decoupling RPO 32 O Ref+ output for external decoupling SCK/RNW 16 I Serial interface: serial clock Parallel interface: 1 – OP(9–2) is output bus, 0 – OP(9–2) is input bus SDI/DNA 17 I Serial interface: serial interface input data Parallel interface: 1 – data, 0 – address SEN/STB 18 I Serial interface: serial data transfer enable, active high. Parallel interface: strobe, active low. SR 24 I CCD reset level sample pulse input SV 23 I CCD signal level sample pulse input MA1, MA0/ACYC absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6.5 V Analog input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC+0.3 V Reference input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCC+0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC+0.3 V Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 150°C Operating free-air temperature range, TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 recommended operating conditions power supplies MIN NOM MAX UNIT Analog supply voltage, AVDD 4.5 5.5 V Digital supply voltage, DVDD 4.5 5.5 V Digital interface supply voltage, DIVDD 2.7 5.5 V digital inputs MIN High-level input voltage, VIH DIVDD = 3 V to 5.5 V DIVDD = 3 V to 5.5 V Low-level input voltage, VIL NOM MAX UNIT 0.8DIVDD V Input ADCCLK frequency 0.2DIVDD 4 MHz 13.3 MHz Input SCLK frequency V electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 5 V, ADCCLK = 4 MHz (unless otherwise noted) total device PARAMETER TEST CONDITIONS MIN AVDD operating current TYP MAX 35 40 UNIT mA 1 mA 2 mA Device power consumption 190 mW Device power consumption, power down mode 7 mW DIVDD operating current 5 pF loading, all outputs switching analog-to-digital converter (ADC) PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 10 Bits INL Integral nonlinearity ±0.6 ±2 LSB DNL Differential nonlinearity ±0.5 ±1 LSB No missing codes Full-scale input voltage 4 Input capacitance VPP pF 15 Conversion rate 4 ADC output latency MHz ADCCLK cycles 4 correlated double sampler (CDS) and programmable gain amplifier (PGA) PARAMETER TEST CONDITIONS MIN TYP CDS sample rate UNIT 4 MHz Analog input voltage 4 Input capacitance 5 pF PGA gain control resolution 6 Bits PGA gain 1 V 5 V/V ±5% PGA gain accuracy 4 MAX PGA output settling time 125 ns New gain settling time 125 ns POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 electrical characteristics over recommended operating free-air temperature range, AVDD = DVDD = 5 V, ADCCLK = 4 MHz (unless otherwise noted) (continued) digital-to-analog converter (DAC) PARAMETER TEST CONDITIONS MIN TYP Resolution MAX UNIT 8 Bits INL Integral nonlinearity ±0.5 ±1 LSB DNL Differential nonlinearity ±0.3 ±1 LSB 2 µs Output settling time To 1% accuracy reference voltages PARAMETER TEST CONDITIONS Internal bandgap voltage reference MIN TYP MAX 1.15 1.22 1.28 Temperature coefficient 100 Voltage reference noise UNIT V ppm/°C 0.5 LSB ADCRef+ ADC positive reference voltage Externally decoupled 3.35 3.5 3.65 V ADCRef– ADC negative reference voltage Externally decoupled 1.35 1.5 1.65 V DACRef+ DAC positive reference voltage 2.5 V input clamp voltages PARAMETER TEST CONDITIONS Clamp voltage, high MIN TYP AVDD = 4.5 V to 5.5 V AVDD = 4.5 V to 5.5 V Clamp voltage, low MAX UNIT 2.5 V 1.5 V digital specifications PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Logic Inputs IIH IIL High-level input current Ci Input capacitance DIVDD = 5 V DIVDD = 5 V Low-level input current –50 –50 50 µA 50 µA 5 pF Logic Outputs VOH VOL High-level output voltage IOZ CO High-impedance-state output current IOH = 50 µA to 0.5 mA IOL = 50 µA to 0.5 mA Low-level output voltage DIVDD–0.4 0.4 –10 Output capacitance • DALLAS, TEXAS 75265 V 10 20 POST OFFICE BOX 655303 V µA pF 5 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 timing requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Serial Interface tw(SCKH) tw(SCKL) SCK high pulse duration 37.5 ns SCK low pulse duration 37.5 ns tsu(SSU) th(SH) Data (SDI) to SCK setup time 10 ns SDI to SCK hold time 10 ns tsu(SCE) tw(SEN) SCK to SEN setup time 20 ns SEN pulse duration 50 ns tsu(SEC) SEN to SCK setup time Parallel Interface 20 ns tw(STB) tsu(D) Strobe pulse duration 50 ns Data to strobe setup time 10 ns th(DH) tsu(ADS) Data to strobe hold time 10 ns Address to srobe setup time 10 ns th(ADH) td(OPZI) Address to strobe hold time 10 RNW low to OP bus 3-state delay time 10 ns td(OPZE) td(OPDV) RNW high to OP bus 3-state delay time 0 ns RNW high to data valid delay time 10 ns tdis ten Output disable time 10 ns Output enable time 10 ns td(POW) Delay time to power up 2 ms td(PD) CIS Mode Delay time to power down 30 ns td(LSD) tw(ACYPW) ACYC high to the first valid pixel delay time 1 µs tw(ACLKH) tw(ACLKL) tsu(SMPSU) td(OD) Sampling setup time ns Output ACYC pulse duration 25 ns ADCCLK high pulse duration 125 ns ADCCLK low pulse duration 125 ns 20 ns ADCCLK to output data delay time 15 ns 1 µs CCD Mode td(LSD) tw(ACLKH) ACYC high to the first valid pixel delay time ADCCLK high pulse duration 125 ns tw(ACLKL) tw(SRW) ADCCLK low pulse duration 125 ns Sample Reset (SR) pulse duration 40 ns tw(SVW) td(ACLKSR) Sample Video (SV) pulse duration 40 ns ADCCLK low to SR low 60 ns td(SRSVN) td(SRSVM) Delay time SR low to SV high 20 ns Delay time SV low to SR high 125 ns td(OD) ADCCLK to output data delay time 6 POST OFFICE BOX 655303 15 • DALLAS, TEXAS 75265 ns TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 PARAMETER MEASUREMENT INFORMATION tw(ACYPW) ACYC td(LDS) CIS Clock n+1 n CIS Output tw(ACLKH) tsu(SMPSU) ADCCLK tW(ACLKL) td(OD) ADC OUT Figure 1. Typical CIS Mode Operation Timing tw(ACYPW) ACYC td(LSD) CCD Reset CCD Output n+1 n tw(SRW) SR td(SRSVM) tw(SVW) td(SRSVN) SV td(ACLKSR) tw(ACLKH) ADCCLK tw(ACLKL) td(OD) ADC OUT Figure 2. Typical CCD Mode Operation Timing POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 PARAMETER MEASUREMENT INFORMATION SCK tw(SCKH) SDI tw(SCKL) tsu(ssu) a5 a4 th(SH) a3 a2 a1 a0 b7 b0 tsu(SEC) tsu(SCE) SEN tw(SEN) Figure 3. Serial Interface Timing tw(STB) STB th(DH) tsu(D) OP (2–9) tsu(D) Address th(DH) Data tsu(ADS) th(ADH) DNA td(OPZI) td(OPZE) RNW td(OPDV) Figure 4. Parallel Interface Timing OE tdis OP (0–9) Active ten Hi-Z Figure 5. High-Impedance Output Timing 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 PRINCIPLES OF OPERATION internal register definition ADDRESS A5–A0 DESCRIPTION R/W DEF. (Hex) 000000 Not Used 000001 Setup register 1 R/W 01 000010 Setup register 2 R/W 00 000011 Setup register 3 R/W 02 000100 Software reset W 00 000101 Auto-cycle reset W 00 000110 Read-only ID R R/W B7 B6 B5 FME B4 FM1 FM0 B3 B2 B1 B0 MUXOP SM1 SM0 ENBL INTM1 INTM0 MM1 MM0 RLC1 RLC0 0 0 0 0 0 0 0 1 00 ST RR RA5 RA4 RA3 RA2 RA1 RA0 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 000111 Test register 001000 Reserved 001001 Reserved 1000xx DAC values R/W 00 1001xx DAC signs R/W 00 1010xx PGA gains R/W 00 xx BIT DAC0 DSIGN PGA5 A1 A0 ADDRESS LSB DECODE R/W 0 0 Red register R/W 0 1 Green register R/W 1 0 Blue register R/W 1 1 Red, green, and blue PGA4 PGA3 PGA2 PGA1 PGA0 DEFAULT (HEX) 00 W setup register 1 description BIT NAME DEFAULT DESCRIPTION B0 ENBL 1 Standby mode, 0 – standby, 1 – power up B2,B1 SM1, SM0 00 Sensor mode control: SM1 SM0 0 0 0 1 1 0 B3 MUXOP 0 CIS mode – single-ended input (default, RIN pin) CIS mode – differential input (RIN, GIN pins) CCD mode Eight bit output mode: 0 – ten bit, 1– eight-bit multiplexed setup register 2 description BIT NAME DEFAULT DESCRIPTION B1,B0 MM1, MM0 00 Input MUX and register MUX control: MM1 MM0 0 0 Internal 0 1 External 1 0 Auto-cycling B3,B2 INTM1, INTM0 00 Register containing color codes used in internal modes B5,B4 FM1, FM0 00 Register containing color codes used in force mux modes B6 FME 0 Force mux mode control, 1 – force mux, 0 – no force mux POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 PRINCIPLES OF OPERATION color selection mode description FME MM1 MM0 NAME DESCRIPTION 0 0 0 Internal, no force mux Input mux, offset and gain register selected from internal register bits INTM1, INTM0 0 0 1 External, no force mux Input mux, offset and gain register selected from external pins MA1, MA0 MA1 MA0 0 0 Red 0 1 Green 1 0 Blue 0 1 0 Auto-cycling, no force mux Input mux, offset and gain register auto-cycled, R → G → B → R on ACYC pulse. 1 0 0 Internal, force mux Input mux selected from internal register bits FM1, FM0; offset and gain register selected from internal register bits INTM1, INTM0 1 0 1 External, force mux Input mux selected from internal register bits FM1, FM0; offset and gain register selected from external pins MA1, MA0 1 1 0 Auto-cycling, force mux Input mux selected from internal register bits FM1, FM0; offset and gain register auto-cycled, R → G → B → R on ACYC pulse setup register 3 description BIT B1, B0 NAME DEFAULT RCL1, RCL0 DESCRIPTION No default setting These two bits control the input clamp voltage levels. RCL1 RCL0 0 0 Clamp low, 1.5 V 0 1 Clamp high, 2.5 V software reset description BIT B7–B0 DESCRIPTION Software reset, reset system to the default settings. auto-cycle reset description BIT B7–B0 DESCRIPTION In auto-cycling mode this will reset auto-cycling to RED channel, RED gain register, and RED offset register. read-only I.D. description BIT NAME B7–B0 ID DEFAULT DESCRIPTION Hard-coded device revision identification. This can be read in one of the test modes. test register description BIT NAME DEFAULT B5–B0 RA5–RA0 00 These six bits select the internal register to be read out at the output data bus. B7 ST 0 Self test. 1 – self-test enable, the DAC output is connected to the PGA input. 0 – self-test disable (default) B6 RR 0 Read internal register value from the output data bus. 1 – read enable, 0 – read disable (default). When the RR bit is set to 1, the content of a register specified by RA5–RA0 can be read from the parallel data bus upper 8 bits, OP(9–2). Both the parallel and serial ports can be used to write any internal registers, but only the parallel port is used to read the registers. 10 DESCRIPTION POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLC8188 10-BIT, 4 MSPS, CIS/LINEAR CCD SENSOR PROCESSOR SLAS177A – DECEMBER 1997 – REVISED SEPTEMBER 1998 PRINCIPLES OF OPERATION DAC value registers and DAC sign register format DSIGN = 0: DSIGN = 1: DAC coding CIS mode DAC output CCD mode DAC output 0000 0000 0 V (default) 0 V (default) 1000 0000 1.25 V 250 mV 1111 1111 2.5 V 500 mV DAC coding CIS mode DAC output CCD mode DAC output 0000 0000 Not applicable 0 V (default) 1000 0000 –250 mV 1111 1111 –500 mV PGA output in CCD mode: VO(PGA) = Gain (Vr – Vs) – Voffset Offset correction performed after gain stage. PGA output in CIS single-ended mode: VO(PGA) = Gain (Vs – Voffset) Offset correction performed before gain stage. PGA output in CIS differential input mode: VO(PGA) = Gain (Signal on RIN – Signal on GIN) No additional offset cancellation. gain registers format PGA coding PGA gain 000000 1 V/V (default) 111111 5 V/V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. 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