TI TLV0832CP

TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
D
D
D
D
D
D
D
D
D
D
8-Bit Resolution
2.7 V to 3.6 V VCC
Easy Microprocessor Interface or
Standalone Operation
Operates Ratiometrically or With VCC
Reference
Single Channel or Multiplexed Twin
Channels With Single-Ended or Differential
Input Options
Input Range 0 V to VCC With VCC Reference
Inputs and Outputs Are Compatible With
TTL and MOS
Conversion Time of 32 µs at
f(CLK) = 250 kHz
Designed to Be Functionally Equivalent to
the National Semiconductor ADC0831 and
ADC0832 at 3 V Supply
Total Unadjusted Error . . . ± 1 LSB
TLV0831 . . . D OR P PACKAGE
(TOP VIEW)
CS
IN+
IN–
GND
1
8
2
7
3
6
4
5
VCC
CLK
DO
REF
TLV0832 . . . D OR P PACKAGE
(TOP VIEW)
CS
CH0
CH1
GND
1
8
2
7
3
6
4
5
VCC /REF
CLK
DO
DI
description
These devices are 8-bit successive-approximation analog-to-digital converters. The TLV0831 has single input
channels; the TLV0832 has multiplexed twin input channels. The serial output is configured to interface with
standard shift registers or microprocessors.
The TLV0832 multiplexer is software configured for single-ended or differential inputs. The differential analog
voltage input allows for common-mode rejection or offset of the analog zero input voltage value. In addition, the
voltage reference input can be adjusted to allow encoding any smaller analog voltage span to the full 8 bits of
resolution.
The operation of the TLV0831 and TLV0832 devices is very similar to the more complex TLV0834 and TLV0838
devices. Ratiometric conversion can be attained by setting the REF input equal to the maximum analog input
signal value, which gives the highest possible conversion resolution. Typically, REF is set equal to VCC (done
internally on the TLV0832).
The TLV0831C and TLV0832C are characterized for operation from 0°C to 70°C. The TLV0831I and TLV0832I
are characterized for operation from – 40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
0°C to 70°C
TLV0831CD
TLV0832CD
TLV0831CP
TLV0832CP
– 40°C to 85°C
TLV0831ID
TLV0832ID
TLV0831IP
TLV0832IP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
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1
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
functional block diagram
Start
Flip-Flop
CLK
CS
CLK
Shift Register
ODD/EVEN
D
DI
(TLV0832
only)
S
R
Start
CLK
To Internal
Circuits
CLK
SGL/DIF
CH0/IN+
CH1/IN –
Analog
MUX
S
Comparator
R
Time
Delay
EN
CS
CS
CS
CS
CS
EN
REF
(TLV0831
only)
Ladder
and
Decoder
Bits 0–7
R
EN
SAR
Logic
and
Latch
CLK
Bits 0–7
Bit 1
MSB
First
9-Bit
Shift
Register
LSB
First
One
Shot
2
POST OFFICE BOX 655303
R
• DALLAS, TEXAS 75265
EOC
R
CLK
D
DO
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
functional description
The TLV0831 and TLV0832 use a sample-data-comparator structure that converts differential analog inputs by
a successive-approximation routine. The input voltage to be converted is applied to an input terminal and is
compared to ground (single ended), or to an adjacent input (differential). The TLV0832 input terminals can be
assigned a positive (+) or negative (–) polarity. The TLV0831 contains only one differential input channel with
fixed polarity assignment; therefore it does not require addressing. The signal can be applied differentially,
between IN+ and IN–, to the TLV0831 or can be applied to IN+ with IN– grounded as a single ended input. When
the signal input applied to the assigned positive terminal is less than the signal on the negative terminal, the
converter output is all zeros.
Channel selection and input configuration are under software control using a serial-data link from the controlling
processor. A serial-communication format allows more functions to be included in a converter package with no
increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter
at the analog sensor and communicating serially with the controlling processor. This process returns noise-free
digital data to the processor.
A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete
conversion process. A clock input is then received from the processor. An interval of one clock period is
automatically inserted to allow the selected multiplexed channel to settle. DO comes out of the high-impedance
state and provides a leading low for one clock period of multiplexer settling time. The SAR comparator compares
successive outputs from the resistive ladder with the incoming analog signal. The comparator output indicates
whether the analog input is greater than or less than the resistive-ladder output. As the conversion proceeds,
conversion data is simultaneously output from DO, with the most significant bit (MSB) first. After eight clock
periods, the conversion is complete. When CS goes high, all internal registers are cleared. At this time, the
output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low
transition followed by address information.
A TLV0832 input configuration is assigned during the multiplexer-addressing sequence. The multiplexer
address shifts into the converter through the data input (DI) line. The multiplexer address selects the analog
inputs to be enabled and determines whether the input is single ended or differential. When the input is
differential, the polarity of the channel input is assigned. In addition to selecting the differential mode, the polarity
may also be selected. Either channel of the channel pair may be designated as the negative or positive input.
On each low-to-high transition of the clock input, the data on DI is clocked into the multiplexer-address shift
register. The first logic high on the input is the start bit. A 2-bit assignment word follows the start bit on the
TLV0832. On each successive low-to-high transition of the clock input, the start bit and assignment word are
shifted through the shift register. When the start bit is shifted into the start location of the multiplexer register,
the input channel is selected and conversion starts. The TLV0832 DI terminal to the multiplexer shift register
is disabled for the duration of the conversion.
The TLV0832 outputs the least-significant-bit (LSB) first data after the MSB-first data stream. The DI and DO
terminals can be tied together and controlled by a bidirectional processor I/O bit received on a single wire. This
is possible because DI is only examined during the multiplexer-addressing interval and DO is still in the
high-impedance state.
POST OFFICE BOX 655303
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3
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
sequence of operation
TLV0831
1
2
3
4
5
6
7
8
9
10
CLK
tsu
tconv
CS
MSB-First Data
MUX
Settling Time
Hi-Z
DO
MSB
7
Hi-Z
LSB
6
5
4
3
2
1
0
TLV0832
1
2
3
4
5
6
10
11
12
13
14
18
19
20
21
CLK
tconv
tsu
CS
+Sign Bit
Start
ODD
SGL
Bit
DI
(TLV0832
only)
Don’t Care
DIF EVEN
MSB-First Data
LSB-First Data
MUX
Settling Time
DO
Hi-Z
MSB
7
LSB
6
2
1
MSB
0
1
2
6
TLV0832 MUX-ADDRESS CONTROL LOGIC TABLE
MUX ADDRESS
SGL/DIF
L
L
H
H
CHANNEL NUMBER
ODD/EVEN
L
H
L
H
CH0
CH1
+
–
+
–
+
+
H = high level, L = low level,
– or + = terminal polarity for the selected input channel
4
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7
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
absolute maximum ratings over recommended operating free-air temperature range (unless
otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
Input voltage range, VI: Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VCC + 0.3 V
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Total input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
Operating free-air temperature range, TA: C suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
I suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: P package . . . . . . . . . . . . . . . . . . . . . 260°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to the network ground terminal.
recommended operating conditions
Supply voltage, VCC (see clock operating conditions)
High-level input voltage, VIH
MIN
NOM
MAX
2.7
3.3
3.6
2
Low-level input voltage, VIL
frequency f(CLK)
Clock frequency,
VCC = 2.7 V
VCC = 3.3 V
Clock duty cycle (see Note 2)
UNIT
V
V
0.8
V
250
kHz
10
600
kHz
40%
60%
Pulse duration, CS high, twH(CS)
220
ns
Setup time, CS low or TLV0832 data valid before CLK↑, tsu
350
ns
Hold time, TLV0832 data valid after CLK↑, th
Operating free-air
free air temperature,
temperature TA
90
C suffix
I suffix
ns
0
70
– 40
85
°C
NOTE 2: The clock-duty-cycle range ensures proper operation at all clock frequencies. When a clock frequency is used outside the
recommended duty-cycle range, the minimum pulse duration (high or low) is 1 µs.
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5
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
electrical characteristics over recommended range of operating free-air temperature, VCC = 3.3 V,
f(CLK) = 250 kHz (unless otherwise noted)
digital section
C SUFFIX
MIN
TYP‡
MAX
TEST CONDITIONS†
PARAMETER
I SUFFIX
MIN
TYP‡
MAX
VCC = 3 V,
VCC = 3 V,
IOH = – 360 µA
2.8
2.4
IOH = – 10 µA
2.9
2.8
VCC = 3 V,
VIH = 3.6 V
IOL = 1.6 mA
High-level input current
IIL
Low-level input current
VIL = 0
IOH
High-level output
(source) current
At VOH, DO= 0 V,
TA = 25°C
– 6.5
IOL
Low-level output (sink) current
At VOL, DO= 0 V,
IOZ
High-impedance-state
output
g
current (DO)
TA = 25°C
TA = 25°C
8
VO = 3.3 V,
VO = 0,
Ci
Input capacitance
VOH
High level output voltage
High-level
VOL
IIH
Low-level output voltage
TA = 25°C
UNIT
V
0.4
V
0.005
0.34
1
0.005
1
µA
– 0.005
–1
– 0.005
–1
µA
– 15
– 6.5
–16
8
– 15
mA
–16
mA
0.01
3
0.01
3
– 0.01
–3
– 0.01
–3
5
Co
Output capacitance
5
† All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
µA
5
pF
5
pF
analog and converter section
PARAMETER
VIC
Common-mode input voltage
On channel
II(
I(stdby)
tdb )
Off channel
Standby input current (see Note 4)
On channel
Off channel
TEST CONDITIONS†
MIN
See Note 3
– 0.05
to
VCC+ 0.05
TYP‡
MAX
UNIT
V
VI = 3.3 V
VI = 0
1
–1
VI = 0
VI = 3.3 V
–1
µA
1
ri(REF)
Input resistance to REF
1.3
2.4
5.9
kΩ
† All parameters are measured under open-loop conditions with zero common-mode input voltage.
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
NOTES: 3. When channel IN– is more positive than channel IN+, the digital output code is 0000 0000. Connected to each analog input are two
on-chip diodes that conduct forward current for analog input voltages one diode drop above VCC. Care must be taken during testing
at low VCC levels (3 V) because high-level analog input voltage (3.6 V) can, especially at high temperatures, cause the input diode
to conduct and cause errors for analog inputs that are near full scale. As long as the analog voltage does not exceed the supply
voltage by more than 50 mV, the output code is correct. To achieve an absolute 0- to 3.3-V input range requires a minimum VCC of
3.25 V for all variations of temperature and load.
4. Standby input currents go in or out of the on or off channels when the A/D converter is not performing conversion and the clock is
in a high or low steady-state conditions.
total device
TYP‡
MAX
TLV0831
0.2
0.75
TLV0832
1.5
2.5
PARAMETER
ICC
MIN
Supply current
‡ All typical values are at VCC = 3.3 V, TA = 25°C.
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
UNIT
mA
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
operating characteristics VCC = Vref = 3.3 V, f(CLK) = 250 kHz, tr = tf = 20 ns, TA = 25°C (unless
otherwise noted)
TEST CONDITIONS†
PARAMETER
Supply-voltage variation error
Total unadjusted error (see Note 5)
Common-mode error
tpd
d
Propagation delay time,
output data after CLK↑
(see Note 6)
tdi
dis
time DO after CS↑
Output disable time,
tconv
Conversion time (multiplexer-addressing
time not included)
TYP
MAX
UNIT
VCC = 3 V to 3.6 V
Vref = 3.3 V,
TA = MIN to MAX
± 1/16
± 1/4
LSB
±1
LSB
Differential mode
± 1/16
± 1/4
LSB
200
500
80
200
80
125
MSB-first data
LSB-first data
CL = 100 pF
CL = 10 pF,
CL = 100 pF,
MIN
ns
RL = 10 kΩ
RL = 2 kΩ
250
8
ns
clock
periods
† All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the
appropriate value specified under recommended operating conditions.
NOTES: 5. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.
6. The MSB-first data is output directly from the comparator and, therefore, requires additional delay to allow for comparator response
time. LSB-first data applies only to TLV0832.
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7
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
PARAMETER MEASUREMENT INFORMATION
VCC
CLK
50%
50%
GND
VCC
tsu
tsu
CLK
VCC
50%
GND
CS
tpd
0.4 V
GND
th
2V
VOH
th
DO
50%
VOL
VCC
2V
DI
0.4 V
0.4 V
Figure 2. Data-Output Timing
GND
Figure 1. TLV0832 Data-Input Timing
VCC
Test
Point
S1
RL
From Output
Under Test
CL
(see Note A)
S2
LOAD CIRCUIT
tr
CS
50%
tr
VCC
90%
10%
CS
10%
GND
DO
Output
90%
VCC
GND
DO
Output
S1 closed
S2 open
VCC
10%
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTE A: CL includes probe and jig capacitance.
Figure 3. Output Disable Time Test Circuit and Voltage Waveforms
8
GND
tdis
tdis
S1 open
S2 closed
VCC
90%
50%
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GND
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
TYPICAL CHARACTERISTICS
UNADJUSTED OFFSET ERROR
vs
REFERENCE VOLTAGE
LINEARITY ERROR
vs
REFERENCE VOLTAGE
1.5
VCC = 3.3 V
f(CLK) = 250 kHz
TA = 25°C
VI+ = VI – = 0 V
14
1.25
12
E L – Linearity Error – LSB
EO(unadj) – Unadjusted Offset Error – LSB
16
10
8
6
4
1.0
0.75
0.5
0.25
2
0
0.01
0.1
1.0
0
10
1
0
Vref – Reference Voltage – V
4
Figure 5
LINEARITY ERROR
vs
FREE-AIR TEMPERATURE
LINEARITY ERROR
vs
CLOCK FREQUENCY
0.5
2.0
Vref = 3.3 V
VCC = 3.3 V
1.8
Vref = 3.3 V
f(CLK) = 250 kHz
1.6
E L – Linearity Error – LSB
E L – Linearity Error – LSB
3
Vref – Reference Voltage – V
Figure 4
0.45
2
0.4
0.35
0.3
1.4
85°C
1.2
1
0.8
25°C
0.6
0.4
– 40°C
0.2
0.25
– 50
– 25
0
25
50
75
100
0
0
100
TA – Free-Air Tempertature – °C
200
300
400
500
600
700
800
f(CLK) – Clock Frequency – kHz
Figure 6
Figure 7
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9
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
TYPICAL CHARACTERISTICS
TLV0831
TLV0831
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
SUPPLY CURRENT
vs
CLOCK FREQUENCY
0.3
0.5
f(CLK) = 250 kHz
CS = High
VCC = 3.3 V
TA = 25°C
0.4
I CC – Supply Current – mA
I CC – Supply Current – mA
VCC = 3.6 V
VCC = 3.3 V
0.2
VCC = 3 V
0.3
0.2
0.1
0.1
– 50
– 25
0
25
50
75
0
100
0
100
TA – Free-Air Temperature — °C
200
Figure 9
OUTPUT CURRENT
vs
FREE-AIR TEMPERATURE
16.5
VCC = 3.3 V
I O – Output Current – mA
16
IOL (DO = 3.3 V)
15.5
– IOH (DO = 0 V)
15
– IOH (DO = 2.4 V)
14.5
IOL (DO = 0.4 V)
– 25
0
25
50
TA – Free-Air Temperature – °C
Figure 10
10
400
f(CLK) – Clock Frequency – kHz
Figure 8
14
– 50
300
POST OFFICE BOX 655303
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75
100
500
TLV0831C, TLV0831I
TLV0832C, TLV0832I
3-VOLT 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL
SLAS148 – SEPTEMBER 1996
Differential Nonlinearity – LSB
TYPICAL CHARACTERISTICS
1
0.5
0
Vref = 3.3 V
TA = 25°C
F(CLK) = 250 kHz
VDD = 3.3 V
–0.5
–1
0
32
64
96
128
160
192
224
256
224
256
Output Code
Figure 11. Differential Nonlinearity With Output Code
Integral Nonlinearity – LSB
1
Vref = 3.3 V
TA = 25°C
F(CLK) = 250 kHz
VDD = 3.3 V
0.5
0
–0.5
–1
0
32
64
96
128
160
192
Output Code
Figure 12. Integral Nonlinearity With Output Code
Total Unadjusted Error – LSB
1
Vref = 3.3 V
TA = 25°C
F(CLK) = 250 kHz
VDD = 3.3 V
0.5
0
–0.5
–1
0
32
64
96
128
160
192
224
256
Output Code
Figure 13. Total Unadjusted Error With Output Code
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11
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