TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 D D D D D D 8-Bit Voltage Output DAC Programmable Settling Time vs Power Consumption 3 µs in Fast Mode 9 µs in Slow Mode Ultra Low Power Consumption: 900 µW Typ in Slow Mode at 3 V 2.1 mW Typ in Fast Mode at 3 V Differential Nonlinearity . . . <0.2 LSB Typ Compatible With TMS320 and SPI Serial Ports Power-Down Mode D D D Buffered High-Impedance Reference Input Monotonic Over Temperature Available in MSOP Package applications D D D D D Digital Servo Control Loops Digital Offset and Gain Adjustment Industrial Process Control Machine and Motion Control Devices Mass Storage Devices D OR DGK PACKAGE (TOP VIEW) description The TLV5623 is a 8-bit voltage output digital-toanalog converter (DAC) with a flexible 4-wire serial interface. The 4-wire serial interface allows glueless interface to TMS320, SPI, QSPI, and Microwire serial ports. The TLV5623 is programmed with a 16-bit serial string containing 4 control and 12 data bits. Developed for a wide range of supply voltages, the TLV5623 can operate from 2.7 V to 5.5 V. DIN SCLK CS FS 1 8 2 7 3 6 4 5 VDD OUT REFIN AGND The resistor string output voltage is buffered by a x2 gain rail-to-rail output buffer. The buffer features a Class AB output stage to improve stability and reduce settling time. The settling time of the DAC is programmable to allow the designer to optimize speed versus power dissipation. The settling time is chosen by the control bits within the 16-bit serial input string. A high-impedance buffer is integrated on the REFIN terminal to reduce the need for a low source impedance drive to the terminal. Implemented with a CMOS process, the TLV5623 is designed for single supply operation from 2.7 V to 5.5 V. The device is available in an 8-terminal SOIC package. The TLV5623C is characterized for operation from 0°C to 70°C. The TLV5623I is characterized for operation from – 40°C to 85°C. AVAILABLE OPTIONS PACKAGE TA SMALL OUTLINE† (D) 0°C to 70°C TLV5623CD MSOP (DGK) TLV5623CDGK – 40°C to 85°C TLV5623ID TLV5623IDGK † Available in tape and reel as the TLV5623CDR and the TLV5623IDR Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1999, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 functional block diagram _ 6 + REFIN 10 Serial Input Register 1 DIN 8 8-Bit Data Latch 2 SCLK 16 Cycle Timer 3 CS 4 FS 8 x2 7 OUT Update 2 Power-On Reset Speed/Power-Down Logic Terminal Functions TERMINAL NAME 2 NO. I/O DESCRIPTION AGND 5 CS 3 I Analog ground Chip select. Digital input used to enable and disable inputs, active low. DIN 1 I Serial digital data input FS 4 I Frame sync. Digital input used for 4-wire serial interfaces such as the TMS320 DSP interface. OUT 7 O DAC analog output REFIN 6 I Reference analog input voltage SCLK 2 I Serial digital clock input VDD 8 Positive power supply POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (VDD to AGND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Reference input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Digital input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to VDD + 0.3 V Operating free-air temperature range, TA: TLV5623C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C TLV5623I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to 85°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions VDD = 5 V VDD = 3 V Supply voltage voltage, VDD High-level digital input voltage, VIH Low-level digital input voltage, VIL Reference voltage, Vref to REFIN terminal Reference voltage, Vref to REFIN terminal VDD = 2.7 V to 5.5 V VDD = 2.7 V to 5.5 V MIN NOM MAX 4.5 5 5.5 V 2.7 3 3.3 V 2 V 0.8 VDD = 5 V (see Note 1) VDD = 3 V (see Note 1) AGND 2.048 AGND 1.024 2 10 Load resistance, RL VDD –1.5 VDD – 1.5 Clock frequency, fCLK Operating free-air free air temperature, temperature TA TLV5623I V V V kΩ Load capacitance, CL TLV5623C UNIT 100 pF 20 MHz 0 70 °C – 40 85 °C NOTE 1: Due to the x2 output buffer, a reference input voltage ≥ VDD/2 causes clipping of the transfer function. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) power supply PARAMETER IDD TEST CONDITIONS Power supply current MIN Power supply rejection ratio MAX UNIT VDD = 5 V, VREF = 2.048 V, No load, All inputs = AGND or VDD, DAC latch = 0x800 Fast 0.9 1.35 mA Slow 0.4 0.6 mA VDD = 3 V, VREF = 1.024 V No load, All inputs = AGND or VDD, DAC latch = 0x800 Fast 0.7 1.1 mA Slow 0.3 0.45 mA Power down supply current (see Figure 12) PSRR TYP 1 Zero scale See Note 2 –68 Full scale See Note 3 –68 Power on threshold voltage, POR 2 µA dB V NOTES: 2. Power supply rejection ratio at zero scale is measured by varying VDD and is given by: PSRR = 20 log [(EZS(VDDmax) – EZS(VDDmin))/VDDmax] 3. Power supply rejection ratio at full scale is measured by varying VDD and is given by: PSRR = 20 log [(EG(VDDmax) – EG(VDDmin))/VDDmax] POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) (continued) static DAC specifications RL = 10 kΩ, CL = 100 pF PARAMETER TEST CONDITIONS MIN Resolution TYP MAX UNIT 8 bits INL Integral nonlinearity See Note 4 ± 0.3 ± 0.5 LSB DNL Differential nonlinearity See Note 5 ± 0.07 ± 0.2 LSB EZS EZS TC Zero-scale error (offset error at zero scale) See Note 6 Zero-scale-error temperature coefficient See Note 7 EG Gain error See Note 8 Gain-error temperature coefficient See Note 9 ± 10 10 mV ppm/°C ± 0.6 10 % of FS voltage ppm/°C NOTES: 4. The relative accuracy or integral nonlinearity (INL) sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. 5. The differential nonlinearity (DNL) sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. 6. Zero-scale error is the deviation from zero voltage output when the digital input code is zero. 7. Zero-scale-error temperature coefficient is given by: EZS TC = [EZS (Tmax) – EZS (Tmin)]/Vref × 106/(Tmax – Tmin). 8. Gain error is the deviation from the ideal output (2Vref – 1 LSB) with an output load of 10 kΩ excluding the effects of the zero-error. 9. Gain temperature coefficient is given by: EG TC = [EG(Tmax) – EG (Tmin)]/Vref × 106/(Tmax – Tmin). output specifications PARAMETER VO TEST CONDITIONS Voltage output range MIN RL = 10 kΩ Output load regulation accuracy TYP 0 MAX VDD–0.1 ±0.1 RL = 2 kΩ, vs 10 kΩ ±0.25 UNIT V % of FS voltage reference input (REF) PARAMETER VI RI Input voltage range CI Input capacitance TEST CONDITIONS MIN TYP 0 MAX VDD–1.5 Input resistance 10 Reference input bandwidth 0 2 Vpp + 1.024 1 024 V dc REFIN = 0.2 Reference feed through REFIN = 1 Vpp at 1 kHz + 1.024 V dc (see Note 10) UNIT V MΩ 5 pF Slow 525 kHz Fast 1.3 MHz –75 dB NOTE 10: Reference feedthrough is measured at the DAC output with an input code = 0x000. digital inputs PARAMETER IIH IIL High-level digital input current CI Input capacitance 4 Low-level digital input current TEST CONDITIONS MIN TYP VI = VDD VI = 0 V 3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ±1 µA ±1 µA pF TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 operating characteristics over recommended operating free-air temperature range (unless otherwise noted) analog output dynamic performance PARAMETER TEST CONDITIONS ts(FS) (FS) Output settling time, time full scale RL = 10 kΩ,, See Note 11 CL = 100 pF, ts(CC) (CC) Output settling time time, code to code RL = 10 kΩ,, See Note 12 CL = 100 pF, SR S/N Slew rate RL = 10 kΩ,, See Note 13 CL = 100 pF,, Glitch energy Code transition from 0x7F0 to 0x800 MIN TYP MAX Fast 3 5.5 Slow 9 20 Fast 1 µs Slow 2 µs Fast 3.6 Slow 0.9 Signal to noise S/(N+D) Signal to noise + distortion THD Total harmonic distortion fs = 400 KSPS fout = 1.1 kHz, RL = 10 kΩ kΩ, pF, CL = 100 pF BW = 20 kHz Spurious free dynamic range UNIT µs V/µs 10 nV–s 57 dB 49 dB –50 dB 60 dB NOTES: 11. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of 0x020 to 0xFF0 or 0xFF0 to 0x020. Not tested, ensured by design. 12. Settling time is the time for the output signal to remain within ± 0.5 LSB of the final measured value for a digital input code change of one count. Not tested, ensured by design. 13. Slew rate determines the time it takes for a change of the DAC output from 10% to 90% full-scale voltage. digital input timing requirements MIN tsu(CS–FS) tsu(FS–CK) Setup time, CS low before FS↓ Setup time, FS low before first negative SCLK edge NOM MAX UNIT 10 ns 8 ns tsu(C16–FS) Setup time, sixteenth negative edge after FS low on which bit D0 is sampled before rising edge of FS 10 ns tsu(C16–CS) Setup time, sixteenth positive SCLK edge (first positive after D0 is sampled) before CS rising edge. If FS is used instead of the sixteenth positive edge to update the DAC, then the setup time is between the FS rising edge and CS rising edge. 10 ns twH twL Pulse duration, SCLK high 25 ns Pulse duration, SCLK low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) twH(FS) Hold time, data held valid after SCLK falling edge 5 ns 20 ns Pulse duration, FS high POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 PARAMETER MEASUREMENT INFORMATION ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ SCLK 1 2 tsu(D) DIN twH twL 3 4 5 15 16 th(D) D15 D14 D13 D12 tsu(FS-CK) D1 D0 tsu(C16-CS) tsu(CS-FS) CS twH(FS) tsu(C16-FS) FS Figure 1. Timing Diagram 6 ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎÎ POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 TYPICAL CHARACTERISTICS OUTPUT VOLTAGE vs LOAD CURRENT OUTPUT VOLTAGE vs LOAD CURRENT 2.004 2.002 3 V Fast Mode, SOURCE 2 5 V Slow Mode, SOURCE 4.005 VO – Output Voltage – V VO – Output Voltage – V 4.01 VDD = 3 V, Vref = 1 V, Full Scale 3 V Slow Mode, SOURCE 1.998 1.996 1.994 1.992 4 5 V Fast Mode, SOURCE 3.995 3.99 3.985 3.98 1.990 3.975 0 0.01 0.02 0.05 0.1 0.2 0.5 1 2 0 Load Current – mA 0.02 0.04 0.1 0.2 0.4 1 Load Current – mA Figure 2 4 OUTPUT VOLTAGE vs LOAD CURRENT 0.2 0.35 VDD = 3 V, Vref = 1 V, Zero Code 0.3 0.16 0.14 VO – Output Voltage – V VO – Output Voltage – V 2 Figure 3 OUTPUT VOLTAGE vs LOAD CURRENT 0.18 VDD = 5 V, Vref = 2 V, Full Scale 3 V Slow Mode, SINK 0.12 0.1 0.08 3 V Fast Mode, SINK 0.06 VDD = 5 V, Vref = 2 V, Zero Code 0.25 5 V Slow Mode, SINK 0.2 0.15 5 V Fast Mode, SINK 0.1 0.04 0.05 0.02 0 0 0 0.01 0.02 0.05 0.1 0.2 0.5 Load Current – mA 1 2 0 0.02 0.04 0.1 0.2 0.4 1 Load Current – mA Figure 4 2 4 Figure 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE SUPPLY CURRENT vs FREE-AIR TEMPERATURE 1 1 VDD = 5 V, Vref = 2 V, Full Scale I DD – Supply Current – mA I DD – Supply Current – mA VDD = 3 V, Vref = 1 V, Full Scale 0.8 Fast Mode 0.6 0.4 Fast Mode 0.8 0.6 0.4 Slow Mode Slow Mode 0.2 0.2 85 –55 –40 –25 0 25 40 70 TA – Free-Air Temperature – C° 125 85 –55 –40 –25 0 25 40 70 TA – Free-Air Temperature – C° Figure 6 Figure 7 TOTAL HARMONIC DISTORTION vs FREQUENCY TOTAL HARMONIC DISTORTION vs FREQUENCY 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale –10 THD – Total Harmonic Distortion – dB THD – Total Harmonic Distortion – dB 0 –20 –30 ––40 –50 –60 Fast Mode –70 –80 0 5 10 20 30 50 100 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale –10 –20 –30 ––40 –50 –60 Slow Mode –70 –80 0 5 f – Frequency – kHz 10 20 Figure 9 POST OFFICE BOX 655303 30 f – Frequency – kHz Figure 8 8 125 • DALLAS, TEXAS 75265 50 100 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 TYPICAL CHARACTERISTICS Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale –10 TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY THD – Total Harmonic Distortion And Noise – dB 0 –20 –30 ––40 –50 Fast Mode –60 –70 –80 0 Vref = 1 V dc + 1 V p/p Sinewave, Output Full Scale –10 –20 –30 ––40 –50 Slow Mode –60 –70 –80 0 5 10 20 30 50 100 0 5 f – Frequency – kHz 10 20 30 50 100 f – Frequency – kHz Figure 10 Figure 11 SUPPLY CURRENT vs TIME (WHEN ENTERING POWER-DOWN MODE) 900 800 I DD – Supply Current – µ A THD – Total Harmonic Distortion And Noise – dB TOTAL HARMONIC DISTORTION AND NOISE vs FREQUENCY 700 600 500 400 300 200 100 0 0 100 200 300 400 500 600 700 800 900 1000 T – Time – ns Figure 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 TYPICAL CHARACTERISTICS DNL – Differential Nonlinearity – LSB DIFFERENTIAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.10 0.08 0.06 0.04 0.02 0.00 –0.02 –0.04 –0.06 –0.08 –0.10 0 64 128 192 255 Digital Output Code Figure 13 INL – Integral Nonlinearity – LSB INTEGRAL NONLINEARITY vs DIGITAL OUTPUT CODE 0.5 0.4 0.3 0.2 0.1 –0.0 –0.1 –0.2 –0.3 –0.4 –0.5 0 64 128 Digital Output Code Figure 14 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 192 255 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 APPLICATION INFORMATION general function The TLV5623 is an 8-bit single supply DAC based on a resistor string architecture. The device consists of a serial interface, speed and power-down control logic, a reference input buffer, a resistor string, and a rail-to-rail output buffer. The output voltage (full scale determined by external reference) is given by: 2 REF CODE [V] 0x1000 Where REF is the reference voltage and CODE is the digital input value within the range of 0x000 to 0xFF0. Bits 3 to 0 must be set to zero. A power-on reset initially resets the internal latches to a defined state (all bits zero). serial interface The device has to be enabled with CS set to low. A falling edge of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling edges of SCLK. After 16 bits have been transferred or FS rises, the content of the shift register is moved to the DAC latch, which updates the voltage output to the new level. The serial interface of the TLV5623 can be used in two basic modes: D D Four wire (with chip select) Three wire (without chip select) Using chip select (four-wire mode), it is possible to have more than one device connected to the serial port of the data source (DSP or microcontroller). The interface is compatible with the TMS320 family. Figure 15 shows an example with two TLV5623s connected directly to a TMS320 DSP. TLV5623 TLV5623 CS FS DIN SCLK CS FS DIN SCLK TMS320 DSP XF0 XF1 FSX DX CLKX Figure 15. TMS320 Interface POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 APPLICATION INFORMATION serial interface (continued) If there is no need to have more than one device on the serial bus, then CS can be tied low. Figure 16 shows an example of how to connect the TLV5623 to a TMS320, SPI, or Microwire port using only three pins. TMS320 DSP TLV5623 FSX SPI FS DIN DX CLKX TLV5623 FS DIN SS MOSI SCLK SCLK Microwire FS DIN I/O SO SK SCLK CS TLV5623 SCLK CS CS Figure 16. Three-Wire Interface Notes on SPI and Microwire: Before the controller starts the data transfer, the software has to generate a falling edge on the I/O pin connected to FS. If the word width is 8 bits (SPI and Microwire), two write operations must be performed to program the TLV5623. After the write operation(s), the DAC output is updated automatically on the sixteenth positive clock edge. serial clock frequency and update rate The maximum serial clock frequency is given by: f SCLKmax +t ) twL(min) + 20 MHz wH(min) 1 The maximum update rate is: f UPDATEmax + 16 ǒ t 1 wH(min) Ǔ ) twL(min) + 1.25 MHz The maximum update rate is a theoretical value for the serial interface, since the settling time of the TLV5623 has to be considered also. data format The 16-bit data word for the TLV5623 consists of two parts: D D Control bits (D15 . . . D12) New DAC value (D11 . . . D0) D15 D14 D13 D12 X SPD PWR X X: don’t care SPD: Speed control bit. PWR: Power control bit. D11 1 → fast mode 1 → power down D10 D9 D8 D7 D6 D5 New DAC value (8 bits) 0 → slow mode 0 → normal operation In power-down mode, all amplifiers within the TLV5623 are disabled. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D4 D3 D2 D1 D0 0 0 0 0 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 APPLICATION INFORMATION TLV5623 interfaced to TMS320C203 DSP hardware interfacing Figure 17 shows an example how to connect the TLV5623 to a TMS320C203 DSP. The serial interface of the TLV5623 is ideally suited to this configuration, using a maximum of four wires to make the necessary connections. In applications where only one synchronous serial peripheral is used, the interface can be simplified even further by pulling CS low all the time as shown in the figure. TMS320C203 VDD TLV5623 FS FS DX DIN SCLK CLKX REF OUT REFIN CS AGND RLOAD Figure 17. TLV5623 to DSP Interface TLV5623 interfaced to MCS51 microcontroller hardware interfacing Figure 18 shows an example of how to connect the TLV5623 to an MCS51 compatible microcontroller. The serial DAC input data and external control signals are sent via I/O port 3 of the controller. The serial data is sent on the RxD line, with the serial clock output on the TxD line. P3.4 and P3.5 are configured as outputs to provide the chip select and frame sync signals for the TLV5623. MCS51 Controller TLV5623 RxD SDIN TxD SCLK P3.4 P3.5 CS FS VDD OUT REF REFIN RLOAD AGND Figure 18. TLV5623 to MCS51 Controller Interface MCS is a registered trademark of Intel Corporation POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 APPLICATION INFORMATION linearity, offset, and gain error using single ended supplies When an amplifier is operated from a single supply, the voltage offset can still be either positive or negative. With a positive offset, the output voltage changes on the first code change. With a negative offset, the output voltage may not change with the first code, depending on the magnitude of the offset voltage. The output amplifier attempts to drive the output to a negative voltage. However, because the most negative supply rail is ground, the output cannot drive below ground and clamps the output at 0 V. The output voltage then remains at zero until the input code value produces a sufficient positive output voltage to overcome the negative offset voltage, resulting in the transfer function shown in Figure 19. Output Voltage 0V DAC Code Negative Offset Figure 19. Effect of Negative Offset (single supply) This offset error, not the linearity error, produces this breakpoint. The transfer function would have followed the dotted line if the output buffer could drive below the ground rail. For a DAC, linearity is measured between zero-input code (all inputs 0) and full-scale code (all inputs 1) after offset and full scale are adjusted out or accounted for in some way. However, single supply operation does not allow for adjustment when the offset is negative due to the breakpoint in the transfer function. So the linearity is measured between full-scale code and the lowest code that produces a positive output voltage. power-supply bypassing and ground management Printed-circuit boards that use separate analog and digital ground planes offer the best system performance. Wire-wrap boards do not perform well and should not be used. The two ground planes should be connected together at the low-impedance power-supply source. The best ground connection may be achieved by connecting the DAC AGND terminal to the system analog ground plane, making sure that analog ground currents are well managed and there are negligible voltage drops across the ground plane. A 0.1-µF ceramic-capacitor bypass should be connected between VDD and AGND and mounted with short leads as close as possible to the device. Use of ferrite beads may further isolate the system analog supply from the digital power supply. Figure 20 shows the ground plane layout and bypassing technique. Analog Ground Plane 1 8 2 7 3 6 4 5 0.1 µF Figure 20. Power-Supply Bypassing 14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 APPLICATION INFORMATION definitions of specifications and terminology integral nonlinearity (INL) The relative accuracy or integral nonlinearity (INL), sometimes referred to as linearity error, is the maximum deviation of the output from the line between zero and full scale excluding the effects of zero code and full-scale errors. differential nonlinearity (DNL) The differential nonlinearity (DNL), sometimes referred to as differential error, is the difference between the measured and ideal 1 LSB amplitude change of any two adjacent codes. Monotonic means the output voltage changes in the same direction (or remains constant) as a change in the digital input code. zero-scale error (EZS) Zero-scale error is defined as the deviation of the output from 0 V at a digital input value of 0. gain error (EG) Gain error is the error in slope of the DAC transfer function. signal-to-noise ratio + distortion (S/N+D) S/N+D is the ratio of the rms value of the output signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels. spurious free dynamic range (SFDR) SFDR is the difference between the rms value of the output signal and the rms value of the largest spurious signal within a specified bandwidth. The value for SFDR is expressed in decibels. total harmonic distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental signal and is expressed in decibels. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PIN SHOWN 0.050 (1,27) 0.020 (0,51) 0.014 (0,35) 14 0.010 (0,25) M 8 0.008 (0,20) NOM 0.244 (6,20) 0.228 (5,80) 0.157 (4,00) 0.150 (3,81) Gage Plane 0.010 (0,25) 1 7 0°– 8° A 0.044 (1,12) 0.016 (0,40) Seating Plane 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) PINS ** 0.004 (0,10) 8 14 16 A MAX 0.197 (5,00) 0.344 (8,75) 0.394 (10,00) A MIN 0.189 (4,80) 0.337 (8,55) 0.386 (9,80) DIM 4040047 / D 10/96 NOTES: A. B. C. D. 16 All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). Falls within JEDEC MS-012 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TLV5623C, TLV5623I 2.7 V TO 5.5 V LOW POWER 8-BIT DIGITAL-TO-ANALOG CONVERTERS WITH POWER DOWN SLAS231 – JUNE 1999 MECHANICAL DATA DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,25 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/B 04/98 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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