DVCPro50 Decoder (v01.01.00) on TMS320C6678 SPRS807 – NOVEMBER 2011 • • • • • • • • • eXpressDSP Digital Media (XDM1.2) interface compliant Validated on TMS320C6678 EVM Supports both IEC61834 and SMPTE314M standards Progressive frame and Interlaced field decoding is supported Supports YUV 4:2:2 color formats. Supports decoding of D1 NTSC and D1 PAL bitsreams Transform 8x8 and 2-4-8 modes are supported Supports sample conversion from YUV 4:2:2 format to YUV 4:2:0 format Supports Multi-Channel and Multi-Instance functionality No dependency on operating system • • • • Supports frame level granularity with XDM APIs Error resilient codec does not support error concealment Supports ELF ABI Format Supports “ecpy” for EDMA & IRES interface. PRODUCT PREVIEW • Description DVCPro50 is a tape and file based video compression standard used in camcorders. DVCPro50 standard specifies interleaved storing of Audio and Video content in a single stream. DVCPro50 compressed audio and video frames are recorded in Digital Video Cassette (DVC). Original DVCPro50 specification is standardized within IEC 61834 families of standards. In addition to IEC standards for 50Mbps, SMPTE defines three standards, one for DV at 25 Mbps, one for 50Mbps and one for 100Mbps.This project is developed using Code Composer Studio version 4.2.3.00004 and using code generation tools version 7.2.6. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2011, Texas Instruments Incorporated 1 DVCPro50 Decoder (v01.01.00) on TMS320C6678 SPRS807 – NOVEMBER 2011 Summary of performance This section describes the performance of Standalone DVCPro50 Decoder tested on TMS320C6678 EVM. Table 1. Configuration Table CONFIGURATION ID Table 2. DV50_DEC_001 Cycles Information – Profiled on TMS320C6678 EVM with Code Generation Tools Version 7.2.6 PERFORMANCE STATISTICS (MEGA CYCLES PER SECOND) CONFIGURATION ID (3) TEST DESCRIPTION AVERAGE (4) (1) (2) (4) PEAK football_720x480_420p_300fr 472.4 489.9 container_720x576_422p_300fr 437.5 438.1 DV50_DEC_001 Note: 1. 2. 3. 2 Measured with CPU speed at 1GHz, DDR speed at 666.7MHz, Program memory, I/0 buffers in external memory and stack in internal L2 memory with cache configurations: 32KB L1P Program cache, 32KB L1D Data cache and 64KB L2 cache. There could be a variation of approximately 1-2% in the values. First 30frames have been considered for calculating the average and peak cycle consumption by the decoder library for each of the listed input files. The numbers are based on NTSC @30fps and PAL @25fps. PRODUCT PREVIEW DVCPro50 Decoder DVCPro50 Decoder (v01.01.00) on TMS320C6678 SPRS807 – NOVEMBER 2011 Table 3. Memory Statistics (TMS320C6678 External Memory) MEMORY STATISTICS(1)(2) PROGRAM MEMORY DV50_DEC_001 Note: 1. 2. 3. 4. 5. DATA MEMORY(4) (5) TOTAL PERSISTENT CONSTANT STACK 0.75 26.1 3 23.4 PRODUCT PREVIEW CONFIGURATION ID 53.25 All these memory requirements are for DVCPro50 decoder library only. They do not include any memory requirements from test application side. Stack, heap and code requirements for test-application are extra. All memory requirements are expressed in kilobytes (1K bytes = 1024 bytes). The memory requirements given in Table 3 are calculated for D1 PAL resolution. Typical input and output buffers for D1 PAL resolutions are as follows. Input Buffer: 282KB Output Buffer:810KB One output buffer is sufficient as a part of DPB i.e only Intra frames are allowed in the standard. Table 4. Internal Data Memory Split-up DATA MEMORY – INTERNAL(1) (3) CONFIGURATION ID LOCAL L2(2) CONSTANTS PERSISTENT SCRATCH 0 0 61 DV50_DEC_001 Note: 1. 2. 3. SHARED L2 TOTAL 0 61 Decoder stack is mapped to Local L2 memory and not included in the above table. Constant and Persistent memory can be corrupted by application provided application uses algorithm activate and deactivate APIs before using process and control APIs All memory requirements are expressed in kilobytes (1K bytes = 1024 bytes). Table 5. Cache/SRAM configuration NAME AVAILABLE CACHE SRAM L1p (Program Memory) 32K 32K 0K L1d( Data Memory) 32K 32K 0K L2 512K 64K 448K 3 DVCPro50 Decoder (v01.01.00) on TMS320C6678 SPRS807 – NOVEMBER 2011 EDMA Configuration TC Q TC 0 TC 1 TC 2 TC 3 TOTAL MAXIMUM(1) Usage Not Used Not Used Writes to DDR Writes to L2 - - Priority(2) - - 2 2 - - EDMA Channels - - 3 1 4 64 QDMA Channels - - 0 0 0 0 Num PARAMS - - 15 1 16 256 Notes: 1. Lesser number corresponds to higher TC priority. Default priority is 2. When different TC’s have same priority, the arbitration order is TC0 > TC1 > TC2 > TC3. 2. Max corresponds to the maximum number of EDMA/QDMA channels or maximum number of PARAMS available on the chip. It does NOT indicate the maximum number requested by the codec. 4 PRODUCT PREVIEW Table 6. DVCPro50 Decoder (v01.01.00) on TMS320C6678 SPRS807 – NOVEMBER 2011 References • • IEC 61834: Helical-scan digital video cassette recording system using 6,35 mm magnetic tape for consumer use (525-60, 625-50, 1125-60 and 1250-50 systems) SMPTE 314M: Data structure for DV-Based Audio, Data and Compressed Video 25 and 50 Mb/s User Guide for DVCPro50 decoder PRODUCT PREVIEW • Glossary Constants Elements that go into .const memory section Scratch Memory space that can be reused across different instances of the algorithm Shared Sum of Constants and Scratch Acronyms ABI Application Binary Interface DV Digital Video D1 720x576 resolution for PAL and 720x480 resolution for NTSC DMA Direct Memory Access DPB Decoded Picture Buffer ELF Executable and Linkable format EVM Evaluation Module EDMA Enhanced Direct Memory Access IRES Resource interface 5 PACKAGE OPTION ADDENDUM www.ti.com 1-Feb-2012 PACKAGING INFORMATION Orderable Device TMS320TEST1000 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan ACTIVE TBD (2) Lead/ Ball Finish Call TI MSL Peak Temp (3) Samples (Requires Login) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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