TI TMS470R1VF478GJZA

TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
O
O
O
– Standard Can Controller (SCC)
– 16-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
– Multi-Buffered Serial Peripheral Interface
(MibSPI)
– 128-Word Buffer
– Four DMA Channels
– Six Chip Selects
High-Performance Static CMOS Technology
TMS470R1x 16/32-Bit RISC Core (ARM7TDMI™)
– 24-MHz System Clock (60-MHz Pipeline)
– Independent 16/32-Bit Instruction Set
– Open Architecture With Third-Party Support
– Built-In Debug Module
– Utilizes Big-Endian Format
Integrated Memory
– 288K-Byte Program Flash
– One 32K-Byte Bank With Four 8K-Byte
Sectors
– One 256K-Byte Bank With Four 64K-Byte
Sectors
– Internal State Machine for Program and
Erase
– 16K-Byte Static RAM (SRAM)
O
High-End Timer (HET)
– 32 Programmable I/O Channels:
– 30 High-Resolution Pins
– 2 Standard-Resolution Pins
– High-Resolution Share Feature (XOR)
– High-End Timer RAM
– 128-Instruction Capacity
O
Operating Features
– Core Supply Voltage (VCC): 1.81 V - 2.05 V
– I/O Supply Voltage (VCCIO): 3.0 V - 3.6 V
– Low-Power Modes: STANDBY and HALT
– Industrial and Automotive Temperature
Ranges
O
Two 10-Bit, 16-Channel Multi-Buffered ADCs
– 128-Word FIFO Buffer
– Single- or Continuous-Conversion Modes
– 1.55 μs Minimum Sample and Conversion
Time
– Calibration Mode and Self-Test Features
O
470+ System Module
– 32-Bit Address Space Decoding
– Bus Supervision for Memory and
Peripherals
– Analog Watchdog (AWD) Timer
– Digital Watchdog (DWD) Timer
– Real-Time Interrupt (RTI)
– System Integrity and Failure Detection
O
Four External Interrupts
Flexible Interrupt Handling
3 Dedicated General-Purpose I/O (GIO) Pins,
1 Input-Only GIO Pin, and 62 Additional
Peripheral I/Os
Compatible ROM Device (Planned)
On-Chip Scan-Base Emulation Logic,
IEEE Standard 1149.1† (JTAG) Test-Access Port
176-Pin Plastic Ball Grid Array (GJZ Suffix)
Development System Support Tools Available
– Code Composer Studio™ Integrated
Development Environment (IDE)
– HET Assembler and Simulator
– Real-Time In-Circuit Emulation
– Flash Programming
O
Direct Memory Access (DMA) Controller
– 32 Control Packets and 16 Channels
O
Frequency-Modulated Phase-Locked Loop
(FMPLL)-Based Clock Module With Prescaler
– Multiply-by-4 or -8 Internal FMPLL Option
O
Six Communication Interfaces:
– Two Serial Peripheral Interfaces (SPIs)
– 255 Programmable Baud Rates
– Serial Communication Interface (SCI)
– 224 Selectable Baud Rates
– Asynchronous/Isosynchronous Modes
– High-End CAN Controller:
– 32-Mailbox Capacity
– Fully Compliant With CAN Protocol,
Version 2.0B
O
O
O
O
O
O
O
External Clock Prescale (ECP) Module
– Programmable Low-Frequency External
Clock (CLK)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Code Composer Studio is a trademark of Texas Instruments.
ARM7TDMI is a trademark of Advanced RISC Machines Limited (ARM).
All trademarks are the property of their respective owners.
† The test-access port is compatible with the IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary Scan Architecture
specification. Boundary scan is not supported on this device.
Copyright © 2006, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication
date. Products conform to specifications per the Texas
Instruments standard warranty. Production processing does
not necessarily include testing of all parameters.
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1
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
description
The TMS470R1VF478† device is a member of the Texas Instruments TMS470R1x family of general-purpose
16/32-bit reduced instruction set computer (RISC) microcontrollers. The VF478 microcontroller offers high
performance utilizing the high-speed ARM7TDMI 16/32-bit RISC central processing unit (CPU), resulting in a
high instruction throughput while maintaining greater code efficiency. The ARM7TDMI 16/32-bit RISC CPU
views memory as a linear collection of bytes numbered upwards from zero. The TMS470R1VF478 utilizes the
big-endian format where the most significant byte of a word is stored at the lowest numbered byte and the least
significant byte at the highest numbered byte.
High-end embedded control applications demand more performance from their controllers while maintaining
low costs. The VF478 RISC core architecture offers solutions to these performance and cost demands while
maintaining low power consumption.
The VF478 device contains the following:
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
ARM7TDMI 16/32-Bit RISC CPU
TMS470R1x system module (SYS) with 470+ enhancements [including a 16-channel direct-memory access
(DMA) controller
288K-byte flash
16K-byte SRAM
Frequency-modulated phase-locked loop (FMPLL) clock module
Analog watchdog (AWD) timer
Digital watchdog (DWD) timer
Real-time interrupt (RTI) module
Two serial peripheral interface (SPI) modules
One serial communications interface (SCI) module
High-end CAN controller (HECC)
Standard CAN controller (SCC)
Two 10-bit multi-buffered analog-to-digital converters (MibADC), 16-input channels
Multi-buffered serial peripheral interface (MibSPI) module
High-end timer (HET) controlling 32 I/Os
External Clock Prescale (ECP) module
Up to 65 I/O pins and 1 input-only pin
The functions performed by the 470+ system module (SYS) include: address decoding; memory protection;
memory and peripherals bus supervision; reset and abort exception management; prioritization for all internal
interrupt sources; device clock control; and parallel signature analysis (PSA). This data sheet includes devicespecific information such as memory and peripheral select assignment, interrupt priority, and a device memory
map. For a more detailed functional description of the SYS module, see the TMS470R1x System Module
Reference Guide (literature number SPNU189).
The VF478 memory includes general-purpose SRAM supporting single-cycle read/write accesses in byte,
half-word, and word modes.
The flash memory on this device is a nonvolatile, electrically erasable and programmable memory implemented
with a 32-bit-wide data bus interface.The flash operates with a system clock frequency of up to 24 MHz. When
in pipeline mode, the flash operates with a system clock frequency of up to 60 MHz. For more detailed information
on the flash, see the flash section of this data sheet and the TMS470R1x F05 Flash Reference Guide (literature
number SPNU213).
† Throughout the remainder of this document, the TMS470R1VF478 device name shall be referred to as TMS470R1VF478 or VF478.
2
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
description (continued)
The VF478 device has seven communication interfaces: a MibSPI, two SPIs, an HECC, an SCC, and an SCI.
The SPI provides a convenient method of serial interaction for high-speed communications between similar
shift-register type devices. The SCI is a full-duplex, serial I/O interface intended for asynchronous communication between the CPU and other peripherals using the standard Non-Return-to-Zero (NRZ) format. The HECC
uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with
robust communication rates of up to1 megabit per second (Mbps). The HECC is ideal for applications operating
in harsh environments (e.g., automotive and industrial fields) that require reliable serial communication or
multiplexed wiring. The SCC uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 Megabit per second (Mbps). The SCC is
ideal for applications operating in noisy and harsh environments (e.g. automotive and industrial fields) that
require reliable serial communication or multiplexed wiring. The MibSPI is a high-speed synchronous serial
input/output port that allows a serial bit stream of programmed length to be shifted into and out of the device
at a programmed bit-transfer rate. For more detailed functional information on the SPI, SCI, and HECC peripherals, see the specific reference guides (literature numbers SPNU195, SPNU196, and SPNU197, respectively).
For more information on the MibSPI peripheral, see the TMS470R1x Multi-Buffered Serial Peripheral Interface
(MibSPI) Reference Guide (literature number SPNU217).
The HET is an advanced intelligent timer that provides sophisticated timing functions for real-time applications.
The timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and
an attached I/O port. The HET can be used for compare, capture, or general-purpose I/O. It is especially well
suited for applications requiring multiple sensor information and drive actuators with complex and accurate
time pulses. For more detailed functional information on the HET, see the TMS470R1x High-End Timer (HET)
Reference Guide (literature number SPNU199). The VF478 HET peripheral contains the XOR-share feature.
This feature allows two adjacent HET high- resolution channels to be XORed together, making it possible to
output smaller pulses than a standard HET. For more detailed information on the HET XOR-share feature, see
the TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199).
The VF478 device has two 10-bit-resolution sample-and-hold MibADCs. The MibADC channels can be converted individually or can be grouped by software for sequential conversion sequences. There are three separate
groupings, two of which are triggerable by an external event. Each sequence can be converted once when
triggered or configured for continuous conversion mode. For more detailed functional information on the
MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature
number SPNU206).
The frequency-modulated phase-locked loop (FMPLL) clock module contains a phase-locked loop, a clockmonitor circuit, a clock-enable circuit, and a prescaler (with prescale values of 1–8). The function of the FMPLL
is to multiply the external frequency reference to a higher frequency for internal use. The FMPLL provides
ACLK‡ to the system (SYS) module. The SYS module subsequently provides system clock (SYSCLK), realtime interrupt clock (RTICLK), CPU clock (MCLK), and peripheral interface clock (ICLK) to all other VF478
device modules. For more detailed functional information on the FMPLL, see the TMS470R1x FrequencyModulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221).
† SAE Standard J1850 Class B Data Communication Network Interface
‡ ACLK should not be confused with the MibADC internal clock, ADCLK. ACLK is the continuous system clock from an external resonator/crystal
reference.
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3
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
device characteristics
The TMS470R1VF478 device is a derivative of the F05 system emulation device SE470R1VB8AD. Table 1
identifies all the characteristics of the TMS470R1VF478 device except the SYSTEM and CPU, which are
generic. The COMMENTS column aids the user in software-programming and references device-specific
information.
Table 1. Device Characteristics
CHARACTERISTICS
DEVICE DESCRIPTION
TMS470R1VF478
COMMENTS FOR VF478
MEMORY
For the number of memory selects on this device, see the Memory Selection Assignment table (Table 2).
Flash is pipeline-capable
INTERNAL
MEMORY
288K-Byte flash
16K-Byte SRAM
The VF478 RAM is implemented in one 16K array selected by two memoryselect signals (see the Memory Selection Assignment table, Table 2).
PERIPHERALS
For the device-specific interrupt priority configurations, see the Interrupt Priority table (Table 6). And for the 1K peripheral address ranges and
their peripheral selects, see the VF478 Peripherals, System Module, and Flash Base Addresses table (Table 4).
4
CLOCK
FMPLL
GENERAL-PURPOSE
I/Os
3 I/O
1 Input only
SCI
1 (3-pin)
CAN
(HECC and/or SCC)
1 HECC, 1 SCC
SPI
(5-pin, 4-pin or 3-pin)
2 (5-pin)
MibSPI
(5-pin, 4-pin or 3-pin)
1 (5-pin)
HET with
XOR Share
32 I/O
HET RAM
128-Instruction Capacity
MibADC
2 10-bit, 16-channel
128-word FIFO
CORE VOLTAGE
1.8 V
I/O VOLTAGE
3.3 V
PINS
176
PACKAGE
GJZ
FMPLL has no external loop filter pins.
Only four (4) external pins
High-end CAN controller and standard CAN controller
SPI1 and SPI2
The high-resolution (HR) SHARE feature allows even HR pins to share the next
higher odd HR pin structures. This HR sharing is independent of whether or not
the odd pin is available externally. If an odd pin is available externally and shared,
then the odd pin can only be used as a general-purpose I/O. For more information
on HR SHARE, see the TMS470R1x High-End Timer (HET) Reference Guide
(literature number SPNU199).
MibADC1 and MibADC2
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
functional block diagram
External Pins
FLTP1
OSCIN
FLASH
(288K Bytes)
8 Sectors
FMPLL
and OSC
RAM
(16K Bytes)
OSCOUT
Crystal
External Pins
VCCP
PLLDIS
FLTP2
ADIN1[15:0]
TEST
CPU Address/Data Bus
ADEVT1
MibADC1
with
128-Word
FIFO
TRST
ADREFLO1
VCCAD1
TMS470R1x
CPU
TCK
ADREFHI1
VSSAD1
TDI
ADIN2[15:0]
TDO
ADEVT2
TMS
TMS2
MibADC2
with
128-Word
FIFO
TMS470R1x 470+ SYSTEM MODULE
AWD
PORRST
ICE
Crusher
Expansion Address/Data Bus
RST
DMA Controller
16 Channels
CLKOUT
EMU1
GIOA[1]/INT[1]/
ECLK
Analog
Watchdog
(AWD)
Digital
Watchdog
(DWD)
EMU0
ADREFHI2
ADREFLO2
VCCAD2
VSSAD2
HET with
XOR Share
HET [31:0]
CANHTX
HECC
CANHRX
CANSTX
SCC
ECP
CANSRX
SCICLK
SCI
SCIRXD
SCITXD
SPI3SOMI
GIOA[0]/INT[0]†
GIO
SPI3SIMO
GIOA[2:3]/INT[2:3]
MibSPI
SPI2
SPI3CLK
SPI3ENA
SPI1
SPI1SCS
SPI1ENA
SPI1CLK
SPI1SIMO
SPI2SCS
SPI1SOMI
SPI2ENA
SPI2CLK
SPI2SIMO
SPI2SOMI
SPI3SCS[5:0]
† GIOA[0]/INT[0] is an input-only GIO pin.
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5
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
Terminal Functions
TERMINAL
NAME
BALL NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
HIGH-END TIMER (HET)
HET[0]
H1
HET[1]
J1
HET[2]
M5
HET[3]
M4
HET[4]
M3
HET[5]
N3
HET[6]
N4
HET[7]
N5
HET[8]
A14
HET[9]
A13
HET[10]
M8
HET[11]
N8
HET[12]
P8
HET[13]
P9
HET[14]
N7
HET[15]
P7
HET[16]
M6
HET[17]
N6
HET[18]
B14
HET[19]
C14
HET[20]
C13
HET[21]
B12
HET[22]
D13
HET[23]
M7
HET[24]
G14
HET[25]
H2
HET[26]
J2
HET[27]
B13
The VF478 device has both the logic and registers for a full 32-I/O HET
implemented.
Timer input capture or output compare. The HET[31:0] applicable pins can be
programmed as general-purpose input/output (GIO) pins. HET[29:0] are highresolution pins and HET[31:30] are loop-resolution pins.
3.3-V I/O
IPD
The high-resolution (HR) SHARE feature allows even HR pins to share the next
higher odd HR pin structures. This HR sharing is independent of whether or not
the odd pin is available externally. If an odd pin is available externally and shared,
then the odd pin can only be used as a general-purpose I/O. For more information
on HR SHARE, see theTMS470R1x High-End Timer (HET) Reference Guide
(literature number SPNU199).
HET[28]
J13
HET[29]
H13
HET[30]
G13
HET[31]
H14
CANHRX
B11
3.3-V I/O
HECC receive pin or GIO pin
CANHTX
B10
3.3-V I/O
HECC transmit pin or GIO pin
CANSRX
K1
3.3-V I/O
SCC receive pin or GIO pin
CANSTX
L1
3.3-V I/O
SCC transmit pin or GIO pin
HIGH-END CAN CONTROLLER (HECC)
STANDARD CAN CONTROLLER (SCC)
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
6
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
BALL NO.
INTERNAL
PULLUP/
PULLDOWN§
TYPE†‡
DESCRIPTION
GENERAL-PURPOSE I/O (GIO)
GIOA[0]/INT0
K14
GIOA[1]/INT1/ECLK
J14
GIOA[2]/INT2
J4
GIOA[3]/INT3
J3
ADEVT1
B2
ADIN1[0]
D4
ADIN1[1]
D3
ADIN1[2]
D2
ADIN1[3]
D1
ADIN1[4]
C5
ADIN1[5]
C3
ADIN1[6]
C2
3.3-V I
General-purpose input/output pins. GIOA[0]/INT[0] is an input-only pin.
GIOA[3:0]/INT[3:0] are interrupt-capable pins.
3.3-V I/O
IPD
GIOA[1]/INT[1]/ECLK pin is multiplexed with the external clock-out function
of the external clock prescale (ECP) module.
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER 1 (MibADC1)
ADIN1[7]
C1
ADIN1[8]
G4
ADIN1[9]
G2
ADIN1[10]
E4
ADIN1[11]
D5
ADIN1[12]
G3
3.3-V I/O
IPD
3.3-V I
MibADC1 event input. Can be programmed as a GIO pin.
MibADC1 analog input pins
ADIN1[13]
F4
ADIN1[14]
E3
ADIN1[15]
C4
ADREFHI1
E2
3.3-V REF I
MibADC1 module high-voltage reference input
ADREFLO1
F3
GND REF I
MibADC1 module low-voltage reference input
VCCAD1
E1
3.3-V
PWR
MibADC1 analog supply voltage
VSSAD1
F1
GND
MibADC1 analog ground reference
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER 2 (MibADC2)
ADEVT2
K13
ADIN2[0]
K12
ADIN2[1]
L10
ADIN2[2]
L11
ADIN2[3]
L12
ADIN2[4]
L13
ADIN2[5]
L14
ADIN2[6]
K11
ADIN2[7]
M10
ADIN2[8]
M11
ADIN2[9]
M12
ADIN2[10]
M13
3.3-V I/O
3.3-V I
IPD
MibADC2 event input. Can be programmed as a GIO pin.
MibADC2 analog input pins
ADIN2[11]
M14
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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7
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
BALL NO.
INTERNAL
PULLUP/
PULLDOWN§
TYPE†‡
DESCRIPTION
MULTI-BUFFERED ANALOG-TO-DIGITAL CONVERTER 2 (MibADC2) (CONTINUED)
ADIN2[12]
N10
ADIN2[13]
N11
ADIN2[14]
N14
3.3-V I
MibADC2 analog input pins
ADIN2[15]
P14
ADREFH2I
N13
3.3-V REF I
MibADC2 module high-voltage reference input
ADREFLO2
N12
GND REF I
MibADC2 module low-voltage reference input
VCCAD2
P13
3.3-V
PWR
VSSAD2
P12
GND
MibADC2 analog supply voltage
MibADC2 analog ground reference
SERIAL PERIPHERAL INTERFACE 1 (SPI1)
SPI1CLK
N1
SPI1 clock. SPI1CLK can be programmed as a GIO pin.
SPI1ENA
L5
SPI1 chip enable. SPI1ENA can be programmed as a GIO pin.
SPI1SCS
L6
SPI1 slave chip select. SPI1SCS can be programmed as a GIO pin.
3.3-V I/O
IPD
SPI1SIMO
M2
SPI1 data stream. Slave in/master out. SPI1SIMO can be programmed as a
GIO pin.
SPI1SOMI
N2
SPI1 data stream. Slave out/master in. SPI1SOMI can be programmed as a
GIO pin.
SPI2CLK
D12
SPI2 clock. SPI2CLK can be programmed as a GIO pin.
SPI2ENA
D10
SPI2 chip enable. SPI2ENA can be programmed as a GIO pin.
SPI2SCS
C11
SERIAL PERIPHERAL INTERFACE 2 (SPI2)
SPI2 slave chip select. SPI2SCS can be programmed as a GIO pin.
3.3-V I/O
IPD
SPI2SIMO
C12
SPI2 data stream. Slave in/master out. SPI2SIMO can be programmed as a
GIO pin.
SPI2SOMI
D11
SPI2 data stream. Slave out/master in. SPI2SOMI can be programmed as a
GIO pin.
SPI3CLK
A10
SPI3 clock. SPI3CLK can be programmed as a GIO pin.
SPI3ENA
C7
SPI3 chip enable. SPI3ENA can be programmed as a GIO pin.
SPI3SCS5
B1
SPI3 slave chip select 5. SPI2SCS5 can be programmed as a GIO pin.
SPI3SCS4
A1
SPI3 slave chip select 4. SPI2SCS4 can be programmed as a GIO pin.
SPI3SCS3
A2
SPI3 slave chip select 3. SPI2SCS3 can be programmed as a GIO pin.
SPI3SCS2
A3
SPI3SCS1
B4
SPI3 slave chip select 1. SPI2SCS1 can be programmed as a GIO pin.
SPI3SCS0
A4
SPI3 slave chip select 0. SPI2SCS0 can be programmed as a GIO pin.
SPI3SIMO
A9
SPI3 data stream. Slave in/master out. SPI3SIMO can be programmed as a
GIO pin.
SPI3SOMI
A8
SPI3 data stream. Slave out/master in. SPI3SOMI can be programmed as a
GIO pin.
OSCIN
P4
1.8-V I
Crystal connection pin or external clock input
OSCOUT
P3
1.8-V O
External crystal connection pin
MULTI-BUFFER SERIAL PERIPHERAL INTERFACE (SPI3)
3.3-V I/O
IPD
SPI3 slave chip select 2. SPI2SCS2 can be programmed as a GIO pin.
FREQUENCY-MODULATED PLL (FMPLL)
Enable/disable the FMPLL. The FMPLL can be bypassed and the oscillator
becomes the system clock. If not in bypass mode, TI recommends that this
pin be connected to ground or pulled down to ground by an external resistor.
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
† IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
PLLDIS
8
D8
3.3-V I
IPD
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
BALL NO.
TYPE†‡
INTERNAL
PULLUP/
PULLDOWN§
DESCRIPTION
SERIAL COMMUNICATIONS INTERFACE (SCI)
SCICLK
G7
3.3-V I/O
SCIRXD
B9
3.3-V I/O
IPD
SCI clock. SCICLK can be programmed as a GIO pin.
SCI data receive. SCIRXD can be programmed as a GIO pin.
SCITXD
B8
3.3-V I/O
SCI data transmit. SCITXD can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
CLKOUT
F8
3.3-V I/O
IPD
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of
SYSCLK, ICLK, or MCLK.
PORRST
N9
3.3-V I
IPD
Input master chip power-up reset. External VCC monitor circuitry must assert a
power-on reset.
IPU
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset.
On this pin, the output buffer is implemented as an open drain (drives low only).
To ensure an external reset is not arbitrarily generated, TI recommends that an
external pullup resistor be connected to this pin.
RST
J6
3.3-V I/O
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a system reset if the WD KEY
is not written in time by the system, providing an external RC network circuit is
connected.
AWD
D9
If the user is not using AWD, TI recommends that this pin be connected to ground
or pulled down to ground by an external resistor.
3.3-V I/O
For more details on the external RC network circuit, see the TMS470R1x System
Module Reference Guide (literature number SPNU189) and the application note
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection
Constraints (literature number SPNA005).
TEST/DEBUG (T/D)
EMU0
H3
3.3-V I/O
IPU
EMU1
H4
3.3-V I/O
IPU
Emulation pin 0
Emulation pin 1
TCK
C8
3.3-V I
IPD
Test clock. TCK controls the test hardware (JTAG).
TDI
C10
3.3-V I
IPU
Test data in. TDI inputs serial data to the test instruction register, test data
register, and programmable test address (JTAG).
TDO
C9
3.3-V O
IPD
Test data out. TDO outputs serial data from the test instruction register, test data
register, identification register, and programmable test address (JTAG).
TEST
J9
3.3-V I
IPD
Test enable. Reserved for internal use only. TI recommends that this pin be
connected to ground or pulled down to ground by an external resistor.
TMS
B3
3.3-V I
IPU
Serial input for controlling the state of the CPU test access port (TAP) controller
(JTAG).
TMS2
G8
3.3-V I
IPU
Serial input for controlling the second TAP. TI recommends that this pin be
connected to VCCIO or pulled up to VCCIO by an external resistor.
TRST
J12
3.3-V I
IPD
Test hardware reset to TAP1 and TAP2. IEEE Standard 1149-1 (JTAG)
Boundary-Scan Logic. TI recommends that this pin be pulled down to ground
by an external resistor.
FLASH
FLTP1
H8
NC
Flash test pad 1. For proper operation, this pin must not be connected
[no connect (NC)].
FLTP2
H7
NC
Flash test pad 2. For proper operation, this pin must not be connected
[no connect (NC)].
VCCP
M1
3.3-V PWR
Flash external pump voltage (3.3 V)
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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9
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
BALL NO.
VCC
A5
D6
F11
F14
K4
K2
L7
P1
VCCIO
A7
A11
D14
G1
P6
P10
TYPE†‡
1.8-V
PWR
INTERNAL
PULLUP/
PULLDOWN§
SUPPLY VOLTAGE CORE (1.8 V)
DESCRIPTION
Core logic supply voltage
SUPPLY VOLTAGE DIGITAL I/O (3.3 V)
3.3-V
PWR
Digital I/O supply voltage
SUPPLY GROUND CORE
VSS
VSS
A6
D7
E11
E14
L2
L4
L8
P2
F6
F7
F9
G6
G9
H6
H9
H11
J7
J8
J11
L9
M9
GND
Core supply ground reference
Core supply ground reference
GND
These VSS balls in the center of the package act as both electrical grounds and
thermal relief. They are all tied to ground, which is the method used for thermal
dissipation
SUPPLY GROUND DIGITAL I/O
VSSIO
A12
B7
E13
F2
P5
P11
GND
Digital I/O supply ground reference
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
10
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
Terminal Functions (Continued)
TERMINAL
NAME
NC
BALL NO.
K3
L3
B5
B6
C6
E12
F12
F13
G11
G12
H12
TYPE†‡
NC
INTERNAL
PULLUP/
PULLDOWN§
NO CONNECTS
DESCRIPTION
No connects.
† I = input, O = output, PWR = power, GND = ground, REF = reference voltage, NC = no connect
‡ All I/O pins, except RST, are configured as inputs while PORRST is low and immediately after PORRST goes high.
§ IPD = internal pulldown, IPU = internal pullup (all internal pullups and pulldowns are active on input pins, independent of the PORRST state.)
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11
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
VF478 DEVICE-SPECIFIC INFORMATION
memory
Figure 1 shows the memory map of the VF478 device.
Memory (4G Bytes)
SYSTEM with PSA, CIM, RTI, DEC,
DMA, MMC, DWD
System Module Control Registers
(512K Bytes)
Reserved
0xFFFF_FFFF
HET
Peripheral Control Registers
(512K Bytes)
SPI1
0xFFF0_0000
0xFFEF_FFFF
0xFFE8_4024
0xFFE8_4023
0xFFE8_4000
0xFFE8_3FFF
SCI
Reserved
MibADC2
Flash Control Registers
MibADC1
Reserved
GIO/ECP
MPU Control Registers
HECC
Reserved
HECC RAM
SCC
0xFFE0_0000
RAM
(16K Bytes)
SCC RAM
Reserved
0xFFF7_F000
0xFFF7_EC00
0xFFF7_E800
0xFFF7_E400
0xFFF7_E000
0xFFF7_DC00
0xFFF7_D400
0xFFF7_CC00
0xFFF7_C800
0xFFF0_C000
0x0000_001F
IRQ
Reserved
Data Abort
Prefetch Abort
Exception, Interrupt, and
Reset Vectors
0xFFF7_F100
0xFFF7_D500
FIQ
0x0000_0020
0x0000_001F
0xFFF7_F400
MibSPI
Reserved
FLASH
(288K Bytes)
8 Sectors
0xFFF7_F800
0xFFF7_D800
Reserved
Program
and
Data Area
0xFFF7_FC00
Reserved
SPI2
0x0000_0000
0xFFFF_FD00
0xFFF8_0000
0xFFF8_0000
0xFFF7_FFFF
0xFFE8_C000
0xFFE8_BFFF
0xFFE8_8000
0xFFE8_7FFF
0xFFFF_FFFF
Software Interrupt
Undefined Instruction
Reset
0x0000_001C
0x0000_0018
0x0000_0014
0x0000_0010
0x0000_000C
0x0000_0008
0x0000_0004
0x0000_0000
NOTES: A. Memory addresses are configurable by the system (SYS) module within the range of 0x0000_0000 to 0xFFE0_0000.
B. The CPU registers are not a part of the memory map.
Figure 1. Memory Map
12
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
memory selects
Memory selects allow the user to address memory arrays (i.e., flash, RAM, and HET RAM) at user-defined
addresses. Each memory select has its own set (low and high) of memory base address registers (MFBAHRx
and MFBALRx) that, together, define the array’s starting (base) address, block size, and protection.
The base address of each memory select is configurable to any memory address boundary that is a multiple
of the decoded block size. For more information on how to control and configure these memory select registers,
see the bus structure and memory sections of the TMS470R1x System Module Reference Guide (literature
number SPNU189).
For the memory selection assignments and the memory selected, see Table 2.
Table 2. Memory Selection Assignment
MEMORY
SELECT
MEMORY SELECTED
(ALL INTERNAL)
0 (fine)
FLASH
1 (fine)
FLASH
2 (fine)
MEMORY
SIZE
288K
RAM
16K†
3 (fine)
RAM
MPU
MEMORY BASE ADDRESS REGISTER
NO
MFBAHR0 and MFBALR0
NO
MFBAHR1 and MFBALR1
YES, illegal writes
blocked
MFBAHR2 and MFBALR2
YES, illegal writes
blocked
MFBAHR3 and MFBALR3
STATIC MEM CTL
REGISTER
4 (fine)
HET RAM
1.5K
No
MFBAHR4 and MFBALR4
SMCR1
5 (fine)
MibSPI RAM
1K
No
MFBAHR5 and MFBALR5
SMCR2
MibADC1 RAM
1K
No
n/a
MibADC2 RAM
1K
No
n/a
† The starting addresses for both RAM memory-select signals cannot be offset from each other by a multiple of the user-defined block size in the
memory-base address register.
JTAG security module
The VF478 device includes a JTAG security module to provide maximum security to the memory contents. The
visible unlock code can be in the OTP sector or in the first bank of the user-programmable memory. For the
VF478, the visible unlock code is in the OTP sector at address 0x0000_01F8.
RAM
The VF478 device contains 16K bytes of internal static RAM configurable by the SYS module to be addressed
within the range of 0x0000_0000 to 0xFFE0_0000. This VF478 RAM is implemented in one 16K array selected
by two memory-select signals. This VF478 configuration imposes an additional constraint on the memory map
for RAM; the starting addresses for both RAM memory selects cannot be offset from each other by the multiples
of the size of the physical RAM (i.e., 16K for the VF478). The VF478 RAM is addressed through memory
selects 2 and 3.
The RAM can be protected by the memory protection unit (MPU) portion of the SYS module, allowing the user
finer blocks of memory protection than is allowed by the memory selects. The MPU is ideal for protecting an
operating system while allowing access to the current task. For more detailed information on the MPU portion
of the SYS module and memory protection, see the memory section of the TMS470R1x System Module
Reference Guide (literature number SPNU189).
F05 flash
The F05 flash memory is a nonvolatile, electrically erasable and programmable memory implemented with a
32-bit-wide data bus interface. The F05 flash has an external state machine for programming and erase
functions. See the flash read and flash program and erase sections below.
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13
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
flash protection keys
The VF478 device provides flash protection keys. These four 32-bit protection keys prevent program/erase/
compaction operations from occurring until after the four protection keys have been matched by the CPU loading
the correct user keys into the FMPKEY control register. The protection keys on the VF478 are located in the
last four words of the first 8K sector. For more detailed information on the flash protection keys and the FMPKEY
control register, see the Optional Quadruple Protection Keys and Programming the Protection Keys portions
of the TMS470R1x F05 Flash Reference Guide (literature number SPNU213).
flash read
The VF478 flash memory is configurable by the SYS module to be addressed within the range of 0x0000_0000
to 0xFFE0_0000. The flash is addressed through memory selects 0 and 1.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
flash pipeline mode
When in pipeline mode, the flash operates with a system clock of up to 60 MHz (versus a system clock in normal
mode of up to 24 MHz). Flash in pipeline mode is capable of accessing 64-bit words and provides two 32-bit
pipelined words to the CPU. Also, in pipeline mode, the flash can be read with no wait states when memory
addresses are contiguous (after the initial 1- or 2-wait-state reads).
NOTE
After a system reset, pipeline mode is disabled (ENPIPE bit [FMREGOPT.0] is a 0). In other words, the
VF478 device powers up and comes out of reset in non-pipeline mode. Furthermore, setting the flash
configuration mode bit (GBLCTRL.4) will override pipeline mode.
flash program and erase
The VF478 device flash has one 32K-byte banks that consists of a total of four sectors, and a 256K-byte bank
consisting of four sectors. These banks and sectors are sized as in Table 3.
Table 3. Flash Sector Addresses
SECTOR
NO.
SEGMENT
LOW ADDRESS
OTP
2K Bytes
0x0000_0000
0x0000_07FF
0
8K Bytes
0x0000_0000
0x0000_1FFF
1
8K Bytes
0x0000_2000
0x0000_3FFF
2
8K Bytes
0x0000_4000
0x0000_5FFF
3
8K Bytes
0x0000_6000
0x0000_7FFF
0
64K Bytes
0x0004_0000
0x0004_FFFF
1
64K Bytes
0x0005_0000
0x0005_FFFF
2
64K Bytes
0x0006_0000
0x0006_FFFF
3
64K Bytes
0x0007_0000
0x0007_FFFF
HIGH ADDRESS
MEMORY ARRAYS
(OR BANKS)
BANK0
(32K Bytes)
BANK1
(256K Bytes)
The minimum size for an erase operation is one sector. The maximum size for a program operation is one
16-bit word.
NOTE
The flash external pump voltage (VCCP) is required for all operations (program, erase, and read).
Execution can occur from one bank while programming/erasing any or all sectors of another bank. However,
execution cannot occur from any sector within a bank that is being programmed or erased.
14
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
NOTE
When the OTP sector is enabled, the rest of flash memory is disabled. The OTP memory can only be
read or programmed from code executed out of RAM.
For more detailed information on flash program and erase operations, see the TMS470R1x F05 Flash Reference
Guide (literature number SPNU213).
HET RAM
The VF478 device contains HET RAM. The HET RAM has a 128-instruction capability. The HET RAM is
configurable by the SYS module to be addressed within the range of 0x0000_0000 to 0xFFE0_0000. The HET
RAM is addressed through memory select 4.
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15
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
peripheral selects and base addresses
The VF478 device uses ten of the sixteen peripheral selects to decode the base addresses of the peripherals.
These peripheral selects are fixed and transparent to the user since they are part of the decoding scheme used
by the SYS module.
Control registers for the peripherals, SYS module, and flash begin at the base addresses shown in Table 4.
Table 4. VF478 Peripherals, System Module, and Flash Base Addresses
CONNECTING MODULE
16
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
SYSTEM
0xFFFF_FFCC
0xFFFF_FFFF
N/A
RESERVED
0xFFFF_FF70
0xFFFF_FFCB
N/A
DWD
0xFFFF_FF60
0xFFFF_FF6F
N/A
PSA
0xFFFF_FF40
0xFFFF_FF5F
N/A
CIM
0xFFFF_FF20
0xFFFF_FF3F
N/A
RTI
0xFFFF_FF00
0xFFFF_FF1F
N/A
DMA
0xFFFF_FE80
0xFFFF_FEFF
N/A
DEC
0xFFFF_FE00
0xFFFF_FE7F
N/A
MMC
0xFFFF_FD00
0xFFFF_FD7F
N/A
RESERVED
0xFFFF_FC00
0xFFFF_FCFF
N/A
RESERVED
0xFFFF_FB00
0xFFFF_FBFF
N/A
RESERVED
0xFFFF_FA00
0xFFFF_FAFF
N/A
DMA CMD BUFFER
0xFFFF_F800
0xFFFF_F9FF
N/A
RESERVED
0xFFF8_0000
0xFFFF_F7FF
N/A
RESERVED
0xFFF7_FD00
0xFFF7_FFFF
HET
0xFFF7_FC00
0xFFF7_FCFF
RESERVED
0xFFF7_F900
0xFFF7_FBFF
SPI1
0xFFF7_F800
0xFFF7_F8FF
RESERVED
0xFFF7_F500
0xFFF7_F7FF
SCI
0xFFF7_F400
0xFFF7_F4FF
RESERVED
0xFFF7_F200
0xFFF7_F3FF
MibADC2
0xFFF7_F100
0xFFF7_F1FF
MibADC1
0xFFF7_F000
0xFFF7_F0FF
ECP
0xFFF7_EF00
0xFFF7_EFFF
RESERVED
0xFFF7_ED00
0xFFF7_EEFF
GIO
0xFFF7_EC00
0xFFF7_ECFF
RESERVED
0xFFF7_EA00
0xFFF7_EBFF
HECC
0xFFF7_E800
0xFFF7_E9FF
RESERVED
0xFFF7_E600
0xFFF7_E7FF
HECC RAM
0xFFF7_E400
0xFFF7_E5FF
RESERVED
0xFFF7_E100
0xFFF7_E3FF
SCC
0xFFF7_E000
0xFFF7_E0FF
RESERVED
0xFFF7_DD00
0xFFF7_DDFF
SCC RAM
0xFFF7_DC00
0xFFF7_DCFF
RESERVED
0xFFF7_D800
0xFFF7_DBFF
RESERVED
0xFFF7_D600
0xFFF7_D7FF
SPI3 (MibSPI)
0xFFF7_D500
0xFFF7_D5FF
SPI2
0xFFF7_D400
0xFFF7_D4FF
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PS[0]
PS[1]
PS[2]
PS[3]
PS[4]
PS[5]
PS[6]
PS[7]
PS[8]
PS[9]
PS[10]
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
peripheral selects and base addresses (continued)
Table 4. VF478 Peripherals, System Module, and Flash Base Addresses (Continued)
CONNECTING MODULE
ADDRESS RANGE
BASE ADDRESS
ENDING ADDRESS
PERIPHERAL SELECTS
RESERVED
0xFFF7_CC00
0xFFF7_D3FF
RESERVED
0xFFF7_C900
0xFFF7_CBFF
RESERVED
0xFFF7_C800
0xFFF7_C8FF
RESERVED
0xFFF7_C000
0xFFF7_C7FF
PS[14] - PS[15]
RESERVED
0xFFF0_0000
0xFFF7_BFFF
N/A
Flash Control Registers
0xFFE8_8000
0xFFE8_BFFF
N/A
MPU Control Registers
0xFFE8_4000
0xFFE8_4023
N/A
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PS[11] - PS[12]
PS[13]
17
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
direct-memory access (DMA)
The direct-memory access (DMA) controller transfers data to and from any specified location in the VF478
memory map (except for restricted memory locations like the system control registers area). The DMA manages
up to 16 channels, and supports data transfer for both on-chip and off-chip memories and peripherals. The
DMA controller is connected to both the CPU and Peripheral busses, enabling these data transfers to occur in
parallel with CPU activity and thus, maximizing overall system performance.
Although the DMA controller has two possible configurations, for the VF478 device, the DMA controller configuration is 32 control packets and 16 channels.
For the VF478 DMA request hardwired configuration, see Table 5.
Table 5. DMA Request Lines Connections
MODULES
MibADC2†
DMA REQUEST INTERRUPT SOURCES
DMA CHANNEL
MibADC2 event
DMAREQ[0]
MibADC2†/SPI1
MibADC2 G1/SPI1 end-receive
DMAREQ[1]
MibADC2†/SPI1
MibADC2 G2/SPI1 end-transmit
DMAREQ[2]
MibADC1 event
DMAREQ[3]
MibADC G1/SCI1 end-receive
DMAREQ[4]
MibADC1
†
MibADC1†/SCI1
†/SCI1
MibADC G2/SCI1 end-transmit
DMAREQ[5]
MibADC2 G1
DMAREQ[6]
MibSPI/SPI2
MIBSPI_DMA_REQ(3)/SPI2 end-receive
DMAREQ[7]
MibSPI/SPI2
MIBSPI_DMA_REQ(2)/SPI2 end-transmit
MibADC1
MibADC2
†
DMAREQ[8]
RESERVED
DMAREQ[9]
RESERVED
DMAREQ[10]
†
MibADC2 G2
DMAREQ[11]
MibADC1†
MibADC1 G1
DMAREQ[12]
MibADC2
MibADC1†
MibADC1 G2
DMAREQ[13]
MibSPI
MIBSPI_DMA_REQ(1)
DMAREQ[14]
MibSPI
MIBSPI_DMA_REQ(0)
DMAREQ[15]
† The MibADC is capable of being serviced by the DMA when the device is in buffered mode. For more information on buffered mode, see the
MibADC section of this data sheet and the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number
SPNU206).
Each channel has two control packets attached to it, allowing the DMA to continuously load RAM and generate
periodic interrupts so that the data can be read by the CPU. The control packets allow for the interrupt enable,
and the channels determine the priority level of the interrupt.
DMA transfers occur in one of two modes:
O
Non-request mode (used when transferring from memory to memory)
O
Request mode (used when transferring from memory to peripheral)
For more detailed functional information on the DMA controller, see the TMS470R1x Direct Memory Access
(DMA) Controller Reference Guide (literature number SPNU194).
18
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
interrupt priority
The central interrupt manager (CIM) portion of the SYS module manages the interrupt requests from the device
modules (i.e., SPI1 or SPI2, SCI, and RTI, etc.).
Although the CIM can accept up to 32 interrupt request signals, the VF478 device only uses 21 of those interrupt
request signals. The request channels are maskable so that individual channels can be selectively disabled.
All interrupt requests can be programmed in the CIM to be of either type:
O
Fast interrupt request (FIQ)
O
Normal interrupt request (IRQ)
The precedences of request channels decrease with ascending channel order in the CIM (0 [highest] and
31 [lowest] priority). For these channel priorities and the associated modules, see Table 6.
Table 6. Interrupt Priority
MODULES
INTERRUPT SOURCES
INTERRUPT LEVEL/CHANNEL
SPI1
SPI1 end-transfer/overrun
0
RTI
COMP2 interrupt
1
RTI
COMP1 interrupt
2
RTI
TAP interrupt
3
SPI2
SPI2 end-transfer/overrun
4
GIO
Interrupt A
5
Reserved
6
HET
Interrupt 1
SPI3 - MibSPI
Interrupt 1
7
8
SCI
SCI exception interrupt
9
SCI
SCI receive interrupt
10
End event conversion
12
HECC
Interrupt A
13
SCC
Interrupt A
14
SPI3 - MibSPI
Interrupt 2
15
End event conversion
16
End Group 1 conversion
17
Reserved
MibADC2
MibADC1
MibADC2
DMA
MibADC2
SCI
System
11
Interrupt 0
18
End Group 2 conversion
19
SCI transmit interrupt
20
SW interrupt (SSI)
21
Reserved
22
HET
Interrupt 2
23
HECC
Interrupt B
24
SCC
Interrupt B
25
End Group 1 conversion
27
DMA
Interrupt 2
28
GIO
Interrupt B
29
End Group 2 conversion
30
Reserved
MibADC1
MibADC1
26
Reserved
31
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19
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
MibADC
The multi-buffered analog-to-digital converter (MibADC) accepts an analog signal and converts the signal to a
10-bit digital value.
The VF478 MibADC module can function in two modes: compatibility mode, where its programmer’s model is
compatible with the TMS470R1x ADC module and its digital results are stored in digital result registers; or in
buffered mode, where the digital result registers are replaced with three FIFO buffers, one for each conversion
group [event, group1 (G1), and group2 (G2)]. In buffered mode, the MibADC buffers can be serviced by interrupts
or by the DMA.
MibADC event trigger enhancements
The MibADC includes two major enhancements over the event-triggering capability of the TMS470R1x ADC.
O
Both group1 and the event group can be configured for event-triggered operation, providing up to two eventtriggered groups.
O
The trigger source and polarity can be selected individually for both group 1 and the event group from the
three options identified in Table 7.
Table 7. MibADC Event Hookup Configuration
EVENT #
SOURCE SELECT BITS FOR G1 OR EVENT
(G1SRC[1:0] or EVSRC[1:0])
SIGNAL PIN NAME
MibADC1EVENT0
00
ADEVT1
MibADC1EVENT1
01
HET[18]
MibADC1EVENT2
10
HET[19]
MibADC1EVENT3
11
reserved
MibADC2EVENT0
00
ADEVT2
MibADC2EVENT1
01
HET[18]
MibADC2EVENT2
10
HET[19]
MibADC2EVENT3
11
reserved
For group 1, these event-triggered selections are configured via the group 1 source select bits (G1SRC[1:0])
in the AD event source register (ADEVTSRC.[5:4]). For the event group, these event-triggered selections are
configured via the event group source select bits (EVSRC[1:0]) in the AD event source register
(ADEVTSRC.[1:0]).
For more detailed functional information on the MibADC, see the TMS470R1x Multi-Buffered Analog-to-Digital
Converter (MibADC) Reference Guide (literature number SPNU206).
20
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
MibSPI
The MibSPI is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed
length (one to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The MibSPI
is normally used for communication between the microcontroller and external peripherals or another microcontroller. Typical applications include interface to external I/O or peripheral expansion via devices such as shift
registers, display drivers, and analog-to-digital converters.
Table 7 shows the trigger sources for MibSPI.
Table 8. MibSPI Event Hookup Configuration
EVENT #
SIGNAL PIN NAME
EVENT0
Reserved
EVENT1
GIOA[0]
EVENT2
GIOA[2]
EVENT3
GIOA[3]
EVENT4
Reserved
EVENT5
HET[20]
EVENT6
HET[21]
EVENT7
HET[22]
EVENT8
HET[23]
EVENT9
HET[25]
EVENT10
HET[26]
EVENT11
HET[27]
EVENT12
ADEVT1
EVENT13
ADEVT2
EVENT14
Internal Tick Counter
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21
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
development system support
Texas Instruments provides extensive hardware and software development support tools for the TMS470R1x
family. These support tools include:
O
Code Composer Studio™ Integrated Development Environment (IDE)
–
–
–
O
Optimizing C compiler
–
–
–
–
–
–
–
O
Provides extensive macro capability
Allows high-speed operation
Allows extensive control of the assembly process using assembler directives
Automatically resolves memory references as C and assembly modules are combined
TMS470R1x CPU Simulator
–
–
–
O
Supports high-level language programming
Full implementation of the standard ANSI C language
Powerful optimizer that improves code-execution speed and reduces code size
Extensive run-time support library included
TMS470R1x control registers easily accessible from the C program
Interfaces C functions and assembly functions easily
Establishes comprehensive, easy-to-use tool set for the development of high-performance
microcontroller applications in C/C++
Assembly language tools (assembler and linker)
–
–
–
–
O
Fully integrated suite of software development tools
Includes Compiler/Assembler/Linker, Debugger, and Simulator
Supports Real-Time analysis, data visualization, and open API
Provides capability to simulate CPU operation without emulation hardware
Allows inspection and modifications of memory locations
Allows debugging programs in C or assembly language
XDS emulation communication kits
–
Allow high-speed JTAG communication to the TMS470R1x emulator or target board
For information on pricing and availability, contact the nearest TI field office or authorized distributor.
Code Composer Studio is a trademark of Texas Instruments.
22
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
documentation support
Extensive documentation supports all of the TMS470 microcontroller family generation of devices. The types
of documentation available include: data sheets with design specifications; complete user’s guides for all
devices and development support tools; and hardware and software applications. Useful reference documentation includes:
O
O
User’s Guides
–
TMS470R1x 32-Bit RISC Microcontroller Family User’s Guide (literature number SPNU134)
–
TMS470R1x C/C++ Compiler User’s Guide (literature number SPNU151)
–
TMS470R1x Code Generation Tools Getting Started Guide (literature number SPNU117)
–
TMS470R1x C Source Debugger User’s Guide (literature number SPNU124)
–
TMS470R1x Assembly Language Tools User’s Guide (literature number SPNU118)
–
TMS470R1x System Module Reference Guide (literature number SPNU189)
–
TMS470R1x Direct Memory Access (DMA) Controller Reference Guide (literature number SPNU194)
–
TMS470R1x Serial Peripheral Interface (SPI) Reference Guide (literature number SPNU195)
–
TMS470R1x Serial Communication Interface (SCI) Reference Guide (literature number SPNU196)
–
TMS470R1x Controller Area Network (CAN) Reference Guide (literature number SPNU197)
–
TMS470R1x High-End Timer (HET) Reference Guide (literature number SPNU199)
–
TMS470R1x External Clock Prescale (ECP) Reference Guide (literature number SPNU202)
–
TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number
SPNU206)
–
TMS470R1x F05 Flash Reference Guide (literature number SPNU213)
–
TMS470R1x Frequency-Modulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide
(literature number SPNU221)
–
TMS470R1x Multi-Buffered Serial Peripheral Interface (MibSPI) Reference Guide (literature number
SPNU217)
Application Reports:
–
Analog Watchdog Resistor, Capacitor and Discharge Interval Selection Constraints (literature number
SPNA005)
–
F05/C05 Power Up Reset and Power Sequencing Requirements (literature number SPNA009)
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
device numbering conventions
Figure 2 illustrates the numbering and symbol nomenclature for the TMS470R1x family.
TMS 470 R1 V F 47 8 GJZ Q
Prefix: TMS = Standard Prefix for Fully Qualified Devices
Family:
470 = TMS470 RISC-Embedded Microcontroller Family
V = 1.8-V Core Voltage
Program Memory Types:
CPU Type:
Device Type:
Program Memory Size
C
F
L
B
R
=
=
=
=
=
Masked ROM
Flash
ROM-less
System Emulator for Development Tools
RAM
R1 = ARM7TDMI CPU
47 = 47 Devices Containing the Following Modules:
– FMPLL Clock
– 16K-Byte Static RAM
– 1.5K-Byte HET RAM (128 Instructions)
– Digital Watchdog (DWD)
– Real-Time Interrupt (RTI)
– Two 10-Bit, 16-Input Multi-buffered Analog-to-Digital
Converter (MibADC)
– Two Serial Peripheral Interface (SPI) Modules
– Multi-buffered Serial Peripheral Interface (MibSPI) Module
– Serial Communications Interface (SCI) Module
– Standard Controller Area Network (CAN) [SCC]
– High-End Controller Area Network (CAN) [HECC]
– High-End Timer (HET)
– External Clock Prescaler (ECP)
8 = 0
– No on-chip program memory
1–5 – 1 to < 128K Bytes
6–B – 128K Bytes to < 1M Bytes
C–F – > 1M Bytes
Operating Free-Air
Temperature Ranges:
Package:
A =
T =
Q =
–40°C to 85°C
–40°C to 105°C
–40°C to 125°C
GJZ = 176-Pin Plastic Ball Grid Array
Figure 2. TMS470R1x Family Nomenclature
24
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
device identification code register
The device identification code register identifies the silicon version, the technology family (TF), a ROM or flash
device, and an assigned device-specific part number (see Table 9). The VF478 device identification code
register value is 0x094F.
Table 9. TMS470 Device ID Bit Allocation Register
BIT 31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
BIT 16
6
5
4
3
2
1
BIT 0
RESERVED
FFFF_FFF0
BIT 15
LEGEND:
For bits 3–15:
For bits 0–2:
14
13
12
11
10
9
8
7
VERSION
TF
R/F
PART NUMBER
1
1
1
R-K
R-K
R-K
R-K
R-1
R-1
R-1
R = Read only, -K = Value constant after RESET
R = Read only, -1 = Value after RESET
Bits 31:16
Reserved. Reads are undefined and writes have no effect.
Bits 15:12
VERSION. Silicon version (revision) bits
These bits identify the silicon version of the device.
Bit 11
TF. Technology Family (TF) bit
This bit distinguishes the technology family core power supply:
0 = 3.3 V for F10/C10 devices
1 = 1.8 V for F05/C05 devices
Bit 10
R/F. ROM/flash bit
This bit distinguishes between ROM and flash devices:
0 = Flash device
1 = ROM device
Bits 9:3
PART NUMBER. Device-specific part number bits
These bits identify the assigned device-specific part number.
The assigned device-specific part number for the VF478 device is: 0101001.
Bits 2:0
"1" Mandatory High. Bits 2,1, and 0 are tied high by default.
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
device part numbers
Table 10 lists all the available TMS470R1VF478 devices.
Table 10. Device Part Number
DEVICE PART
NUMBER
PROGRAM MEMORY
PACKAGE TYPE
TEMPERATURE RANGES
FLASH
EEPROM
176-PIN
PBGA
−40°C TO 85°C
TMS470R1VF478GJZA
X
X
X
TMS470R1VF478GJZT
X
X
TMS470R1VF478GJZQ
X
X
26
ROM
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−40°C TO 105°C
−40°C TO 125°C
X
X
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
DEVICE ELECTRICAL SPECIFICATIONS AND TIMING PARAMETERS
absolute maximum ratings over operating free-air temperature range, Q version
(unless otherwise noted)†
Supply voltage ranges: VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.5 V
Supply voltage ranges: VCCIO , VCCAD , VCCP (flash pump) (see Note 1) . . . . . . . . . . . . . . . . . . −0.5 V to 4.1 V
Input voltage range: All input pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.1 V
Input clamp current: IIK (VI < 0 or VI > VCCIO)
All pins except ADIN[0:11], PORRST, TRST, TEST and TCK . . . . . . . . . . . . . . . ±20 mA
IIK (VI < 0 or VI > VCCAD)
ADIN[0:11] . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Operating free-air temperature ranges, TA: A version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 85°C
T version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 105°C
Q version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 125°C
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .−40°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to their associated grounds.
device recommended operating conditions‡
MIN
NOM
MAX
UNIT
1.81
1.95
2.05
V
VCC
Digital logic and flash supply voltage (Core)
VCCIO
Digital logic supply voltage (I/O)
3
3.3
3.6
V
VCCAD
ADC supply voltage
3
3.3
3.6
V
VCCP
Flash pump supply voltage
3
3.3
3.6
V
VSS
Digital logic supply ground
VSSAD
ADC supply ground
TA
TJ
Operating free-air temperature
0
V
− 0.1
0.1
V
A version
− 40
85
°C
T version
− 40
105
°C
Q version
− 40
125
°C
− 40
150
°C
Operating junction temperature
‡ All voltages are with respect to VSS, except VCCAD, which is with respect to VSSAD.
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted)†
PARAMETER
Vhys
TEST CONDITIONS
‡
VIL
VIH
Low-level input voltage
High-level input voltage
0.8
OSCIN only
− 0.3
0.35 VCC
All inputs except
OSCIN
2
0.65 VCC
Input threshold voltage
AWD only
RDSON
Drain to source on resistance
AWD only§
VOL
Low-level output voltage¶
VOH
High-level output voltage¶
IIC
Input clamp current (I/O pins)#
1.35
VOL = 0.35V @ IOL = 4mA
IOL = IOL MAX
IOH = IOH MIN
IOH = 50 μA
IIL Pulldown
IOL
IOH
Low-level output
current
High-level output
current
VCCIO + 0.3
V
90
Ω
0.2
0.8 VCCIO
−2
2
−1
1
VI = VCCIO
VI = VSS
V
V
VCCIO − 0.2
VI < VSSIO − 0.3 or VI > VCCIO + 0.3
IIH Pulldown
V
1.8
VI = VSS
IIL Pullup
V
VCC + 0.3
0.2 VCCIO
IOL = 50 μA
UNIT
V
− 0.3
Vth
Input current (I/O pins)
MAX
All inputs except
OSCIN
OSCIN only
II
MIN
0.15
Input hysteresis
5
40
–40
–5
IIH Pullup
VI = VCCIO
−1
1
All other pins
No pullup or pulldown
−1
1
TDI, TDO, TMS,
TMS2 and CLKOUT
VOL = VOL MAX
8
AWD and RST
VOL = VOL MAX
4
All other output pins|| VOL = VOL MAX
2
mA
μA
mA
mA
TDI, TDO, TMS,
TMS2 and CLKOUT
VOH = VOH MIN
−8
RST
VOH = VOH MIN
−4
mA
VOH = VOH MIN
−2
mA
All other output pins
||
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 35.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
# Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
, For flash pumps/banks in sleep mode.
R I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
28
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
electrical characteristics over recommended operating free-air temperature range, Q version
(unless otherwise noted)†
PARAMETER
TEST CONDITIONS
VCC Digital supply current (operating mode)
ICC
VCC Digital supply current (standby mode)
VCC Digital supply current (halt mode)
,
,
VCCIO Digital supply current (operating mode)
ICCIO
ICCADn
(n = 1 or 2)
ICCP
CI
CO
VCCIO Digital supply current (standby mode)
MIN TYP
MAX UNIT
SYSCLK = 60 MHz, VCC = 2.05 V
118
mA
OSCIN = 7.5 MHz, VCC = 2.05 V
1.5
mA
VCC = 2.05 V
1
mA
R
10
mA
VR
100
μA
R
No DC load, VCCIO = 3.6 V
No DC load, VCCIO = 3.6
VCCIO Digital supply current (halt mode)
No DC load, VCCIO = 3.6 V
100
μA
VCCADn supply current (operating mode)
All frequencies, VCCADn = 3.6 V
15
mA
VCCADn supply current (standby mode)
No DC load, VCCADn = 3.6 V
20
μA
VCCADn supply current (halt mode)
VCCADn = 3.6 V
20
μA
VCCP pump supply current
VCCP = 3.6 V read operation
50
mA
VCCP = 3.6 V program and erase
70
mA
VCCP = 3.6 V standby mode,
20
μA
VCCP = 3.6 V halt mode operation,
20
μA
Input capacitance
2
pF
Output capacitance
3
pF
† Source currents (out of the device) are negative while sink currents (into the device) are positive.
‡ This does not apply to the PORRST pin. For PORRST exceptions, see the RST and PORRST timings section on page 35.
§ These values help to determine the external RC network circuit. For more details, see the TMS470R1x System Module Reference Guide
(literature number SPNU189).
¶ VOL and VOH are linear with respect to the amount of load current (IOL/IOH) applied.
# Parameter does not apply to input-only or output-only pins.
||
The 2 mA buffers on this device are called zero-dominant buffers. If two of these buffers are shorted together and one is outputting a low level
and the other is outputting a high level, the resulting value will always be low.
, For flash pumps/banks in sleep mode.
R I/O pins configured as inputs or outputs with no load. All pulldown inputs ≤ 0.2 V. All pullup inputs ≥ VCCIO − 0.2 V.
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION
IOL
Tester Pin
Electronics
50 Ω
VLOAD
Output
Under
Test
CL
IOH
Where: IOL
= IOL MAX for the respective pin (see Note A)
= IOH MIN for the respective pin (see Note A)
IOH
VLOAD = 1.5 V
= 150-pF typical load-circuit capacitance (see Note B)
CL
NOTES: A. For these values, see the "electrical characteristics over recommended operating free-air temperature range" table.
B. All timing parameters measured using an external load capacitance of 150 pF unless otherwise noted.
Figure 3. Test Load Circuit
30
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
timing parameter symbology
Timing parameter symbols have been created in accordance with JEDEC Standard 100. In order to shorten
the symbols, some of the pin names and other related terminology have been abbreviated as follows:
CM
CO
ER
ICLK
M
OSC, OSCI
OSCO
P
R
R0
R1
Compaction, CMPCT
CLKOUT
Erase
Interface clock
Master mode
OSCIN
OSCOUT
Program, PROG
Ready
Read margin 0, RDMRGN0
Read margin 1, RDMRGN1
RD
RST
RX
S
SCC
SIMO
SOMI
SPC
SYS
TX
Read
Reset, RST
SCInRX
Slave mode
SCInCLK
SPInSIMO
SPInSOMI
SPInCLK
System clock
SCInTX
r
su
t
v
w
rise time
setup time
transition time
valid time
pulse duration (width)
Lowercase subscripts and their meanings are:
a
c
d
f
h
access time
cycle time (period)
delay time
fall time
hold time
The following additional letters are used with these meanings:
H
High
X
L
V
Low
Valid
Z
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31
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
external reference resonator/crystal oscillator clock option
The oscillator is enabled by connecting the appropriate fundamental 4–10 MHz resonator/crystal and load
capacitors across the external OSCIN and OSCOUT pins as shown in Figure 4a. The oscillator is a singlestage inverter held in bias by an integrated bias resistor. This resistor is disabled during leakage test measurement and HALT mode. TI strongly encourages each customer to submit samples of the device to the
resonator/crystal vendors for validation. The vendors are equipped to determine what load capacitors will
best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes.
An external oscillator source can be used by connecting a 1.8V clock signal to the OSCIN pin and leaving the
OSCOUT pin unconnected (open) as shown in Figure 4b.
OSCIN
C1
(see Note A)
OSCOUT
Crystal
OSCIN
C2
(see Note A)
External
Clock Signal
(toggling 0–1.8 V)
(a)
(b)
NOTE A: The values of C1 and C2 should be provided by the resonator/crystal vendor.
Figure 4. Crystal/Clock Connection
32
OSCOUT
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
FMPLL and clock specifications
timing requirements for FMPLL circuits enabled or disabled
MIN
f(OSC)
Input clock frequency
tc(OSC)
Cycle time, OSCIN
tw(OSCIL)
tw(OSCIH)
f(OSCRST)
TYP
4
MAX
UNIT
10
MHz
100
ns
Pulse duration, OSCIN low
15
ns
Pulse duration, OSCIN high
15
ns
OSC FAIL
frequency†
53
kHz
† Causes a device reset (specifically a clock reset) by setting the RST OSC FAIL (GLBCTRL.15) and the OSC FAIL flag (GLBSTAT.1) bits equal
to 1. For more detailed information on these bits and device resets, see the TMS470R1x System Module Reference Guide (literature number
SPNU189).
switching characteristics over recommended operating conditions for clocks‡§
PARAMETER
f(SYS)
System clock frequency#
f(CONFIG)
System clock frequency
f(ICLK)
f(ECLK)
Interface clock frequency
External clock output frequency for ECP Module
tc(SYS)
Cycle time, system clock
tc(CONFIG)
Cycle time, system clock
tc(ICLK)
tc(ECLK)
Cycle time, interface clock
Cycle time, ECP module external clock output
TEST CONDITIONS¶
MAX
UNIT
pipeline mode disabled
MIN
24
MHz
pipeline mode enabled
60
MHz
flash config mode
24
MHz
pipeline mode enabled
25
MHz
pipeline mode disabled
24
MHz
pipeline mode enabled
25
MHz
24
MHz
pipeline mode disabled
pipeline mode disabled
41.6
ns
pipeline mode enabled
16.7
ns
flash config mode
41.6
ns
pipeline mode enabled
40
ns
pipeline mode disabled
41.6
ns
pipeline mode enabled
40
ns
pipeline mode disabled
41.6
ns
‡ f(SYS) = M × f(OSC) / R, where M = {1,2,4, or 8} when PLLDIS = 0, and M = 1 when PLLDIS = 1; and where R = {1,2,4, or 8}. Please see the
TMS470R1x Frequency-Modulated Phase-Locked Loop (FMPLL) Clock Module Reference Guide (literature number SPNU221) for details on
M and R values.
f(SYS) = f(OSC) / R, where R = {1,2,3,4,5,6,7,8} when PLLDIS = 1.
f(ICLK) = f(SYS) / X, where X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits
in the SYS module.
§ f(ECLK) = f(ICLK) / N, where N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
¶ Pipeline mode enabled or disabled is determined by the ENPIPE bit (FMREGOPT.0).
# Flash Vread must be set to 5V to achieve maximum System Clock Frequency.
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SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
FMPLL and clock specifications (continued)
switching characteristics over recommended operating conditions for external clocks
(see Figure 5 and Figure 6)†‡§
NO.
PARAMETER
TEST CONDITIONS
SYSCLK or MCLK
1
tw(COL)
MIN
¶
ICLK, X is even or 1#
Pulse duration, CLKOUT low
0.5tc(ICLK) – tf
ICLK, X is odd and not
1#
tw(COH)
Pulse duration, CLKOUT high ICLK, X is even or
0.5tc(ICLK) – tr
ICLK, X is odd and not 1
3
4
tw(EOH)
Pulse duration, ECLK low
Pulse duration, ECLK high
ns
0.5tc(SYS) – tr
1#
#
tw(EOL)
UNIT
0.5tc(ICLK) + 0.5tc(SYS) – tf
SYSCLK or MCLK¶
2
MAX
0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tf
N is odd and X is even
0.5tc(ECLK) – tf
N is odd and X is odd and not 1
0.5tc(ECLK) + 0.5tc(SYS) – tf
N is even and X is even or odd
0.5tc(ECLK) – tr
0.5tc(ECLK) – tr
N is odd and X is even
N is odd and X is odd and not 1
ns
0.5tc(ICLK) – 0.5tc(SYS) – tr
ns
ns
0.5tc(ECLK) – 0.5tc(SYS) – tr
† X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0.[4:1] bits in the SYS module.
‡ N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL.[7:0] register bits in the ECP module.
§ CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
¶ Clock source bits selected as either SYSCLK (CLKCNTL.[6:5] = 11 binary) or MCLK (CLKCNTL.[6:5] = 10 binary).
# Clock source bits selected as ICLK (CLKCNTL.[6:5] = 01 binary).
2
CLKOUT
1
Figure 5. CLKOUT Timing Diagram
4
ECLK
3
Figure 6. ECLK Timing Diagram
34
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
FMPLL and clock specifications (continued)
Table 11 is based on a specific OSCIN, SYSCLK, and modulation depth, varying the number of glitches per
four periods in order to obtain the modulation frequency. The numerical integration yields an average frequency
that is compared to the base frequency in order to find the maximum, worst-case percentage offset over a given
length of time in μs.
Table 11. Average FMPLL Frequency (OSCIN = 7.5MHz, SYSCLK = 60MHz, CAN = 500kHz)
MODULATION
FREQUENCY
ACTUAL MODULATION
EXPECTED
DEPTH FROM
MODULATION
CHARACTERIZATION
DEPTH
4μs
6μs
8μs
10μs
12μs
14μs
134 kHz
2%
6.89%
1.23%
0.60%
0.26%
0.51%
0.44%
0.22%
117 kHz
2%
6.99%
1.42%
0.81%
0.22%
0.39%
0.49%
0.40%
104 kHz
2%
7.01%
1.65%
1.13%
0.50%
0.23%
0.48%
0.53%
94 kHz
2%
7.05%
1.83%
1.28%
0.76%
0.23%
0.35%
0.53%
134 kHz
1%
5.62%
0.78%
0.42%
0.20%
0.35%
0.30%
0.16%
117 kHz
1%
5.66%
0.91%
0.53%
0.17%
0.28%
0.33%
0.27%
104 kHz
1%
5.63%
1.09%
0.77%
0.35%
0.20%
0.34%
0.37%
94 kHz
1%
5,63%
1.23%
0.87%
0.52%
0.18%
0.26%
0.38%
134 kHz
0.5%
4,42%
0.64%
0.39%
0.21%
0.33%
0.27%
0.17%
104 kHz
0.5%
4,41%
0.81%
0.60%
0.27%
0.18%
0.27%
0.29%
94 kHz
0.5%
4.41%
0.93%
0.67%
0.40%
0.16%
0.22%
0.30%
16μs
18μs
20μs
22μs
24μs
26μs
MODULATION
FREQUENCY
ACTUAL MODULATION
EXPECTED
DEPTH FROM
MODULATION
CHARACTERIZATION
DEPTH
134 kHz
2%
6.89%
0.22%
0.31%
0.26%
0.09%
0.20%
0.23%
117 kHz
2%
6.99%
0.20%
0.18%
0.30%
0.29%
0.18%
0.10%
104 kHz
2%
7.01%
0.42%
0.22%
0.16%
0.30%
0.33%
0.25%
94 kHz
2%
7.05%
0.53%
0.41%
0.22%
0.14%
0.28%
0.33%
134 kHz
1%
5.62%
0.16%
0.21%
0.19%
0.08%
0.15%
0.16%
117 kHz
1%
5.66%
0.15%
0.15%
0.21%
0.20%
0.14%
0.09%
104 kHz
1%
5.63%
0.30%
0.16%
0.13%
0.21%
0.24%
0.18%
94 kHz
1%
5,63%
0.37%
0.29%
0.17%
0.12%
0.21%
0.23%
134 kHz
0.5%
4,42%
0.17%
0.20%
0.18%
0.09%
0.16%
0.15%
104 kHz
0.5%
4,41%
0.24%
0.14%
0.12%
0.17%
0.19%
0.14%
94 kHz
0.5%
4.41%
0.29%
0.23%
0.14%
0.11%
0.17%
0.19%
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
RST and PORRST timings
timing requirements for PORRST (see Figure 7)
MIN
NO.
MAX
UNIT
VCCPORL
VCC low supply level when PORRST must be active during power up
VCCPORH
VCC high supply level when PORRST must remain active during power up and
become active during power down
VCCIOPORL
VCCIO low supply level when PORRST must be active during power up
VCCIOPORH
VCCIO high supply level when PORRST must remain active during power up and
become active during power down
VIL
Low-level input voltage after VCCIO > VCCIOPORH
VIL(PORRST)
Low-level input voltage of PORRST before VCCIO > VCCIOPORL
3
tsu(PORRST)r
Setup time, PORRST active before VCCIO > VCCIOPORL during power up
0
ms
5
tsu(VCCIO)r
Setup time, VCCIO > VCCIOPORL before VCC > VCCPORL
0
ms
6
th(PORRST)r
Hold time, PORRST active after VCC > VCCPORH
1
ms
0.6
V
1.5
V
1.1
V
2.75
V
0.2 VCCIO
V
0.5
V
7
tsu(PORRST)f
Setup time, PORRST active before VCC ≤ VCCPORH during power down
8
μs
8
th(PORRST)rio
Hold time, PORRST active after VCCIO > VCCIOPORH
1
ms
9
th(PORRST)d
Hold time, PORRST active after VCC < VCCPORL
0
ms
10
tsu(PORRST)fio
Setup time, PORRST active before VCCIO ≤ VCCIOPORH during power down
0
ns
11
tsu(VCCIO)f
Setup time, VCC < VCCPORL before VCCIO < VCCIOPORL
0
ns
VCCP/VCCIO
VCCIOPORH
VCCIOPORH
VCCIO
8
VCC
VCC
VCCPORH
6
VCCIOPORL
VCC
11
VCCPORH
7
6
10
7
VCCPORL
VCCPORL
VCCIOPORL
5
VCCP/VCCIO
3
PORRST
VIL(PORRST)
9
VIL
VIL
VIL
VIL
VIL(PORRST)
Figure 7. PORRST Timing Diagram
switching characteristics over recommended operating conditions for RST†
MIN
PARAMETER
tv(RST)
tfsu
4112tc(OSC)
Valid time, RST active after PORRST inactive
8tc(SYS)
Valid time, RST active (all others)
Flash start up time, from RST inactive to fetch of first instruction from flash
(flash pump stabilization time)
836tc(OSC)
MAX
UNIT
ns
ns
† Specified values do NOT include rise/fall times. For rise and fall timings, see the ’switching characteristics for output timings versus load
capacitance’ table.
36
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JTAG scan interface timing (JTAG clock specification 10-MHz and 50-pF load on TDO output)
MIN
NO.
MAX
UNIT
1
tc(JTAG)
Cycle time, JTAG low and high period
50
ns
2
tsu(TDI/TMS - TCKr)
Setup time, TDI, TMS before TCK rise (TCKr)
15
ns
3
th(TCKr -TDI/TMS)
Hold time, TDI, TMS after TCKr
15
ns
4
th(TCKf -TDO)
Hold time, TDO after TCKf
10
ns
5
td(TCKf -TDO)
Delay time, TDO valid after TCK fall (TCKf)
45
ns
TCK
1
1
TMS
TDI
2
3
TDO
4
5
Figure 8. JTAG Scan Timing
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
output timings
switching characteristics for output timings versus load capacitance (CL) (see Figure 9)
MIN
PARAMETER
tf
tf
tf
tf
tr
tf
Rise time, CLKOUT, TDI, TDO, TMS, TMS2
Fall time, CLKOUT, TDI, TDO, TMS, TMS2
Rise time, AWD
Fall time, AWD, RST
Rise time, all other output pins
Fall time, all other output pins
0.5
2.5
CL= 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
0.5
2.5
CL= 50 pF
1.5
5
CL = 100 pF
3
9
CL = 150 pF
4.5
12.5
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
8
CL= 50 pF
5
14
CL = 100 pF
9
23
CL = 150 pF
13
32
CL = 15 pF
2.5
10
CL = 50 pF
6.0
25
CL = 100 pF
12
45
CL = 150 pF
18
65
CL = 15 pF
3
10
CL = 50 pF
8.5
25
CL = 100 pF
16
45
CL = 150 pF
23
65
tr
tf
80%
Output
20%
VCC
80%
20%
Figure 9. CMOS-Level Outputs
38
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0
ns
ns
ns
ns
ns
ns
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
input timings
timing requirements for input timings† (see Figure 10)
MIN
tpw
tc(ICLK) + 10
Input minimum pulse width
MAX
UNIT
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
tpw
Input
80%
20%
VCC
80%
20%
0
Figure 10. CMOS-Level Inputs
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16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
flash timings
timing requirements for program flash†
MIN
tprog(16-bit)
288K-byte programming
time‡
terase(sector)
Sector erase time
twec
Write/erase cycles at TA = 125°C
tfp(RST)
MAX
UNIT
16
200
μs
2.3
9
s
4
Half word (16-bit) programming time
tprog(Total)
TYP
2
15
s
500
cycles
Flash pump settling time from RST to SLEEP
167tc(SYS)
ns
tfp(SLEEP)
Initial flash pump settling time from SLEEP to STANDBY
167tc(SYS)
ns
tfp(STDBY)
Initial flash pump settling time from STANDBY to ACTIVE
84tc(SYS)
ns
† For more detailed information on the flash core sectors, see the flash program and erase section of this data sheet.
‡ The 288K-byte programming times include overhead of state machine.
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SPIn master mode timing parameters
SPIn master mode external timing parameters (CLOCK PHASE = 0, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 11)
NO.
1
2#
3#
4
MAX
100
256tc(ICLK)
Cycle time, SPInCLK
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPInCLK high to SPInSIMO valid
(clock polarity = 0)
0
10
td(SPCL-SIMO)M
Delay time, SPInCLK low to SPInSIMO valid
(clock polarity = 1)
0
10
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 0)
tc(SPC)M – 5 – tf
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 1)
tc(SPC)M – 5 – tr
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low
(clock polarity = 0)
12
tsu(SOMI-SPCH)M
Setup time, SPInSOMI before SPInCLK high
(clock polarity = 1)
12
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 0)
10
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 1)
10
6#
7#
MIN
tc(SPC)M
#
5#
¶
UNIT
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
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SPIn master mode timing parameters (continued)
SPIn master mode external timing parameters (CLOCK PHASE = 1, SPInCLK = output, SPInSIMO =
output, and SPInSOMI = input)†‡§ (see Figure 12)
NO.
1
2#
3#
4#
5#
6#
7#
tc(SPC)M
Cycle time, SPInCLK
tw(SPCH)M
¶
MIN
MAX
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPInCLK high after SPInSIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 10
tv(SIMO-SPCL)M
Valid time, SPInCLK low after SPInSIMO data valid (clock polarity = 1)
0.5tc(SPC)M – 10
tv(SPCH-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK high (clock polarity = 0)
0.5tc(SPC)M – 5 – tr
tv(SPCL-SIMO)M
Valid time, SPInSIMO data valid after SPInCLK low (clock polarity = 1)
0.5tc(SPC)M – 5 – tf
tsu(SOMI-SPCH)M Setup time, SPInSOMI before SPInCLK high (clock polarity = 0)
12
tsu(SOMI-SPCL)M
Setup time, SPInSOMI before SPInCLK low (clock polarity = 1)
12
tv(SPCH-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK high (clock polarity = 0)
10
tv(SPCL-SOMI)M
Valid time, SPInSOMI data valid after SPInCLK low (clock polarity = 1)
10
UNIT
ns
† The MASTER bit (SPInCTRL2.3) is set and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)M ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)M = 2tc(ICLK) ≥ 100 ns.
# The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn master mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
Master Out Data Is Valid
Data Valid
6
7
SPInSOMI
Master In Data
Must Be Valid
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
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SPIn slave mode timing parameters
SPIn slave mode external timing parameters (CLOCK PHASE = 0, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 13)
NO
1
2||
3||
#
MIN
MAX
100
256tc(ICLK)
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
td(SPCH-SOMI)S
Delay time, SPInCLK high to SPInSOMI valid (clock
polarity = 0)
12 + tr
td(SPCL-SOMI)S
Delay time, SPInCLK low to SPInSOMI valid (clock
polarity = 1)
12 + tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
tc(SPC)S – 12 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
tc(SPC)S – 12 – tf
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 0)
10
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 1)
10
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 0)
10
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 1)
10
4||
5||
6||
7||
UNIT
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is cleared.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
6
7
SPInSIMO
SPISIMO Data
Must Be Valid
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
46
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SPIn slave mode timing parameters (continued)
SPIn slave mode external timing parameters (CLOCK PHASE = 1, SPInCLK = input, SPInSIMO =
input, and SPInSOMI = output)†‡§¶ (see Figure 14)
NO
1
2||
3||
tc(SPC)S
Cycle time, SPInCLK
tw(SPCH)S
MIN
MAX
100
256tc(ICLK)
Pulse duration, SPInCLK high (clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPInCLK low (clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPInCLK high (clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tv(SOMI-SPCH)S
Valid time, SPInCLK high after SPInSOMI data valid
(clock polarity = 0)
0.5tc(SPC)S – 12 – tr
tv(SOMI-SPCL)S
Valid time, SPInCLK low after SPInSOMI data valid (clock
polarity = 1)
0.5tc(SPC)S – 12 – tf
tv(SPCH-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK high
(clock polarity = 0)
0.5tc(SPC)S – 12 – tr
tv(SPCL-SOMI)S
Valid time, SPInSOMI data valid after SPInCLK low (clock
polarity = 1)
0.5tc(SPC)S – 12 – tf
tsu(SIMO-SPCH)S
Setup time, SPInSIMO before SPInCLK high (clock
polarity = 0)
10
tsu(SIMO-SPCL)S
Setup time, SPInSIMO before SPInCLK low (clock
polarity = 1)
10
tv(SPCH-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK high
(clock polarity = 0)
10
tv(SPCL-SIMO)S
Valid time, SPInSIMO data valid after SPInCLK low (clock
polarity = 1)
10
4||
5||
6||
7
#
||
UNIT
ns
† The MASTER bit (SPInCTRL2.3) is cleared and the CLOCK PHASE bit (SPInCTRL2.0) is set.
‡ If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPInCTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
# When the SPIn is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ 100 ns, where PS is the prescale value set in the SPInCTL1.[12:5] register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ 100 ns.
||
The active edge of the SPInCLK signal referenced is controlled by the CLOCK POLARITY bit (SPInCTRL2.1).
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SPIn slave mode timing parameters (continued)
1
SPInCLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSOMI
SPISOMI Data Is Valid
Data Valid
6
7
SPInSIMO
SPISIMO Data Must
Be Valid
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
48
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MibSPI master mode timing parameters
MibSPI master mode external timing parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO
= output, and SPISOMI = input)†‡§ (see Figure 15)
NO.
1
2¶
3¶
tc(SPC)M
Cycle time, SPICLK ¶
MIN
MAX
UNIT
90
256tc(ICLK)
ns
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
0.5tc(SPC)M – tr
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
td(SPCH-SIMO)M
Delay time, SPICLK high to SPISIMO valid
(clock polarity = 0)
6
td(SPCL-SIMO)M
Delay time, SPICLK low to SPISIMO valid
(clock polarity = 1)
6
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low (clock
polarity = 0)
0.5tc(SPC)M – 5
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high (clock
polarity = 1)
0.5tc(SPC)M – 5
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 0)
tf(SPC) - tc(ICLK) + 5
tf(SPC) - 0.5tc(ICLK) + 5
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 1)
tr(SPC) - tc(ICLK) + 5
tr(SPC) - 0.5tc(ICLK) + 5
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after SPICLK low (clock
polarity = 0)
tc(ICLK) - tf(SPC) + 5
0.5tc(ICLK) - tf(SPC) + 5
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after SPICLK high (clock
polarity = 1)
tc(ICLK) - tr(SPC) + 5
0.5tc(ICLK) - tr(SPC) + 5
4¶
5¶
6¶
7¶
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPICTRL2.3) is set and the CLOCK PHASE bit (SPICTRL2.0) is cleared.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICTRK2.1).
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MibSPI master mode timing parameters (continued)
1
SPICLK
(clock polarity = 0)
2
3
SPInCLK
(clock polarity = 1)
4
5
SPInSIMO
SIMO Bit1
SIMO Bit0
6
7
Master In Data
Must Be Valid
SPISOMI
Figure 15. MibSPI Master Mode External Timing (CLOCK PHASE = 0)
50
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MibSPI master mode timing parameters (continued)
MibSPI master mode external timing parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO =
output, and SPISOMI = input)†‡§ (see Figure 16)
MIN
MAX
UNIT
90
256tc(ICLK)
ns
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
NO.
1
2¶
3¶
4
¶
tc(SPC)M
Cycle time, SPICLK
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 0)
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 1)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCL)M
Pulse duration, SPICLK low (clock polarity = 0)
0.5tc(SPC)M – tf
0.5tc(SPC)M + 5
tw(SPCH)M
Pulse duration, SPICLK high (clock polarity = 1)
0.5tc(SPC)M – tr
0.5tc(SPC)M + 5
tv(SIMO-SPCH)M
Valid time, SPICLK high after SPISIMO data valid
(clock polarity = 0)
0.5tc(SPC)M – 6
tv(SIMO-SPCL)M
Valid time, SPICLK low after SPISIMO data valid
(clock polarity = 1)
0.5tc(SPC)M – 6
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5tc(SPC)M – 5
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5tc(SPC)M – 5
tsu(SOMI-SPCH)M
Setup time, SPISOMI before SPICLK high
(clock polarity = 0)
tf(SPC) - tc(ICLK) + 5
tf(SPC) - 0.5tc(ICLK) + 5
tsu(SOMI-SPCL)M
Setup time, SPISOMI before SPICLK low
(clock polarity = 1)
tr(SPC) - tc(ICLK) + 5
tr(SPC) - 0.5tc(ICLK) + 5
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after SPICLK high
(clock polarity = 0)
tc(ICLK) - tf(SPC) + 5
0.5tc(ICLK) - tf(SPC) + 5
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after SPICLK low
(clock polarity = 1)
tc(ICLK) - tr(SPC) + 5
0.5tc(ICLK) - tr(SPC) + 5
¶
5¶
6¶
7¶
ns
ns
ns
ns
ns
ns
† The MASTER bit (SPICTRL2.3) is set and the CLOCK PHASE bit (SPICTRL2.0) is set.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICTRL2.1).
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MibSPI master mode timing parameters (continued)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISIMO
SIMO Bit0
SIMO Bit 1
6
7
SPISOMI
Master In Data
Must Be Valid
Figure 16. MibSPI Master Mode External Timing (CLOCK PHASE = 1)
52
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MibSPI slave mode timing parameters
MibSPI slave mode external timing parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)†‡§¶ (see Figure 17)
NO.
1
2
MIN
MAX
UNIT
90
256tc(ICLK)
ns
tc(SPC)S
Cycle time, SPICLK
tw(SPCH)S
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)S – 0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5 tc(ICLK) + trf(SOMI)
1.5 tc(ICLK) + trf(SOMI)
0.5 tc(ICLK) + trf(SOMI)
1.5 tc(ICLK) + trf(SOMI)
||
3||
td(SPCH-SOMI)S
4||
td(SPCL-SOMI)S
ns
ns
Delay time, SPICLK high to SPISOMI valid
(clock polarity = 0),
Delay time, SPICLK low to SPISPISOMI valid
(clock polarity = 1),
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK
high (clock polarity =0)
tc(SPC)S – tc(ICLK)
tc(SPC)S + tc(ICLK)
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK
low (clock polarity =1)
tc(SPC)S – tc(ICLK)
tc(SPC)S + tc(ICLK)
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low
(clock polarity = 0)
0.5 tc(ICLK) + 4
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high
(clock polarity = 1)
0.5 tc(ICLK) + 4
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK
low (clock polarity = 0)
0.5 tc(ICLK) + 6
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK
high (clock polarity = 1)
0.5 tc(ICLK) + 6
5||
6||
7
#
||
ns
ns
ns
† The MASTER bit (SPICTRL2.3) is cleared and the CLOCK PHASE bit (SPICTRL2.0) is cleared.
‡ If the MibSPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPICTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK), trf(SOMI) = Rise/Fall time of the SOMI pin.
# When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ Master Clock Period, where PS is the prescale value set in the SPICTL1.[12:5]
register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ Master Clock Period.
||
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICTRL2.1).
, MibSPI in Slave mode transmits data on the SPISOMI pin with respect to the receive edge of SPICLK.
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MibSPI slave mode timing parameters (continued)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
5
4
SPISOMI
SPISOMI Data Bit n
SPISOMI Data Bit n+1
6
7
SPISIMO
SPISIMO Data
Must Be Valid
Figure 17. MibSPI Slave Mode External Timing (CLOCK PHASE = 0)
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MibSPI slave mode timing parameters (continued)
MibSPI slave mode external timing parameters (CLOCK PHASE = 1, SPICLK = input, SPISIMO =
input, and SPISOMI = output)†‡§¶ (see Figure 18)
MIN
MAX
UNIT
2tc(ICLK)
256tc(ICLK)
ns
tw(SPCH)S
Pulse duration, SPICLK high
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPICLK low
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCL)S
Pulse duration, SPICLK low
(clock polarity = 0)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
tw(SPCH)S
Pulse duration, SPICLK high
(clock polarity = 1)
0.5tc(SPC)S –0.25tc(ICLK)
0.5tc(SPC)S + 0.25tc(ICLK)
0.5 tc(ICLK) + trf(SOMI)
1.5 tc(ICLK) + trf(SOMI)
0.5 tc(ICLK) + trf(SOMI)
1.5 tc(ICLK) + trf(SOMI)
NO.
1
tc(SPC)S
Cycle time, SPICLK
2||
3||
tv(SOMI-SPCH)S
4||
tv(SOMI-SPCL)S
#
Valid time, SPICLK high after SPISOMI
data valid (clock polarity = 0),
Valid time, SPICLK low after SPISOMI
data valid (clock polarity = 1),
ns
ns
ns
tv(SPCH-SOMI)S
Valid time, SPISOMI data valid after
SPICLK high (clock polarity = 0)
tc(SPC)S – tc(ICLK)
tc(SPC)S + tc(ICLK)
tv(SPCL-SOMI)S
Valid time, SPISOMI data valid after
SPICLK low (clock polarity = 1)
tc(SPC)S – tc(ICLK)
tc(SPC)S + tc(ICLK)
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high
(clock polarity = 0)
0.5 tc(ICLK) + 4
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low
(clock polarity = 1)
0.5 tc(ICLK) + 4
tv(SPCH-SIMO)S
Valid time, SPISIMO data valid after
SPICLK high (clock polarity = 0)
0.5 tc(ICLK) + 6
tv(SPCL-SIMO)S
Valid time, SPISIMO data valid after
SPICLK low (clock polarity = 1)
0.5 tc(ICLK) + 6
5||
6||
7||
ns
ns
ns
† The MASTER bit (SPICTRL2.3) is cleared and the CLOCK PHASE bit (SPICTRL2.0) is set.
‡ If the MibSPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(ICLK), where PS = prescale value set in SPICTL1.[12:5].
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
¶ tc(ICLK) = interface clock cycle time = 1/f(ICLK), trf(SOMI) = Rise/Fall time of the SOMI pin.
# When the MibSPI is in Slave mode, the following must be true:
For PS values from 1 to 255:
tc(SPC)S ≥ (PS +1)tc(ICLK) ≥ Master Clock Period, where PS is the prescale value set in the SPICTL1.[12:5]
register bits.
For PS values of 0:
tc(SPC)S = 2tc(ICLK) ≥ Master Clock Period.
||
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICTRL2.1).
, MibSPI in Slave mode transmits data on the SPISOMI pin with respect to the receive edge of SPICLK.
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MibSPI slave mode timing parameters (continued)
1
SPICLK
(clock polarity = 0)
2
3
SPICLK
(clock polarity = 1)
4
5
SPISOMI
SOMI Bit 1
SOMI Bit 0
6
7
SPISIMO
SPISIMO Data Must
Be Valid
Figure 18. MibSPI Slave Mode External Timing (CLOCK PHASE = 1)
56
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SCIn isosynchronous mode timings — internal clock
timing requirements for internal clock SCIn isosynchronous mode†‡§ (see Figure 19)
(BAUD + 1)
IS EVEN OR BAUD = 0
NO.
(BAUD + 1)
IS ODD AND BAUD ≠ 0
UNIT
MIN
MAX
MIN
MAX
2tc(ICLK)
224tc(ICLK)
3tc(ICLK)
(224 –1) tc(ICLK)
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCL)
Pulse duration,
SCInCLK low
0.5tc(SCC) – tf
0.5tc(SCC) + 5
0.5tc(SCC) +0.5tc(ICLK) – tf 0.5tc(SCC) +0.5tc(ICLK)
ns
3
tw(SCCH)
Pulse duration,
SCInCLK high
0.5tc(SCC) – tr
0.5tc(SCC) + 5
0.5tc(SCC) –0.5tc(ICLK) – tr 0.5tc(SCC) –0.5tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK
high to SCInTX valid
5
tv(TX)
Valid time, SCInTX data
after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX
before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data
- tc(ICLK) + tf + 20
after SCInCLK low
10
10
ns
ns
tc(SCC) – 10
tc(SCC) – 10
ns
tc(ICLK) + tf + 20
tc(ICLK) + tf + 20
ns
- tc(ICLK) + tf + 20
ns
† BAUD = 24-bit concatenated value formed by the SCI[H,M,L]BAUD registers.
‡ tc(ICLK) = interface clock cycle time = 1/f(ICLK)
§ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
1
3
2
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
Data Valid
NOTE A: Data transmission/reception characteristics for isosynchronous mode with internal clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 19. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
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SCIn isosynchronous mode timings — external clock
timing requirements for external clock SCIn isosynchronous mode†‡ (see Figure 20)
MIN
NO.
§
MAX
1
tc(SCC)
Cycle time, SCInCLK
2
tw(SCCH)
Pulse duration, SCInCLK high
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
3
tw(SCCL)
Pulse duration, SCInCLK low
0.5tc(SCC) – 0.25tc(ICLK)
0.5tc(SCC) + 0.25tc(ICLK)
ns
4
td(SCCH-TXV)
Delay time, SCInCLK high to SCInTX valid
2tc(ICLK) + 12 + tr
ns
8tc(ICLK)
5
tv(TX)
Valid time, SCInTX data after SCInCLK low
6
tsu(RX-SCCL)
Setup time, SCInRX before SCInCLK low
7
tv(SCCL-RX)
Valid time, SCInRX data after SCInCLK low
ns
2tc(SCC)–10
0
2tc(ICLK) + 10
1
2
3
SCICLK
5
4
SCITX
Data Valid
6
7
SCIRX
Data Valid
NOTE A: Data transmission/reception characteristics for isosynchronous mode with external clocking are similar to the asynchronous
mode. Data transmission occurs on the SCICLK rising edge, and data reception on the SCICLK falling edge.
Figure 20. SCIn Isosynchronous Mode Timing Diagram for External Clock
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ns
ns
† tc(ICLK) = interface clock cycle time = 1/f(ICLK)
‡ For rise and fall timings, see the "switching characteristics for output timings versus load capacitance" table.
§ When driving an external SCInCLK, the following must be true: tc(SCC) ≥ 8tc(ICLK)
58
UNIT
ns
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
high-end timer (HET) timings
minimum PWM output pulse width:
This is equal to one High Resolution Clock Period (HRP). The HRP is defined by the 6-bit High Resolution
Prescale Factor (hr) which is user defined, giving prescale factors of 1 to 64, with a linear increment of codes.
Therefore, the minimum PWM output pulse width = HRP(min) = hr(min)/SYSCLK = 1/SYSCLK
For example, for a SYSCLK of 30 MHz, the minimum PWM output pulse width = 1/30 = 33.33ns
minimum input pulses we can capture:
The input pulse width must be greater or equal to the Low Resolution Clock Period (LRP), i.e., the HET loop
(the HET program must fit within the LRP). The LRP is defined by the 3-bit Loop-Resolution Prescale Factor
(lr), which is user defined, with a power of 2 increment of codes. That is, the value of lr can be 1, 2, 4, 8, 16, or 32.
Therefore, the minimum input pulse width = LRP(min) = hr(min) * lr(min)/SYSCLK = 1 * 1/SYSCLK
For example, with a SYSCLK of 30 MHz, the minimum input pulse width = 1 * 1/30 = 33.33 ns
Note: Once the input pulse width is greater than LRP, the resolution of the measurement is still HRP. (That is,
the captured value gives the number of HRP clocks inside the pulse.)
Abbreviations:
High resolution clock period = HRP = hr/SYSCLK
Loop resolution clock period = LRP = hr*lr/SYSCLK
hr = HET high resolution divide rate = 1, 2, 3,...63, 64
lr = HET low resolution divide rate = 1, 2, 4, 8, 16, 32
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59
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
high-end CAN controller (HECC) and standard CAN controller (SCC) mode timings
dynamic characteristics for the CANHTX, CANHRX, CANSTX and CANSRX pins
MIN
MAX
UNIT
td(CANHTX/CNASTX)
Delay time, transmit shift register to CANHTX/CANSTX pin†
15
ns
td(CANHRX/CANSRX)
Delay time, CANHRX/CANSRX pin to receive shift register
5
ns
† These values do not include rise/fall times of the output buffer.
60
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
multi-buffered A-to-D converter (MibADC)
The multi-buffered A-to-D converter (MibADC) has a separate power bus for its analog circuitry that enhances
the A-to-D performance by preventing digital switching noise on the logic circuitry which could be present on
VSS and VCC from coupling into the A-to-D analog stage. All A-to-D specifications are given with respect to
ADREFLO unless otherwise noted.
Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 bits (1024 values)
Monotonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Assured
Output conversion code . . . . . . . . . . . . . . . . . . . . . . . 00h to 3FFh [00 for VAI ≤ADREFLO; 3FF for VAI ≥ ADREFHI]
MibADC recommended operating conditions†
ADREFHI
ADREFLO
MIN
MAX
UNIT
A-to-D high-voltage reference source
VSSAD
VCCAD
V
A-to-D low-voltage reference source
VSSAD
VCCAD
V
VSSAD − 0.3
VCCAD + 0.3
V
VAI
Analog input voltage
IAIC
Analog input clamp current‡
(VAI < VSSAD – 0.3 or VAI > VCCAD + 0.3)
−2
2
mA
† For VCCAD and VSSAD recommended operating conditions, see the "device recommended operating conditions" table.
‡ Input currents into any ADC input channel outside the specified limits could affect conversion results of other channels.
operating characteristics over full ranges of recommended operating conditions§¶
PARAMETER
Ra
Analog input resistance
Rb
Sample switch resistance
TYP
MAX
UNIT
See Figure 21
250
500
Ω
See Figure 21
250
500
Ω
Conversion
10
pF
Sampling
30
pF
1
μA
5
mA
DESCRIPTION/CONDITIONS
Ci
Analog input capacitance
See Figure 21
IAIL
Analog input leakage current
See Figure 21
IADREFHI
ADREFHI input current
ADREFHI = 3.6 V, ADREFLO = VSSAD
CR
Conversion range over which specified
accuracy is maintained
ADREFHI − ADREFLO
EDNL
Differential nonlinearity error
Difference between the actual step width and the
ideal value. (See Figure 23)
EINL
ETOT
MIN
–1
3
3.6
V
±1.5
LSB
Integral nonlinearity error
Maximum deviation from the best straight line through
the MibADC. MibADC transfer characteristics,
excluding the quantization error.
(See Figure 24)
±2
LSB
Total error/Absolute Accuracy
Maximum value of the difference between an analog
value and the ideal midstep value.
(See Figure 25)
±2
LSB
§ VCCAD = ADREFHI
¶ 1 LSB = (ADREFHI – ADREFLO)/210 for the MibADC
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61
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
multi-buffered A-to-D converter (MibADC) (continued)
Sample Switch
Rs
Ra
ADINx
Sample
Capacitor
Parasitic
Capacitance
Vsrc
To ADC
Comparator
Rb
Rleak
CI
Figure 21. MibADC Input Equivalent Circuit
multi-buffer ADC timing requirements
MIN
MAX
UNIT
μs
tc(ADCLK)
Cycle time, MibADC clock
td(SH)
Delay time, sample and hold time
1
μs
td(C)
Delay time, conversion time
0.55
μs
td(SHC)†
Delay time, total sample/hold and conversion time
1.55
μs
0.05
† This is the minimum sample/hold and conversion time that can be achieved. These parameters are dependent on many factors; for more
details, see the TMS470R1x Multi-Buffered Analog-to-Digital Converter (MibADC) Reference Guide (literature number SPNU206).
Tclk
CLK
Tsu
Th
Ta
START
Reset Period
Conversion Period
Comparator
Reset
SAR
Reset
EOC
LSB
Valid
Tdv
Tdh
DATA
MSB
Valid
MSB-1
Valid
DATA
Valid
Figure 22. MibADC Timing Diagram
62
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MSB
Valid
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
multi-buffered A-to-D converter (MibADC) (continued)
The differential nonlinearity error shown in Figure 23 (sometimes referred to as differential linearity) is the
difference between an actual step width and the ideal value of 1 LSB.
0 ... 110
Digital Output Code
0 ... 101
0 ... 100
0 ... 011
Differential
Linearity Error (1/2 LSB)
1 LSB
0 ... 010
0 ... 001
Differential Linearity
Error (–1/2 LSB)
1 LSB
0 ... 000
0
1
2
3
4
Analog Input Value (LSB)
5
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
Figure 23. Differential Nonlinearity (DNL)
The integral nonlinearity error shown in Figure 24 (sometimes referred to as linearity error) is the deviation of
the values on the actual transfer function from a straight line.
0 ... 111
Digital Output Code
0 ... 110
Ideal
Transition
0 ... 101
Actual
Transition
0 ... 100
At Transition
011/100
(– 1/2 LSB)
0 ... 011
0 ... 010
End-Point Lin. Error
0 ... 001
At Transition
001/010 (– 1/4 LSB)
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 24. Integral Nonlinearity (INL) Error
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63
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
multi-buffer A-to-D converter (MibADC) (continued)
The absolute accuracy or total error of an MibADC as shown in Figure 25 is the maximum value of the difference
between an analog value and the ideal midstep value.
0 ... 111
Digital Output Code
0 ... 110
0 ... 101
0 ... 100
Total Error
At Step 0 ... 101
(–1 1/4 LSB)
0 ... 011
0 ... 010
Total Error
At Step
0 ... 001 (1/2 LSB)
0 ... 001
0 ... 000
0
1
2
3
4
5
6
Analog Input Value (LSB)
NOTE A: 1 LSB = (ADREFHI – ADREFLO)/210
7
Figure 25. Absolute Accuracy (Total) Error
64
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANAURY 2004 – REVISED JANUARY 2006
MECHANICAL DATA
GJZ (S-PBGA-N176)
PLASTIC BALL GRID ARRAY
15,20
14,80 SQ
13,20
SQ
12,80
13,00 TYP
1,00
0,50
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A1 Corner
0,50
1,00
1 2 3 4 5 6 7 8 9 10 1112 13 14
Bottom View
0,56 REF
0,60
0,40
2,05 MAX
Seating Plane
0,10 C
0,70
0,50
0,10
C
4203226-2/E 03/03
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Thermal Resistance Characteristics†
PARAMETER
°C/W
RΘJA
34.31
RΘJC
7.51
†Assuming power dissipation = 0.6W; ambient temperature = 70C;
PCB = 4-layer metal 101.50 x 114.50 x 1.60mm
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65
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
List of Figures
Functional Block Diagram
Figure 1. Memory Map
Figure 2. TMS470R1x Family Nomenclature
Figure 3. Test Load Circuit
Figure 4. Crystal/Clock Connection
Figure 5. CLKOUT Timing Diagram
Figure 6. ECLK Timing Diagram
Figure 7. PORRST Timing Diagram
Figure 8. JTAG Scan Timing
Figure 9. CMOS-Level Outputs
Figure 10. CMOS-Level Inputs
Figure 11. SPIn Master Mode External Timing (CLOCK PHASE = 0)
Figure 12. SPIn Master Mode External Timing (CLOCK PHASE = 1)
Figure 13. SPIn Slave Mode External Timing (CLOCK PHASE = 0)
Figure 14. SPIn Slave Mode External Timing (CLOCK PHASE = 1)
Figure 15. MibSPI Master Mode External Timing (CLOCK PHASE = 0)
Figure 16. MibSPI Master Mode External Timing (CLOCK PHASE = 1)
Figure 17. MibSPI Slave Mode External Timing (CLOCK PHASE = 0)
Figure 18. MibSPI Slave Mode External Timing (CLOCK PHASE = 1)
Figure 19. SCIn Isosynchronous Mode Timing Diagram for Internal Clock
Figure 20. SCIn Isosynchronous Mode Timing Diagram for External Clock
Figure 21. MibADC Input Equivalent Circuit
Figure 22. MibADC Timing Diagram
Figure 23. Differential Nonlinearity (DNL)
Figure 24. Integral Nonlinearity (INL) Error
Figure 25. Absolute Accuracy (Total) Error
Mechanical Data
66
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TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
SPNS082D – JANUARY 2004 – REVISED JANUARY 2006
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Device Characteristics
Memory Selection Assignment
Flash Sector Addresses
VF478 Peripherals, System Module, and Flash Base Addresses
DMA Request Lines Connections
Interrupt Priority
MibADC Event Hookup Configuration
MibSPI Event Hookup Configuration
TMS470 Device ID Bit Allocation Register
Device Part Number
Average FMPLL Frequency (OSCIN = 7.5MHz, SYSCLK = 60MHz, CAN = 500kHz)
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67
TMS470R1VF478
16/32-BIT RISC FLASH MICROCONTROLLER
REVISION HISTORY
REVISION HISTORY
REV
D
DATE
1/06
NOTES
Updates:
Document status moved to Production Data.
Page 12, SCC and SCC RAM added to memory map.
Page 60, dynamic characteristics updated to include CANSTX and CANSRX pins.
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67
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