TN0604 N-Channel Enhancement-Mode Vertical DMOS FET Features General Description ► ► ► ► ► ► ► ► This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex’s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Low threshold — 1.6V max. High input impedance Low input capacitance — 140pF typical Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage Complementary N- and P-channel devices Supertex’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Applications ► ► ► ► ► ► ► Logic level interfaces – ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches The Quad-Array package (20-Lead SOW (WG)) uses four independent DMOS transistors which provide four independent channels. Ordering Information RDS(ON) ID(ON) VGS(th) (V) max (Ω) min (A) max (V) TO-92 20-Lead SOW 40 0.75 4.0 1.6 TN0604N3-G - 40 1.0 4.0 1.6 - TN0604WG-G BVDSS/BVDGS Package Options -G indicates package is RoHS compliant (‘Green’) Pin Configurations Absolute Maximum Ratings Parameter Value Drain-to-source voltage BVDSS Drain-to-gate voltage BVDGS Gate-to-source voltage ±20V Operating and storage temperature DRAIN -55OC to +150OC Soldering temperature* 300OC Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. GATE TO-92 (N3) 20-Lead SOW (WG) Product Marking Top Marking YYWW TN 0604W G LLLLLLLLLL Product Marking TN 0604 YYWW YY = Year Sealed WW = Week Sealed = “Green” Packaging TO-92 (N3) DRAIN1 DRAIN1 DRAIN1 GATE1 SOURCE1 SOURCE2 GATE2 DRAIN2 DRAIN2 DRAIN2 SOURCE DRAIN4 DRAIN4 DRAIN4 GATE4 SOURCE4 SOURCE3 GATE3 DRAIN3 DRAIN3 DRAIN3 Bottom Marking CCCCCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = “Green” Packaging *May be part of top marking 20-Lead SOW (WG) TN0604 Thermal Characteristics (continuous)(1) (pulsed) Power Dissipation @TA = 25OC (A) (A) (W) TO-92 (N3) 0.7 4.6 20-Lead SOW (WG) 1.0 4.0 ID Package ID θjc θja O IDR(1) IDRM O ( C/W) ( C/W) (A) (A) 0.74 125 170 0.7 4.6 1.5 - 84 1.0 4.0 Notes: (1) ID (continuous) is limited by max rated Tj . Electrical Characteristics (@25 C unless otherwise specified) O Sym Parameter BVDSS VGS(th) ΔVGS(th) Min Typ Max Units Conditions Drain-to-source breakdown voltage 40 - - V VGS = 0V, ID = 2.0mA Gate threshold voltage 0.6 - 1.6 V VGS = VDS, ID= 1.0mA O Change in VGS(th) with temperature - -3.8 -4.5 IGSS Gate body leakage - - 100 nA VGS = ± 20V, VDS = 0V - - 10 µA VGS = 0V, VDS = Max Rating IDSS Zero gate voltage drain current - - 1.0 mA VGS = 0V, VDS = 0.8 Max Rating, TA = 125°C ID(ON) ON-state drain current 1.5 2.1 - 4.0 7.0 - TO-92/ 20-Lead SOW - 1.0 1.6 RDS(ON) Static drain-to-source ON-state resistance TO-92 - 0.6 0.75 20-Lead SOW - - 1.0 - 0.5 0.75 0.5 0.8 - ΔRDS(ON) Change in RDS(ON) with temperature mV/ C VGS = VDS, ID= 2.5mA A VGS = 5.0V, VDS = 20V VGS = 10V, VDS = 20V VGS = 5.0V, ID = 0.75A Ω %/OC VGS = 10V, ID = 1.5A VGS = 10V, ID = 1.5A GFS Forward transductance CISS Input capacitance - 140 190 COSS Common source output capacitance - 75 110 CRSS Reverse transfer capacitance - 25 50 td(ON) Turn-ON delay time - - 10 Rise time - - 6.0 Turn-OFF delay time - - 25 Fall time - - 20 Diode forward voltage drop - 1.2 1.8 V VGS = 0V, ISD = 1.5A Reverse recovery time - 300 - ns VGS = 0V, ISD = 1.0A tr td(OFF) tf VSD trr mmho VDS = 20V, ID = 1.5A pF ns VGS = 0V, VDS = 20V, f = 1.0MHz VDD = 20V, ID = 0.5A, RGEN = 25Ω Notes: (1) All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300µs pulse, 2% duty cycle.) (2) All A.C. parameters sample tested. Switching Waveforms and Test Circuit VDD 10V 90% INPUT 0V PULSE GENERATOR 10% t(ON) td(ON) VDD t(OFF) tr 10% td(OFF) tF D.U.T. 10% OUTPUT 90% OUTPUT RGEN INPUT 0V RL 90% 2 TN0604 Typical Performance Curves Output Characteristics Saturation Characteristics 10 10 8 8 VGS = VGS = 9V 6 ID (amperes) ID (amperes) 10V 8V 7V 4 6V 9V 8V 4 7V 6V 5V 2 10V 6 5V 2 4V 4V 3V 3V 0 0 10 20 30 40 0 50 0 2 4 6 8 10 VDS (volts) VDS (volts) Transconductance vs. Drain Current Power Dissipation vs. Case Temperature 2.0 2.0 TA = -55°C PD (watts) GFS (siemens) VDS DS= 25V TA = 25°C 1.0 TA = 125°C 0 TO-92 1.0 0 0 1 2 3 4 5 6 7 0 50 25 Maximum Rated Safe Operating Area 100 125 150 Thermal Response Characteristics 1.0 10 Thermal Resistance (normalized) TO-92 (pulsed) ID (amperes) 75 TC (° C) ID (amperes) 1.0 TO-92 (DC) 0.1 0.8 0.6 0.4 TO-92 T C = 25°C P D = 1W 0.2 T C = 25°C 0.01 0.1 1 10 0 0.001 100 VDS (volts) 0.01 0.1 tp (seconds) 3 1 10 TN0604 Typical Performance Curves (cont.) BVDSS Variation with Temperature On-Resistance vs. Drain Current 2.0 1.1 RDS(ON) (ohms) BVDSS (normalized) VGS = 5V 1.0 VGS = 10V 1.0 0.9 0 -50 0 50 100 150 5.0 0 10.0 Tj (°C) ID (amperes) Transfer Characteristics V(th) and RDS Variation with Temperature 10 VDS = 25V 1.4 1.4 = TA C ° 55 - = °C 25 TA 4 = 5 12 °C TA V(th) @ 1mA 1.2 1.2 R DS @ 10V, 1.5A 1.0 1.0 0.8 0.8 0.6 0.6 2 0 0 2 4 6 8 10 -50 0 50 VGS (volts) Capacitance vs. Drain-to-Source Voltage 150 Gate Drive Dynamic Characteristics 200 10 f = 1MHz 8 C ISS VDS = 10V VGS (volts) 150 C (picofarads) 100 Tj (°C) 100 COSS 170 pF 170 pF 6 VDS = 40V 4 50 2 CRSS 0 0 0 10 20 30 0 40 1.0 2.0 3.0 QG (nanocoulombs) VDS (volts) 4 4.0 5.0 RDS(ON) (normalized) 6 VGS(th) (normalized) ID (amperes) 8 TN0604 3-Lead TO-92 Package Outline (N3) D A 1 Seating Plane 2 3 L b C e1 e Side View Front View E1 E 3 1 2 Bottom View Symbol Dimension (inches) A b C D E E1 e e1 L MIN .170 .014 .014 .175 .125 .080 .095 .045 .500 NOM - - - - - - - - - MAX .210 .022 .022 .205 .165 .105 .105 .055 - Drawings not to scale. 5 TN0604 20-Lead SOW (Wide Body) Package Outline (WG) 12.80x7.50mm body, 2.65mm height (max), 1.27mm pitch D θ1 20 E1 E L2 Note 1 (Index Area 0.25D x 0.75E1) L Seating Plane θ L1 1 Top View View B A View B h A A2 e Note 1 h Seating Plane A1 Gauge Plane b A Side View View A-A Note 1: This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. Symbol MIN Dimension NOM (mm) MAX A 2.15 2.65 A1 0.10 0.30 A2 2.05 2.55 b 0.31 0.51 D 12.60 12.80 13.00 E E1 9.97 10.30 10.63 e 7.40 7.50 7.60 h 0.25 1.27 BSC 0.75 L L1 L2 0.40 1.27 θ 0 1.40 REF 0.25 BSC O 8 O θ1 5O 15O JEDEC Registration MS-013, Variation AC, Issue E, Sep. 2005. Drawings not to scale. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Doc.# DSFP-TN0604 A102507 6