TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 15W,30W,50W Filter-Free Class-D Stereo Amplifier Family with AM Avoidance Check for Samples: TPA3116D2 , TPA3118D2, TPA3130D2 FEATURES DESCRIPTION • The TPA31xxD2 series are stereo efficient, digital amplifier power stage for driving speakers up to 100W/2Ω in mono. The high efficiency of the TPA3130D2 allows it to do 2x15W without external heat sink on a single layer PCB. The TPA3118D2 can even run 2x30W/8Ω without heat sink on a dual layer PCB. If even higher power is needed the TPA3116D2 does 2x50W/4Ω with a small heat-sink attached to its top side PowerPad. All three devices share the same footprint enabling a single PCB to be used across different power levels. 1 • • • • • • • • • • • Supports Multiple Output Configurations – 2×50-W into a 4-Ω BTL Load at 21 V (TPA3116D2) – 2×30-W into a 8-Ω BTL Load at 24 V (TPA3118D2) – 2×15-W into a 8-Ω BTL Load at 15 V (TPA3130D2) Wide Voltage Range: 4.5 V – 26 V Efficient Class-D Operation – >90% Power Efficiency Combined with Low Idle Loss Greatly Reduces Heat Sink Size – Advanced Modulation Schemes Multiple Switching Frequencies – AM Avoidance – Master/Slave Synchronization – Up to 1.2 MHz Switching Frequency Feedback Power Stage Architecture with High PSRR Reduces PSU Requirements Programmable Power Limit Differential/Single-Ended Inputs Stereo and Mono Mode with Single Filter Mono Configuration Single Power Supply Reduces Component Count Integrated Self-Protection Circuits Including Over-Voltage, Under-Voltage, OverTemperature, DC-Detect, and Short Circuit with Error Reporting Thermally Enhanced Packages – DAD (32-pin HTSSOP Pad-up) – DAP (32-pin HTSSOP Pad-down) –40°C to 85°C Ambient Temperature Range The TPA31xxD2 advanced oscillator/PLL circuit employs a multiple switching frequency option to avoid AM interferences; this is achieved together with an option of Master/Slave option, making it possible to synchronize multiple devices. The TPA31xxD2 devices are fully protected against faults with short-circuit protection and thermal protection as well as over-voltage, under-voltage and DC protection. Faults are reported back to the processor to prevent devices from being damaged during overload conditions. Simplified Application Circuit Tuner AM/FM Audio Processor And control Right CD/ MP3 4.5 V-26 V PSU TPA3116D2 PBTL Detect Left Right LC Filter Left LC Filter SDZ MUTE Aux in FAULTZ AM /FM Avoidance Control GAIN control and Master /Slave setting Power Limit Capable of synchronizing to other devices AM2,1,0 GAIN/SLV PLIMIT Sync DEVICE POWER HTSSOP 32-PIN TPA3130D2 2 x 15W/8Ω Pad down (DAP) TPA3118D2 2 x 30W/8Ω Pad down (DAP) TPA3116D2 2 x 50W/4Ω Pad up (DAD) APPLICATIONS • • • • Mini-Micro Component, Speaker Bar, Docks After-Market Automotive CRT TV Consumer Audio Applications 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. TERMINAL ASSIGNMENT TPA3116D2 32-PIN HTSSOP PACKAGE (DAD) TPA3130D2 and TPA3118D2 32-PIN HTSSOP PACKAGE (DAP) PACKAGE (TOP VIEW) MODSEL 1 PACKAGE (TOP VIEW) 32 PVCC MODSEL 1 32 PVCC SDZ 2 31 PVCC SDZ 2 31 PVCC FAULTZ 3 30 BSPR FAULTZ 3 30 BSPR RINP 4 29 OUTPR RINP 4 29 OUTPR RINN 5 28 GND RINN 5 28 GND PLIMIT 6 27 OUTNR PLIMIT 6 27 OUTNR GVDD 7 26 BSNR GVDD 7 26 BSNR GAIN/SLV 8 GND GAIN/SLV 8 GND 24 BSPL GND 9 Thermal PAD 25 9 Thermal PAD 25 GND 24 BSPL LINP 10 Top 23 OUTPL LINP 10 Bottom 23 OUTPL LINN 11 22 GND LINN 11 22 GND MUTE 12 21 OUTNL MUTE 12 21 OUTNL AM2 13 20 BSNL AM2 13 20 BSNL AM1 14 19 PVCC AM1 14 19 PVCC AM0 15 18 PVCC AM0 15 18 PVCC SYNC 16 17 AVCC SYNC 16 17 AVCC Terminal Functions PIN NO. TYPE (1) DESCRIPTION 1 MODSEL I Mode selection logic input (LOW = BD mode, HIGH = 1 SPW mode). TTL logic levels with compliance to AVCC. 2 SDZ I Shutdown logic input for audio amp (LOW = outputs Hi-Z, HIGH = outputs enabled). TTL logic levels with compliance to AVCC. 3 FAULTZ 4 RINP I Positive audio input for right channel. Biased at 3 V. 5 RINN I Negative audio input for right channel. Biased at 3 V. 6 PLIMIT I Power limit level adjust. Connect a resistor divider from GVDD to GND to set power limit. Connect directly to GVDD for no power limit. 7 GVDD PO Internally generated gate voltage supply. Not to be used as a supply or connected to any component other than a 1 µF X7R ceramic decoupling capacitor and the PLIMIT and GAIN/SLV resistor dividers. 8 GAIN/SLV I Selects Gain and selects between Master and Slave mode depending on pin voltage divider. DO General fault reporting including Over-temp, DC Detect. Open drain. FAULTZ = High, normal operation FAULTZ = Low, fault condition 9 GND G Ground 10 LINP I Positive audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 11 LINN I Negative audio input for left channel. Biased at 3 V. Connect to GND for PBTL mode. 12 MUTE I Mute signal for fast disable/enable of outputs (HIGH = outputs Hi-Z, LOW = outputs enabled). TTL logic levels with compliance to AVCC. 13 AM2 I AM Avoidance Frequency Selection 14 AM1 I AM Avoidance Frequency Selection (1) 2 NAME TYPE: DO = Digital Output, I = Analog Input, G = General Ground, PO = Power Output, BST = Boot Strap. Copyright © 2012, Texas Instruments Incorporated TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 Terminal Functions (continued) PIN NO. NAME TYPE (1) I DESCRIPTION 15 AM0 16 SYNC DIO 17 AVCC P Analog Supply 18 PVCC P Power supply 19 PVCC P Power supply 20 BSNL BST Boot strap for negative left channel output, connect to 220 nF X5R, or better ceramic cap to OUTPL 21 OUTNL PO Negative left channel output 22 GND 23 OUTPL PO Positive left channel output 24 BSPL BST Boot strap for positive left channel output, connect to 220 nF X5R, or better ceramic cap to OUTNL 25 GND G 26 BSNR BST Boot strap for negative right channel output, connect to 220 nF X5R, or better ceramic cap to OUTNR 27 OUTNR PO Negative right channel output 28 GND 29 OUTPR PO Positive right channel output 30 BSPR BST Boot strap for positive right channel output, connect to 220 nF X5R or better ceramic cap to OUTPR 31 PVCC P Power supply 32 PVCC P Power supply 33 Thermal Pad or PowerPAD G Connect to GND for best system performance. If not connected to GND, leave floating. G G AM Avoidance Frequency Selection Clock input/output for synchronizing multiple class-D devices. Direction determined by GAIN/SLV terminal. Ground Ground Ground Copyright © 2012, Texas Instruments Incorporated 3 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com SYSTEM BLOCK DIAGRAM GVDD SDZ MUTE PVCC BSPR PVCC TTL Buffer Modulation and PBTL Select Gain Control OUTPR_FB Gate Drive GAIN OUTPR + OUTPR FB – RINP RINN Gain Control + – + – + PLIMIT – + – GND PWM Logic GVDD – PVCC BSNR PVCC OUTPNR FB OUTNR_ FB + FAULTZ Gate Drive OUTNR SC Detect GND SYNC GAIN/SLV Ramp Generator AM<2:0> Startup Protection Logic Biases and References PLIMIT Reference PLIMIT DC Detect Thermal Detect UVLO/OVLO GVDD AVDD AVCC PVCC LDO Regulator GVDD Gate Drive GVDD OUTNL + OUTNL_FB OUTNL_ FB – – LINN LINP BSNL PVCC Gain Control – + + + – GND PWM Logic PLIMIT GVDD + PVCC BSPL PVCC OUTPL_FB – Input Sense Gate Drive Modulation and PBTL Select PBTL Select OUTPL OUTPL_FB GND GND Thermal Pad 4 Copyright © 2012, Texas Instruments Incorporated TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage, VCC Input voltage, VI Slew rate, maximum (2) VALUE UNIT PVCC, AVCC –0.3 to 30 V INPL, INNL, INPR, INNR –0.3 to 6.3 V PLIMIT, GAIN / SLV, SYNC –0.3 to GVDD+0.3 V AM0, AM1, AM2, MUTE, SDZ, MODSEL –0.3 to PVCC+0.3 V 10 V/msec Operating free-air temperature, TA AM0, AM1, AM2, MUTE, SDZ, MODSEL –40 to 85 °C Operating junction temperature range, TJ –40 to 150 °C Storage temperature range, Tstg –40 to 125 °C ±2 kV ±500 V Electrostatic discharge: Human body model, ESD Electrostatic discharge: Charged device model, ESD (1) (2) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 100 kΩ series resistor is needed if maximum slew rate is exceeded. THERMAL INFORMATION THERMAL METRIC (1) TPA3130D2 TPA3118D2 TPA3116D2 DAP 1 Layer PCB (2) DAP 2 Layer PCB (3) DAD Heatsink (4) 32 PINS 32 PINS 32 PINS θJA Junction-to-ambient thermal resistance 36 22 14 ψJT Junction-to-top characterization parameter 0.4 0.3 1.2 ψJB Junction-to-board characterization parameter 5.9 4.8 5.7 (1) (2) (3) (4) UNITS °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For the PCB layout please see the TPA3130D2EVM user guide. A 1 layer 90x85mm 1oc PCB was used For the PCB layout please see the TPA3130D2EVM user guide. A 2 layer 90x85mm 1oc PCB was used The heat sink drawing used for the thermal model data are shown in the application section, size: 14mm wide, 50mm long, 25mm high. RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM PVCC, AVCC VIH High-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL VIL Low-level input voltage AM0, AM1, AM2, MUTE, SDZ, SYNC, MODSEL 0.8 V VOL Low-level output voltage FAULTZ, RPULL-UP = 100 kΩ, PVCC = 26 V 0.8 V IIH High-level input current AM0, AM1, AM2, MUTE, SDZ, MODSEL (VI = 2 V, VCC = 18 V) 50 µA Output filter: L = 10 µH, C = 680 nF Minimum load Impedance RL(PBTL) Lo Output filter: L = 10 µH, C = 1 µF Output-filter Inductance 2 3.2 4 TPA3130D2 5.6 8 TPA3116D2, TPA3118D2 1.6 TPA3130D2 3.2 Ω 4 1 Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 V V TPA3116D2, TPA3118D2 Minimum output filter inductance under short-circuit condition Copyright © 2012, Texas Instruments Incorporated 26 UNIT Supply voltage RL(BTL) 4.5 MAX VCC µH 5 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com DC ELECTRICAL CHARACTERISTICS TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS | VOS | Class-D output offset voltage (measured differentially) ICC Quiescent supply current ICC(SD) Quiescent supply current in shutdown mode rDS(on) Drain-source on-state resistance, measured pin to pin G G MIN TYP MAX VI = 0 V, Gain = 36 dB 1.5 15 SDZ = 2 V, No load or filter, PVCC = 12 V 20 35 SDZ = 2 V, No load or filter, PVCC = 24 V 32 50 SDZ = 0.8 V, No load or filter, PVCC = 12 V <50 SDZ = 0.8 V, No load or filter, PVCC = 24 V 50 PVCC = 21 V, Iout = 500 mA, TJ = 25°C Gain (BTL) Gain (SLV) 400 120 19 20 21 R1 = 100 kΩ, R2 = 20 kΩ 25 26 27 R1 = 100 kΩ, R2 = 39 kΩ 31 32 33 R1 = 75 kΩ, R2 = 47 kΩ 35 36 37 R1 = 51 kΩ, R2 = 51 kΩ 19 20 21 R1 = 47 kΩ, R2 = 75 kΩ 25 26 27 R1 = 39 kΩ, R2 = 100 kΩ 31 32 33 R1 = 16 kΩ, R2 = 100 kΩ 35 36 37 Turn-on time SDZ = 2 V tOFF Turn-off time SDZ = 0.8 V GVDD Gate drive supply IGVDD < 200 µA VO Output voltage maximum under PLIMIT control V(PLIMIT) = 2 V; VI = 1 Vrms mV mA µA mΩ R1 = open, R2 = 20 kΩ ton UNIT 10 dB dB dB dB ms 2 µs 6.4 6.9 7.4 V 6.75 7.90 8.75 V TYP MAX UNIT AC ELECTRICAL CHARACTERISTICS TA = 25°C, AVCC = PVCC = 12 V to 24 V, RL = 4 Ω (unless otherwise noted) PARAMETER TEST CONDITIONS MIN 200 mVPP ripple at 1 kHz, Gain = 20 dB, Inputs ACcoupled to GND KSVR Power supply ripple rejection PO Continuous output power THD+N Total harmonic distortion + noise VCC = 21 V, f = 1 kHz, PO = 25 W (half-power) Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz Signal-to-noise ratio Maximum output at THD+N < 1%, f = 1 kHz, Gain = 20 dB, A-weighted SNR fOSC Oscillator frequency –70 THD+N = 10%, f = 1 kHz, PVCC = 14.4 V 25 THD+N = 10%, f = 1 kHz, PVCC = 21 V 50 dB W 0.1% 65 µV –80 dBV –100 dB 102 dB AM2=0, AM1=0, AM0=0 376 400 424 AM2=0, AM1=0, AM0=1 470 500 530 AM2=0, AM1=1, AM0=0 564 600 636 AM2=0, AM1=1, AM0=1 940 1000 1060 AM2=1, AM1=0, AM0=0 1128 1200 1278 kHz AM2=1, AM1=0, AM0=1 AM2=1, AM1=1, AM0=0 Reserved AM2=1, AM1=1, AM0=1 Thermal trip point Thermal hysteresis Over current trip point 6 Submit Documentation Feedback 150+ °C 15 °C TPA3130D2 4.5 TPA3118D2, TPA3116D2 7.5 A Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION +NOISE (BTL) vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY 10 10 PO = 0.5W PO = 1W PO = 2.5W Gain = 26dB PVCC = 6V TA = 25°C RL = 4Ω 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 PO = 1W PO = 2.5W PO = 5W Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω 0.1 0.01 20 100 1k Frequency (Hz) 10k 0.001 20k 20 100 1k Frequency (Hz) 10k 20k G002 G003 Figure 1. Figure 2. TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY 10 10 PO = 1W PO = 5W PO = 10W Gain = 26dB PVCC = 24V TA = 25°C RL = 4Ω 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.001 PO = 1W PO = 2.5W PO = 5W Gain = 26dB PVCC = 12V TA = 25°C RL = 8Ω 0.1 0.01 20 100 1k Frequency (Hz) 10k 20k 0.001 20 100 1k Frequency (Hz) 10k G004 G005 Figure 3. Copyright © 2012, Texas Instruments Incorporated 20k Figure 4. Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 7 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE (BTL) vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER 10 10 PO = 1W PO = 5W PO = 10W Gain = 26dB PVCC = 24V TA = 25°C RL = 8Ω Gain = 26dB PVCC = 6V TA = 25°C RL = 4Ω 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 f = 20Hz f = 1kHz f = 6kHz 0.001 20 100 1k Frequency (Hz) 10k 0.001 0.01 20k 0.1 1 Output Power (W) 10 G006 G008 Figure 5. Figure 6. TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER 10 10 Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω Gain = 26dB PVCC = 24V TA = 25°C RL = 4Ω 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 f = 20Hz f = 1kHz f = 6kHz 1 Output Power (W) 10 40 0.001 0.01 0.1 1 Output Power (W) G009 Submit Documentation Feedback 100 G010 Figure 7. 8 10 Figure 8. Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE (BTL) vs OUTPUT POWER 10 10 Gain = 26dB PVCC = 12V TA = 25°C RL = 8Ω Gain = 26dB PVCC = 24V TA = 25°C RL = 8Ω 1 THD+N (%) 0.1 0.01 0.1 0.01 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 f = 20Hz f = 1kHz f = 6kHz 1 Output Power (W) 10 0.001 0.01 50 0.1 1 Output Power (W) 10 50 G011 G012 Figure 9. Figure 10. OUTPUT POWER (BTL) vs PLIMIT VOLTAGE GAIN/PHASE (BTL) vs FREQUENCY 50 Gain = 26dB TA = 25°C PVCC = 24V RL = 4Ω 300 20 200 10 100 0 0 30 Gain (dB) Output Power (W) 40 30 20 −10 −100 −20 −200 −300 −30 10 Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω −40 −50 0 0 1 2 PLIMIT Voltage (V) 3 Phase (°) THD+N (%) 1 20 100 −400 Gain Phase 1k Frequency (Hz) 10k −500 100k 4 G014 G013 Figure 11. Copyright © 2012, Texas Instruments Incorporated Figure 12. Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 9 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) MAXIMUM OUTPUT POWER (BTL) vs SUPPLY VOLTAGE MAXIMUM OUTPUT POWER (BTL) vs SUPPLY VOLTAGE 50 Gain = 26dB TA = 25°C RL = 8Ω 45 Maximum Output Power (W) Maximum Output Power (W) 40 35 30 25 20 15 10 5 0 THD+N = 1% THD+N = 10% 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 26 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 5 0 Gain = 26dB TA = 25°C RL = 4Ω THD+N = 1% THD+N = 10% 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 26 G016 Figure 14. POWER EFFICIENCY (BTL) vs OUTPUT POWER POWER EFFICIENCY (BTL) vs OUTPUT POWER 100 100 90 90 80 80 70 70 Power Efficiency (%) Power Efficiency (%) G015 Figure 13. 60 50 40 30 50 40 30 20 20 PVCC = 6V PVCC =12V PVCC = 24V Gain = 26dB TA = 25°C RL = 8Ω 10 0 60 0 5 10 15 20 25 30 35 Output Power (W) 40 45 50 0 PVCC = 6V PVCC = 12V PVCC = 24V Gain = 26dB TA = 25°C RL = 4Ω 10 0 5 10 15 20 25 30 35 Output Power (W) G017 Submit Documentation Feedback 45 50 G018 Figure 15. 10 40 Figure 16. Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 0 Gain = 26dB PVCC = 24V TA = 25°C RL = 8Ω −10 −20 −30 −30 −40 −40 −50 −50 Crosstalk (dB) Crosstalk (dB) −20 −60 −70 −80 −60 −70 −80 −90 −90 −100 −100 −110 −110 −120 −120 Right to Left Left to Right −130 −140 Gain = 26dB PVCC = 12V TA = 25°C RL = 4Ω −10 20 100 1k Frequency (Hz) 10k Right to Left Left to Right −130 −140 20k 20 100 1k Frequency (Hz) 10k 20k G021 G022 Figure 17. Figure 18. SUPPLY RIPPLE REJECTION RATIO (BTL) vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE (PBTL) vs FREQUENCY 10 0 Gain = 26dB PVCC = 12VDC + 200mVP-P TA = 25°C RL = 8Ω −10 −20 Gain = 26dB PVCC = 12V TA = 25°C RL = 2Ω 1 −40 THD+N (%) kSVR (dB) −30 −50 −60 0.1 −70 0.01 −80 −90 −100 PO = 1W PO = 5W PO = 10W Left Channel Right Channel 20 100 1k Frequency (Hz) 10k 20k 0.001 20 100 1k Frequency (Hz) 10k G023 G024 Figure 19. Copyright © 2012, Texas Instruments Incorporated 20k Figure 20. Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 11 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE (PBTL) vs OUTPUT POWER MAXIMUM OUTPUT POWER (PBTL) vs SUPPLY VOLTAGE 180 10 Gain = 26dB PVCC = 12V TA = 25°C RL = 2Ω 140 Maximum Output Power (W) 1 THD+N (%) Gain = 26dB TA = 25°C RL = 2Ω 160 0.1 0.01 120 100 80 60 40 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 20 0.1 1 Output Power (W) 10 0 40 THD+N = 1% THD+N = 10% 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 26 G027 Figure 22. POWER EFFICIENCY (PBTL) vs OUTPUT POWER SUPPLY RIPPLE REJECTION RATIO (PBTL) vs FREQUENCY 100 0 90 −10 80 −20 70 −30 60 −40 kSVR (dB) Power Efficiency (%) G025 Figure 21. 50 40 30 −50 −60 −70 20 −80 PVCC = 6V PVCC = 12V PVCC =24V Gain = 26dB TA = 25°C RL = 2Ω 10 0 Gain = 26dB PVCC = 12VDC + 200mVP-P TA = 25°C RL = 2Ω 0 10 20 30 40 50 60 70 Output Power (W) 80 90 −90 100 −100 20 100 1k Frequency (Hz) G028 Submit Documentation Feedback 20k G030 Figure 23. 12 10k Figure 24. Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 TYPICAL CHARACTERISTICS (continued) fs = 400 kHz, BD Mode (unless otherwise noted) TOTAL HARMONIC DISTORTION + NOISE (PBTL) vs OUTPUT POWER MAXIMUM OUTPUT POWER (PBTL) vs SUPPLY VOLTAGE 10 140 Gain = 26dB PVCC = 24V TA = 25°C RL = 3Ω Gain = 26dB TA = 25°C RL = 3Ω 130 120 110 Maximum Output Power (W) THD+N (%) 1 0.1 100 90 80 70 60 50 40 0.01 30 20 f = 20Hz f = 1kHz f = 6kHz 0.001 0.01 0.1 THD+N = 1% THD+N = 10% 10 1 10 Output Power (W) 100 200 0 4 6 8 10 12 14 16 18 Supply Voltage (V) 20 22 24 G032 G034 Figure 25. Copyright © 2012, Texas Instruments Incorporated 26 Figure 26. Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 13 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com DEVICE INFORMATION TYPICAL APPLICATION OUTPUT LC FILTER 16 BSNL AM1 PVCC AM0 PVCC SY NC AVCC C19 OUT_P_RIGHT 1 1 2 1 2 2 OUT_N_RIGHT 1 1 2 2 2 OUT_P_LEFT 1 R17 3.3R C32 1nF C38 10nF + GND PVCC 17 C29 680nF C25 220uF SYNC 2 C24 100nF 1 L9 10uH GND C40 10nF C33 1nF 4R - R18 3.3R 2 1 GND PVCC DECOUPLING PVCC DECOUPLING 1 1 1 2 PVCC C47 220uF 2 2 2 C46 100nF 2 12 13 R22 100k 1 14 15 16 INPL INNL MUTE AM2 GND OUTNL BSNL AM1 PVCC AM0 PVCC SY NC AVCC 22 20 1 19 C44 OUT_P_SUB 1 2 1 2 2 GND GND C56 10nF C54 1nF 2 1 2 R24 3.3R - 220nF L16 18 10uH PVCC 17 C48 1nF C49 100nF 2 2 TPA3116D2 2R C52 1uF 1 C41 1nF + 220nF 220nF 2 23 21 1 1 2 C43 C43 1 C55 10nF 2 1 BSPL OUTPL 25 24 1 GND GND GND 1 OUT_N_SUB 11 GND MUTE_SUB GAIN/SLV BSNR 27 26 R23 3.3R C53 1nF 1 2 12 2 10 GVDD OUTNR 10uH C51 1uF 2 R21 75k 9 8 GND PLIMIT 28 1 7 INNR L15 29 2 R20 47k OUTPR EMI C-RC SNUBBER 2 1 1 6 BSPR INPR 1 220nF 2 2 1uF FAULTZ OUTPUT LC FILTER C42 1 30 1 5 PVCC 1 4 1 SDZ 31 2 3 GND 32 GND 1uF 1 PVCC GND /SD_SUB MODSEL GND 2 1 Power Pad 1 GND U2 2 1 2 220nF C45 1nF R19 100k 2 10uH 18 PVCC C36 1 1 2 1 19 C23 1nF R73 10k 2 L10 C28 680nF 20 TPA3116D2 C35 2 10uH 1 2 21 L8 1 1 22 R16 3.3R 2 2 OUTNL 220nF 220nF 2 23 GND C39 1uF 1 2 2 AM2 GND C17 C18 1 24 1 2 MUTE OUTPL 25 2 1 R14 100k INNL 1 OUT_ N_LEFT 15 2 INPL GND BSPL 26 GND C50 220uF 2 1 GND BSNR 1 MUTE_LR GAIN/SLV OUTNR C31 1nF C27 680nF 1 2 14 GVDD 28 27 - C37 10nF 2 C14 1uF PLIMIT 29 1 13 GND 2 1 OUTPR INNR GND 1 11 C13 1uF 2 1 INPR 30 GND 2 12 2 2 10 BSPR + 220nF 2 1 9 8 12 IN_N_SUB C34 10nF 4R C16 1 2 R12 20k 2 IN_P_SUB C30 1nF 31 1 7 FAULTZ 32 2 R11 100k PVCC 2 1 1 6 PVCC SDZ 1 1uF MODSEL GND 5 IN_N_LEFT R15 3.3R GND GND 4 IN_P_LEFT C26 680nF GND 3 1 C12 GND 10uH C22 220uF U1 2 1uF 1 2 C15 1uF L7 C21 100nF EMI C-RC SNUBBER 2 2 C11 2 IN_N_RIGHT C20 1nF GND C58 100nF 1 GND /SD_LR IN_P_RIGHT 2 1 1 1 R10 3.3R R13 100k GND GND PVCC 2 2 1 2 1 2 C57 10nF Power Pad PVCC 1 1 1 2 PVCC DECOUPLING PVCC GND PVCC DECOUPLING Figure 27. Schematic A 2.1 solution, U1 TPA3116D2 in Master mode 400 kHz, BTL, gain if 20 dB, power limit not implemented. U2 in Slave, PBTL mode gain of 20dB. Inputs are connected for differential inputs. In the following sections the TPA3116D2, TPA3118D2, and TPA3130D2 are referred to as: TPA31xxD2 family. 14 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 GAIN SETTING AND MASTER / SLAVE The gain of the TPA31xxD2 family is set by the voltage divider connected to the GAIN/SLV control pin. Master or Slave mode is also controlled by the same pin. An internal ADC is used to detect the 8 input states. The first four stages sets the GAIN in Master mode in gains of 20, 26, 32, 36 dB respectively, while the next four stages sets the GAIN in Slave mode in gains of 20, 26, 32, 36 dB respectively. The gain setting is latched during power-up and cannot be changed while device is powered. Table 1 shows the recommended resistor values and the state and gain: Table 1. GAIN and MASTER/SLAVE MASTER / SLAVE MODE GAIN R1 (to GND) (1) R2 (to GVDD) (1) INPUT IMPEDANCE Master 20 dB 5.6 kΩ OPEN 60 kΩ Master 26 dB 20 kΩ 100 kΩ 30 kΩ Master 32 dB 39 kΩ 100 kΩ 15 kΩ Master 36 dB 47 kΩ 75 kΩ 9 kΩ Slave 20 dB 51 kΩ 51 kΩ 60 kΩ Slave 26 dB 75 kΩ 47 kΩ 30 kΩ Slave 32 dB 100 kΩ 39 kΩ 15 kΩ Slave 36 dB 100 kΩ 16 kΩ 9 kΩ (1) Resistor tolerance should be 5% or better. 5 2 1 C5 1 µF 2 2 1 R1 INNR 6 1 R2 51 k 51 k PLIMIT 7 GVDD 8 GAIN/SLV 9 GND 10 In Master mode, SYNC terminal is an output, in Slave mode, SYNC terminal is an input for a clock input. TTL logic levels with compliance to GVDD. INPUT IMPEDANCE The TPA31xxD2 family input stage is a fully differential input stage and the input impedance changes with the gain setting from 9 kΩ at 36 dB gain to 60 kΩ at 20 dB gain. Table 1 lists the values from min to max gain. The tolerance of the input resistor value is ±20% so the minimum value will be higher than 7.2 kΩ. The inputs need to be AC-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages during powerON and power-OFF. The input ac-coupling capacitor together with the input impedance forms a high-pass filter with the following cut-off frequency: 1 ƒf = 2pZiCi (1) If a flat bass response is required down to 20 Hz the recommended cut-off frequency is a tenth of that, 2 Hz. Table 2 lists the recommended ac-couplings capacitors for each gain step. If a -3 dB is accepted at 20 Hz 10 times lower capacitors can used – for example, a 1 µF can be used. Table 2. Recommended Input AC-Coupling Capacitors GAIN INPUT IMPEDANCE INPUT CAPACITANCE HIGH-PASS FILTER 20 dB 60 kΩ 1.5 µF 1.8 Hz 26 dB 30 kΩ 3.3 µF 1.6 Hz 32 dB 15 kΩ 5.6 µF 2.3 Hz 36 dB 9 kΩ 10 µF 1.8 Hz Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 15 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com Zf Ci IN Input Signal Zi The input capacitors used should be a type with low leakage, like quality electrolytic, tantalum or ceramic. If a polarized type is used the positive connection should face the input pins which are biased to 3 Vdc. START-UP/SHUTDOWN OPERATION The TPA31xxD2 family employs a shutdown mode of operation designed to reduce supply current (Icc) to the absolute minimum level during periods of nonuse for power conservation. The SDZ input terminal should be held high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling SDZ low will put the outputs to mute and the amplifier to enter a low-current state. It is not recommended to leave SDZ unconnected, because amplifier operation would be unpredictable. For the best power-off pop performance, place the amplifier in the shutdown mode prior to removing the power supply. The gain setting is selected at the end of the start-up cycle. At the end of the start-up cycle, the gain is selected and cannot be changed until the next power-up. PLIMIT OPERATION The TPA31xxD2 family has a built-in voltage limiter that can be used to limit the output voltage level below the supply rail, the amplifier simply operates as if it was powered by a lower supply voltage, and thereby limits the output power. Add a resistor divider from GVDD to ground to set the voltage at the PLIMIT pin. An external reference may also be used if tighter tolerance is required. Add a 1 µF capacitor from pin PLIMIT to ground to ensure stability. It is recommended to connect PLIMIT to GVDD when using 1SPW-modulation mode. Figure 28. POWER LIMIT Example The PLIMIT circuit sets a limit on the output peak-to-peak voltage. The limiting is done by limiting the duty cycle to a fixed maximum value. This limit can be thought of as a "virtual" voltage rail which is lower than the supply connected to PVCC. This "virtual" rail is approximately 4 times the voltage at the PLIMIT pin. This output voltage can be used to calculate the maximum output power for a given maximum input voltage and speaker impedance. 16 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com POUT SLOS708B – APRIL 2012 – REVISED MAY 2012 ææ ö ö RL çç ç ÷ ´ VP ÷÷ è RL + 2 ´ RS ø ø = è 2 ´ RL 2 for unclipped power (2) Where: RS is the total series resistance including RDS(on), and output filter resistance. RL is the load resistance. VP is the peak amplitude VP = 4 × PLIMIT voltage if PLIMIT < 4 × VP POUT (10%THD) = 1.25 × POUT (unclipped) Table 3. POWER LIMIT Example PVCC (V) R to GND R to GVDD OUTPUT VOLTAGE (Vrms) GVDD Short Open 17.90 24 V 3.3 45 kΩ 51 kΩ 12.67 24 V 2.25 24 kΩ 51 kΩ 9.00 12 V GVDD Short Open 10.33 12 V 2.25 24 kΩ 51 kΩ 9.00 12 V 1.5 18 kΩ 68 kΩ 6.30 24 V (1) PLIMIT VOLTAGE (V) (1) PLIMIT measurements taken with EVM gain set to 26dB and input voltage set to 1Vrms. GVDD SUPPLY The GVDD Supply is used to power the gates of the output full bridge transistors. It can also be used to supply the PLIMIT and GAIN/SLV voltage dividers. Decouple GVDD with a X5R ceramic 1 µF capacitor to GND. The GVDD supply is not intended to be used for external supply. It is recommended to limit the current consumption by using resistor voltage dividers for GAIN/SLV and PLIMIT of 100 kΩ or more. BSPx AND BSNx CAPACITORS The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the high side of each output to turn on correctly. A 220 nF ceramic capacitor of quality X5R or better, rated for at least 16 V, must be connected from each output to its corresponding bootstrap input. (See the application circuit diagram in Figure 27.) The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the highside MOSFETs turned on. DIFFERENTIAL INPUTS The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To use the TPA31xxD2 family with a differential source, connect the positive lead of the audio source to the RINP or LINP input and the negative lead from the audio source to the RINN or LINN input. To use the TPA31xxD2 family with a single-ended source, ac ground the negative input through a capacitor equal in value to the input capacitor on positive and apply the audio source to either input. In a single-ended input application, the unused input should be ac grounded at the audio source instead of at the device input for best noise performance. For good transient performance, the impedance seen at each of the two differential inputs should be the same. The impedance seen at the inputs should be limited to an RC time constant of 1 ms or less if possible. This is to allow the input dc blocking capacitors to become completely charged during the 10 ms power-up time. If the input capacitors are not allowed to completely charge, there will be some additional sensitivity to component matching which can result in pop if the input components are not well matched. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 17 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com MONO MODE (PBTL) The TPA31xxD2 family can be connected in MONO mode enabling up to 100W output power. This is done by: • Connect INPL and INNL directly to Ground (without capacitors) this sets the device in Mono mode during power up. • Connect OUTPR and OUTNR together for the positive speaker terminal and OUTNL and OUTPL together for the negative terminal • Analog input signal is applied to INPR and INNR TPA3116D2 4.5 V–26 V PSU OUTPR OUTNR Right LC Filter PBTL Detect Left OUTPL OUTNL DEVICE PROTECTION SYSTEM The TPA31xxD2 family contains a complete set of protection circuits carefully designed to make system design efficient as well as to protect the device against any kind of permanent failures due to short circuits, overload, over temperature, and under-voltage. The FAULTZ pin will signal if an error is detected according to the fault table below: Table 4. Fault Reporting FAULT TRIGGERING CONDITION (typical value) FAULTZ ACTION LATCHED/SELFCLEARING Over Current Output short or short to PVCC or GND Low Output high impedance Latched Over Temperature Tj > 150°C Low Output high impedance Latched Too High DC Offset DC output voltage Low Output high impedance Latched Under Voltage on PVCC PVCC < 4.5V – Output high impedance Self-clearing Over Voltage on PVCC PVCC > 27V – Output high impedance Self-clearing DC DETECT PROTECTION The TPA31xxD2 family has circuitry which will protect the speakers from DC current which might occur due to defective capacitors on the input or shorts on the printed circuit board at the inputs. A DC detect fault will be reported on the FAULT pin as a low state. The DC Detect fault will also cause the amplifier to shutdown by changing the state of the outputs to Hi-Z. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the DC Detect protection latch. A DC Detect Fault is issued when the output differential duty-cycle of either channel exceeds 60% for more than 420 msec at the same polarity. Table x below shows some examples of the typical DC Detect Protection threshold for several values of the supply voltage. This feature protects the speaker from large DC currents or AC currents less than 2Hz. To avoid nuisance faults due to the DC detect circuit, hold the SD pin low at powerup until the signals at the inputs are stable. Also, take care to match the impedance seen at the positive and negative inputs to avoid nuisance DC detect faults. The minimum output offset voltages required to trigger the DC detect are show in Table 5. The outputs must remain at or above the voltage listed in the table for more than 420 msec to trigger the DC detect. 18 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 Table 5. DC Detect Threshold PVCC (V) VOS - OUTPUT OFFSET VOLTAGE (V) 4.5 0.96 6 1.30 12 2.60 18 3.90 SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE The TPA31xxD2 family has protection from over current conditions caused by a short circuit on the output stage. The short circuit protection fault is reported on the FAULTZ pin as a low state. The amplifier outputs are switched to a high impedance state when the short circuit protection latch is engaged. The latch can be cleared by cycling the SDZ pin through the low state. If automatic recovery from the short circuit protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the shortcircuit protection latch. In systems where a possibility of a permanent short from the output to PVDD or to a high voltage battery like a car battery can occur, pull the MUTE pin low with the FAULTZ signal with a inverting transistor to ensure a highZ restart, like shown in the figure below: > 1.4sec SDZ mP MUTE TPA3116D2 FAULTZ SDZ MUTE FAULTZ Figure 29. MUTE Driven by Inverted FAULTZ Figure 30. Timing Requirement for SDZ THERMAL PROTECTION Thermal protection on the TPA31xxD2 family prevents damage to the device when the internal die temperature exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature exceeds the thermal trip point, the device enters into the shutdown state and the outputs are disabled. This is a latched fault. Thermal protection faults are reported on the FAULTZ terminal as a low state. If automatic recovery from the thermal protection latch is desired, connect the FAULTZ pin directly to the SDZ pin. This allows the FAULTZ pin function to automatically drive the SDZ pin low which clears the thermal protection latch. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 19 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com TPA3116/18/30D2 MODULATION SCHEME The TPA31xxD2 family has the option of running in either BD modulation or 1SPW modulation; this is set by the MODSEL pin. MODSEL = GND: BD-modulation This is a modulation scheme that allows operation without the classic LC reconstruction filter when the amp is driving an inductive load with short speaker wires. Each output is switching from 0 volts to the supply voltage. The OUTPx and OUTNx are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTPx is greater than 50% and OUTNx is less than 50% for positive output voltages. The duty cycle of OUTPx is less than 50% and OUTNx is greater than 50% for negative output voltages. The voltage across the load sits at 0V throughout most of the switching period, reducing the switching current, which reduces any I2R losses in the load. OUTP OUTN No Output OUTP- OUTN 0V Speaker Current OUTP OUTN Positive Output PVCC OUTP-OUTN 0V Speaker Current 0A OUTP Negative Output OUTN OUTP - OUTN 0V - PVCC Speaker Current 0A Figure 31. BD Mode Modulation 20 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 MODSEL = HIGH: 1SPW-modulation The 1SPW mode alters the normal modulation scheme in order to achieve higher efficiency with a slight penalty in THD degradation and more attention required in the output filter selection. In 1SPW mode the outputs operate at ~15% modulation during idle conditions. When an audio signal is applied one output will decrease and one will increase. The decreasing output signal will quickly rail to GND at which point all the audio modulation takes place through the rising output. The result is that only one output is switching during a majority of the audio cycle. Efficiency is improved in this mode due to the reduction of switching losses. The THD penalty in 1SPW mode is minimized by the high performance feedback loop. The resulting audio signal at each half output has a discontinuity each time the output rails to GND. This can cause ringing in the audio reconstruction filter unless care is taken in the selection of the filter components and type of filter used. OUTP OUTN OUTP -OUTN No Output 0V Speaker Current OUTP OUTN Positive Output PVCC OUTP -OUTN 0V Speaker Current 0A OUTP Negative Output OUTN OUTP -OUTN 0V - PVCC Speaker Current 0A Figure 32. 1SPW Mode Modulation Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 21 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com EFFICIENCY: LC FILTER REQUIRED WITH THE TRADITIONAL CLASS-D MODULATION SCHEME The main reason that the traditional class-D amplifier-based on AD modulation needs an output filter is that the switching waveform results in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the time at that voltage. The differential voltage swing is 2 × VCC, and the time at each voltage is half the period for the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive, whereas an LC filter is almost purely reactive. The TPA3116D2 modulation scheme has little loss in the load without a filter because the pulses are short and the change in voltage is VCC instead of 2 × VCC. As the output power increases, the pulses widen, making the ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most applications the filter is not needed. An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow through the filter instead of the load. The filter has less resistance but higher impedance at the switching frequency than the speaker, which results in less power dissipation, therefore increasing efficiency. FERRITE BEAD FILTER CONSIDERATIONS Using the Advanced Emissions Suppression Technology in the TPA3116D2 amplifier it is possible to design a high efficiency class-D audio amplifier while minimizing interference to surrounding circuits. It is also possible to accomplish this with only a low-cost ferrite bead filter. In this case it is necessary to carefully select the ferrite bead used in the filter. One important aspect of the ferrite bead selection is the type of material used in the ferrite bead. Not all ferrite material is alike, so it is important to select a material that is effective in the 10 to 100 MHz range which is key to the operation of the class-D amplifier. Many of the specifications regulating consumer electronics have emissions limits as low as 30 MHz. It is important to use the ferrite bead filter to block radiation in the 30 MHz and above range from appearing on the speaker wires and the power supply lines which are good antennas for these signals. The impedance of the ferrite bead can be used along with a small capacitor with a value in the range of 1000 pF to reduce the frequency spectrum of the signal to an acceptable level. For best performance, the resonant frequency of the ferrite bead/ capacitor filter should be less than 10 MHz. Also, it is important that the ferrite bead is large enough to maintain its impedance at the peak currents expected for the amplifier. Some ferrite bead manufacturers specify the bead impedance at a variety of current levels. In this case it is possible to make sure the ferrite bead maintains an adequate amount of impedance at the peak current the amplifier will see. If these specifications are not available, it is also possible to estimate the bead current handling capability by measuring the resonant frequency of the filter output at low power and at maximum power. A change of resonant frequency of less than fifty percent under this condition is desirable. Examples of ferrite beads which have been tested and work well with the TPA3130D2 can be seen in the TPA3130D2EVM user guide SLOU341. A high quality ceramic capacitor is also needed for the ferrite bead filter. A low ESR capacitor with good temperature and voltage characteristics will work best. Additional EMC improvements may be obtained by adding snubber networks from each of the class-D outputs to ground. Suggested values for a simple RC series snubber network would be 18 Ω in series with a 330 pF capacitor although design of the snubber network is specific to every application and must be designed taking into account the parasitic reactance of the printed circuit board as well as the audio amp. Take care to evaluate the stress on the component in the snubber network especially if the amp is running at high PVCC. Also, make sure the layout of the snubber network is tight and returns directly to the GND pins on the IC. 22 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com SLOS708B – APRIL 2012 – REVISED MAY 2012 Figure 33. WHEN TO USE AN OUTPUT FILTER FOR EMI SUPPRESSION The TPA3116D2 has been tested with a simple ferrite bead filter for a variety of applications including long speaker wires up to 125 cm and high power. The TPA3116D2 EVM passes FCC class-B specifications under these conditions using twisted speaker wires. The size and type of ferrite bead can be selected to meet application requirements. Also, the filter capacitor can be increased if necessary with some impact on efficiency. There may be a few circuit instances where it is necessary to add a complete LC reconstruction filter. These circumstances might occur if there are nearby circuits which are sensitive to noise. In these cases a classic second order Butterworth filter similar to those shown in the figures below can be used. Some systems have little power supply decoupling from the AC line but are also subject to line conducted interference (LCI) regulations. These include systems powered by "wall warts" and "power bricks." In these cases, LC reconstruction filters can be the lowest cost means to pass LCI tests. Common mode chokes using low frequency ferrite material can also be effective at preventing line conducted interference. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 23 TPA3116D2 TPA3118D2 TPA3130D2 SLOS708B – APRIL 2012 – REVISED MAY 2012 www.ti.com 10 µH OUTP C2 L1 0.68 µF 4W-8W 10 µH OUTN C3 L2 0.68 µF Ferrite Chip Bead OUTP 1 nF 4W-8W Ferrite Chip Bead OUTN 1 nF Figure 34. AM AVOIDANCE EMI REDUCTION To reduce interference in the AM radio band, the TPA3116D2 has the ability to change the switching frequency via AM<2:0> pins. The recommended frequencies are listed in Table 6. The fundamental frequency and its second harmonic straddle the AM radio band listed. This eliminates the tones that can be present due to the switching frequency being demodulated by the AM radio. Table 6. AM Frequencies US EUROPEAN AM FREQUENCY (kHz) AM FREQUENCY (kHz) SWITCHING FREQUENCY (kHz) AM2 AM1 AM0 500 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 522-540 540-917 540-914 917-1125 914-1122 600 (or 400) 1125-1375 1122-1373 500 1375-1547 1373-1548 600 (or 400) 1547-1700 1548-1701 600 (or 500) PRINTED-CIRCUIT BOARD (PCB LAYOUT) The TPA3116D2 can be used with a small, inexpensive ferrite bead output filter for most applications. However, since the class-D switching edges are fast, it is necessary to take care when planning the layout of the printed circuit board. The following suggestions will help to meet EMC requirements. • Decoupling capacitors — The high-frequency decoupling capacitors should be placed as close to the PVCC and AVCC terminals as possible. Large (100 μF or greater) bulk power supply decoupling capacitors should be placed near the TPA3116D2 on the PVCC supplies. Local, high-frequency bypass capacitors should be placed as close to the PVCC pins as possible. These caps can be connected to the IC GND pad directly for an excellent ground connection. Consider adding a small, good quality low ESR ceramic capacitor between 220 pF and 1 nF and a larger mid-frequency cap of value between 100 nF and 1 µF also of good quality to the PVCC connections at each end of the chip. • Keep the current loop from each of the outputs through the ferrite bead and the small filter cap and back to GND as small and tight as possible. The size of this current loop determines its effectiveness as an antenna. • Grounding — The PVCC decoupling capacitors should connect to GND. All ground should be connected at the IC GND, which should be used as a central ground connection or star ground for the TPA3116D2. 24 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 TPA3116D2 TPA3118D2 TPA3130D2 www.ti.com • SLOS708B – APRIL 2012 – REVISED MAY 2012 Output filter — The ferrite EMI filter (see Figure 34) should be placed as close to the output terminals as possible for the best EMI performance. The LC filter should be placed close to the outputs. The capacitors used in both the ferrite and LC filters should be grounded. For an example layout, see the TPA3116D2 Evaluation Module (TPA3116D2EVM) User Manual. Both the EVM user manual and the thermal pad application report are available on the TI Web site at http://www.ti.com. HEAT SINK USED ON THE EVM The heat sink (part number ATS-TI 10 OP-521-C1-R1) used on the EVM is an 14x25x50 mm extruded aluminum heat sink with three fins (see drawing below). For additional information on the heat sink, go to www.qats.com. 50.00±0.38 [1.969±.015] SINK LENGTH MACHINE THESE 3 EDGES AFTER ANODIZATION 0.00 25.00 –0.60 +.000 .984 –.024 SINK HEIGHT 3.00 [.118] 1.00 [.118] 6.35 [.250] 3.00 [.118] 40.00 [1.575] 30.50 [1.201] 19.50 [.768] 10.00 [.394] 0 [.000] 13.90±0.38 [.547±.015] BASE WIDTH 6.95 [.274] 5.00 [.197] 40.00 [1.575] 2X 4-40 x 6.5 Figure 35. EVM Heatsink This size heat sink has shown to be sufficient for continuous output power. The crest factor of music and having airflow will lower the requirement for the heat sink size and smaller types can be used. Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TPA3116D2 TPA3118D2 TPA3130D2 25 PACKAGE OPTION ADDENDUM www.ti.com 16-May-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TPA3116D2DAD ACTIVE HTSSOP DAD 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3116D2DADR ACTIVE HTSSOP DAD 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3118D2DAP ACTIVE HTSSOP DAP 32 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3118D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3130D2DAP ACTIVE HTSSOP DAP 32 46 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TPA3130D2DAPR ACTIVE HTSSOP DAP 32 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 16-May-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPA3116D2DADR HTSSOP DAD 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 TPA3118D2DAPR HTSSOP DAP 32 2000 330.0 TPA3130D2DAPR HTSSOP DAP 32 2000 330.0 24.4 8.6 11.5 1.6 12.0 24.0 Q1 24.4 8.6 11.5 1.6 12.0 24.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 16-May-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPA3116D2DADR HTSSOP DAD 32 2000 346.0 346.0 41.0 TPA3118D2DAPR HTSSOP DAP 32 2000 346.0 346.0 41.0 TPA3130D2DAPR HTSSOP DAP 32 2000 346.0 346.0 41.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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