TI TPA2037D1YFFT

TPA2037D1
www.ti.com
SLOS648 – OCTOBER 2009
3.2W Mono Class-D Audio Power Amplifier
With 6-dB Gain and Auto Short-Circuit Recovery
Check for Samples : TPA2037D1
FEATURES
APPLICATIONS
•
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1
•
•
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•
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Powerful Mono Class-D Speaker Amplifier
– 3.24 W (4 Ω, 5 V, 10% THDN)
– 2.57 W (4 Ω, 5 V, 1% THDN)
– 1.80 W (8 Ω, 5 V, 10% THDN)
– 1.46 W (8 Ω, 5 V, 1% THDN)
+6 dB Fixed Gain
Integrated Image Reject Filter for DAC Noise
Reduction
Low Output Noise of 20 μV
Low Quiescent Current of 1.5 mA
Differential Input Impedance of 300 kΩ
Auto-Recovering Short-Circuit Protection
Thermal-Overload Protection
Filter-Free Mono Class-D Amp
9-Ball 1,21 mm × 1,16 mm 0,4mm Pitch WCSP
Wireless or Cellular Handsets and PDAs
Portable Navigation Devices
General Portable Audio Devices
DESCRIPTION
The TPA2037D1 is a 3.2 W high efficiency filter-free
class-D audio power amplifier (class-D amp) with
6 dB of fixed gain in a tiny 1.21 mm x 1.16 mm wafer
chip scale package (WCSP). The device requires
only one external component.
Features like 95% efficiency, 1.5 mA quiescent
current, 0.1 μA shutdown current, 81-dB PSRR,
20 μV output noise and improved RF immunity make
the TPA2037D1 class-D amplifier ideal for cellular
handsets. A fast start-up time of 4 ms with no audible
pop makes the TPA2037D1 ideal for PDA and
smart-phone applications.
APPLICATION CIRCUIT
VDD
IN+
VO+
–
PWM
To battery
Cs
Internal
Oscillator
H-Bridge
VO+
TPA2037D1
9-BALL 0.4mm PITCH
WAFER CHIP SCALE PACKAGE (YFF)
(TOP VIEW OF PCB)
IN+
GND
VO-
A1
A2
A3
VDD
PVDD
PGND
B1
B2
B3
IN-
EN
VO+
C1
C2
C3
EN
Bias
Circuitry
GND
1.160 mm
IN-
TPA 2037 D1
1.214 mm
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009, Texas Instruments Incorporated
TPA2037D1
SLOS648 – OCTOBER 2009
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
TA
PACKAGED DEVICES
—40°C to 85°C
(1)
(2)
(1)
PART NUMBER
9-ball WSCP
(2)
SYMBOL
TPA2037D1YFFR
OCA
TPA2037D1YFFT
OCA
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com
The YFF package is only available taped and reeled. The suffix "R" indicates a reel of 3000, the suffix "T" indicates a reel of 250.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range, TA = 25°C (unless otherwise noted) (1)
VALUE
UNIT
In active mode
–0.3 to 6.0
V
In shutdown mode
–0.3 to 6.0
V
–0.3 to VDD + 0.3
V
3.2
Ω
VDD, PVDD
Supply voltage
VI
Input voltage
RL
Minimum load resistance
EN, IN+, IN–
Output continuous total power dissipation
See Dissipation Rating Table
TA
Operating free-air temperature range
–40 to 85
°C
TJ
Operating junction temperature range
–40 to 150
°C
Tstg
Storage temperature range
–65 to 85
°C
(1)
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
DERATING FACTOR
YFF (WCSP)
(1)
(1)
4.2 mW/°C
TA < 25°C
TA = 70°C
TA = 85°C
525 mW
336 mW
273 mW
Derating factor measure with high K board.
RECOMMENDED OPERATING CONDITIONS
VDD,
PVDD
Class-D supply voltage
VIH
High-level input voltage
EN
VIL
Low-level input voltage
EN
VIC
Common mode input voltage range
VDD = 2.5V, 5.5V, CMRR ≥ 49 dB
TA
Operating free-air temperature
2
MIN
MAX
2.5
5.5
1.3
V
V
0.35
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UNIT
V
0.75
VDD-1.1
V
–40
85
°C
Copyright © 2009, Texas Instruments Incorporated
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SLOS648 – OCTOBER 2009
ELECTRICAL CHARACTERISTICS
TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
|VOS|
Output offset voltage (measured
differentially)
VI = 0 V, VDD = 2.5 V to 5.5 V
|IIH|
High-level EN input current
VDD = 5.5 V, VEN = 5.5 V
|IIL|
Low-level EN input current
VDD = 5.5 V, VEN = 0 V
I(Q)
Quiescent current
MIN
MAX
UNIT
1
5
mV
50
μA
1
μA
VDD = 5.5 V, no load
1.8
2.5
VDD = 3.6 V, no load
1.5
2.3
VDD = 2.5 V, no load
1.3
2.1
0.1
2
μA
300
350
kHz
6.0
6.5
I(SD)
Shutdown current
VEN = 0.35 V, VDD = 3.6 V
RO,
Output impedance in shutdown mode
VEN = 0.35 V
f(SW)
Switching frequency
VDD = 2.5 V to 5.5 V
250
AV
Gain
VDD = 2.5 V to 5.5 V, RL = no load
5.5
REN
Resistance from EN to GND
RIN
Single ended input resistance
SD
TYP
mA
2
kΩ
dB
300
VEN ≥ VIH
150
VEN ≤ VIL
75
kΩ
kΩ
OPERATING CHARACTERISTICS
VDD = 3.6 V, TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
THD + N = 10%, f = 1 kHz, RL = 4 Ω
THD + N = 1%, f = 1 kHz, RL = 4 Ω
PO
Output power
THD + N = 10%, f = 1 kHz, RL = 8 Ω
THD + N = 1%, f = 1 kHz, RL = 8 Ω
Vn
THD+N
Noise output voltage
Total harmonic distortion plus
noise
VDD = 3.6 V, Inputs AC grounded
with CI = 2μF, f = 20 Hz to 20 kHz
MIN
TYP
VDD = 5 V
3.24
VDD = 3.6 V
1.62
VDD = 2.5 V
0.70
VDD = 5 V
2.57
VDD = 3.6 V
1.32
VDD = 2.5 V
0.57
VDD = 5 V
1.80
VDD = 3.6 V
0.91
VDD = 2.5 V
0.42
VDD = 5 V
1.46
VDD = 3.6 V
0.74
VDD = 2.5 V
0.33
A-weighting
20
No weighting
26
VDD = 5.0 V, PO = 1.0 W, f = 1 kHz, RL = 8 Ω
0.12%
VDD = 3.6 V, PO = 0.5 W, f = 1 kHz, RL = 8 Ω
0.05%
VDD = 2.5 V, PO = 0.2 W, f = 1 kHz, RL = 8 Ω
0.05%
VDD = 5.0 V, PO = 2.0 W, f = 1 kHz, RL = 4 Ω
0.32%
VDD = 3.6 V, PO = 1.0 W, f = 1 kHz, RL = 4 Ω
0.11%
VDD = 2.5 V, PO = 0.4 W, f = 1 kHz, RL = 4 Ω
0.12%
PSRR
AC power supply rejection ratio
VDD = 3.6 V, Inputs AC grounded with CI = 2 μF,
200 mVpp ripple, f = 217 Hz
CMRR
Common mode rejection ratio
VDD = 3.6 V, VIC = 1 VPP, f = 217 Hz
TSU
Startup time from shutdown
VDD = 3.6 V
4
VDD = 3.6 V, VO+ shorted to VDD
2
VDD = 3.6 V, VO– shorted to VDD
2
VDD = 3.6 V, VO+ shorted to GND
2
VDD = 3.6 V, VO– shorted to GND
2
VDD = 3.6 V, VO+ shorted to VO–
2
ISC
Short circuit protection
threshold
MAX
UNIT
W
W
W
W
μVRMS
81
dB
79
dB
ms
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OPERATING CHARACTERISTICS (continued)
VDD = 3.6 V, TA = 25°C, RL = 8 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Time for which output is
disabled after a short circuit
event, after which
auto-recovery trials are
continuously made
TAR
MIN
VDD = 2.5 V to 5.5 V
TYP
100
MAX
UNIT
ms
Terminal Functions
TERMINAL
NAME
WCSP BALL
I/O
DESCRIPTION
IN–
C1
I
Negative differential audio input.
IN+
A1
I
Positive differential audio input.
VO-
A3
O
Negative BTL audio output.
VO+
C3
O
Positive BTL audio output.
GND
A2
I
Analog ground terminal. Must be connected to same potential as PGND using a direct connection
to a single point ground.
PGND
B3
I
High-current Analog ground terminal. Must be connected to same potential as GND using a direct
connection to a single point ground.
VDD
B1
I
Power supply terminal. Must be connected to same power supply as PVDD using a direct
connection. Voltage must be within values listed in Recommended Operating Conditions table.
PVDD
B2
I
High-current Power supply terminal. Must be connected to same power supply as VDD using a
direct connection. Voltage must be within values listed in Recommended Operating Conditions
table.
EN
C2
I
Enable terminal. Connect to Logic High voltage to enable device, Logic Low voltage to disable
(shutdown).
FUNCTIONAL BLOCK DIAGRAM
EN
Input
Buffer
SC
300 KΩ
4
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SLOS648 – OCTOBER 2009
TEST SETUP FOR GRAPHS
CI
+
OUT+
IN+
Measurement
Output
+
TPA2037D1
CI
-
IN-
30 kHz
Low Pass
Filter
Load
Measurement
Input
-
OUTVDD
GND
CS1
CS2
+
VDD
-
1. CI was shorted for any common-mode input voltage measurement. All other measurements were taken with CI = 0.1-μF
(unless otherwise noted).
2. CS1 = 0.1μF is placed very close to the device. The optional CS2 = 10μF is used for datasheet graphs.
3. The 30-kHz low-pass filter is required even if the analyzer has an internal low-pass filter. An RC low-pass filter (1kΩ,
4700pF) is used on each output for the data sheet graphs.
TYPICAL CHARACTERISTICS
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
EFFICIENCY
vs OUTPUT POWER
100
100
90
90
80
80
70
70
60
50
40
RL = 8 Ω + 33 µH
30
20
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
RL = 4 Ω + 33 µH
30
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
0.4
0.8
1.2
1.6
2.0
2.4
PO − Output Power − W
PO − Output Power − W
Figure 1.
Figure 2.
POWER DISSIPATION
vs OUTPUT POWER
POWER DISSIPATION
vs OUTPUT POWER
0.5
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
0.2
0.1
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
2.8
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
VDD = 3.6 V
0.3
0.2
40
0
0.0
2.0
0.4
0.0
0.0
50
10
PD − Power Dissipation − W
PD − Power Dissipation − W
0.5
0.2
60
20
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
10
0
0.0
η − Efficiency − %
η − Efficiency − %
EFFICIENCY
vs OUTPUT POWER
3.2
3.6
4.0
VDD = 5.0 V
0.4
0.3
0.2
0.1
0.0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
PO − Output Power − W
PO − Output Power − W
Figure 3.
Figure 4.
2.8
3.2
3.6
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
SUPPLY CURRENT
vs OUTPUT POWER
SUPPLY CURRENT
vs OUTPUT POWER
900m
600m
500m
400m
300m
200m
RL = 8 Ω + 33 µH
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
400m
700m
IDD − Supply Current − A
IDD − Supply Current − A
500m
RL = 4 Ω + 33 µH
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
800m
300m
200m
100m
100m
0
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
0
0.0
4.0
0.2
0.6
1.2
Figure 6.
SUPPLY CURRENT
vs SUPPLY VOLTAGE
SUPPLY CURRENT
vs EN VOLTAGE
1.4
1.6
1.8
2.0
200
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
IDD − Supply Current − nA
1.75
1.50
1.25
1.00
2.5
3.0
3.5
4.0
4.5
5.0
150
100
50
0
0.0
5.5
0.1
0.2
VDD − Supply Voltage − V
0.3
0.4
0.5
VEN − EN Voltage − V
Figure 7.
Figure 8.
OUTPUT POWER
vs LOAD RESISTANCE
OUTPUT POWER
vs LOAD RESISTANCE
4
4
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
THD+N = 10 %
Frequency = 1 kHz
3
2
1
0
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
THD+N = 1 %
Frequency = 1 kHz
PO − Output Power − W
PO − Output Power − W
1.0
Figure 5.
RL = No Load
RL = 8 Ω + 33 µH
RL = 4 Ω + 33 µH
3
2
1
0
4
8
12
16
20
24
28
32
4
RL − Load Resistance − Ω
8
12
16
20
24
28
32
RL − Load Resistance − Ω
Figure 9.
6
0.8
PO − Output Power − W
2.00
IDD − Supply Current − mA
0.4
PO − Output Power − W
Figure 10.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
PO − Output Power − W
4
THD + NOISE
vs OUTPUT POWER
THD+N − Total Harmonic Distortion + Noise − %
OUTPUT POWER
vs SUPPLY VOLTAGE
RL = 4 Ω, THD+N = 1 %
RL = 4 Ω, THD+N = 10 %
RL = 8 Ω, THD+N = 1 %
RL = 8 Ω, THD+N = 10 %
3
2
1
Frequency = 1 kHz
3.0
3.5
4.0
4.5
5.0
10
1
0.1
0.01
10m
100m
PO − Output Power − W
Figure 11.
Figure 12.
THD + NOISE
vs OUTPUT POWER
THD + NOISE
vs FREQUENCY
100
RL = 8 Ω + 33 µH
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
10
1
0.1
0.01
10m
100m
1
1
0.1
0.01
0.001
20
100
1k
f − Frequency − Hz
Figure 14.
THD + NOISE
vs FREQUENCY
THD + NOISE
vs FREQUENCY
PO = 25 mW
PO = 125 mW
PO = 500 mW
1
0.1
0.01
0.001
100
1k
f − Frequency − Hz
10k
20k
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
Figure 13.
VDD = 3.6 V
RL = 8 Ω + 33 µH
5
PO = 50 mW
PO = 250 mW
PO = 1 W
VDD = 5.0 V
RL = 8 Ω + 33 µH
5
10
1
10
PO − Output Power − W
20
RL = 4 Ω + 33 µH
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
VDD − Supply Voltage − V
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
0
2.5
100
10k
20k
10
PO = 15 mW
PO = 75 mW
PO = 200 mW
VDD = 2.5 V
RL = 8 Ω + 33 µH
1
0.1
0.01
0.001
20
Figure 15.
100
1k
f − Frequency − Hz
10k
20k
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
PO = 100 mW
PO = 500 mW
PO = 2 W
VDD = 5.0 V
RL = 4 Ω + 33 µH
1
0.1
0.01
0.001
100
1k
f − Frequency − Hz
10k
1
0.1
0.01
0.001
100
1k
f − Frequency − Hz
10k
Figure 17.
Figure 18.
THD + NOISE
vs FREQUENCY
THD + NOISE vs
COMMON MODE INPUT VOLTAGE
PO = 30 mW
PO = 150 mW
PO = 400 mW
VDD = 2.5 V
RL = 4 Ω + 33 µH
1
0.1
0.01
0.001
100
1k
f − Frequency − Hz
10k
20k
10
RL = 8 Ω + 33 µH
Frequency = 1 kHz
PO = 200 mW
20k
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
1
0.1
0.01
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VIC − Common Mode Input Voltage − V
Figure 19.
Figure 20.
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
POWER SUPPLY REJECTION RATIO
vs FREQUENCY
−20
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−30
−40
−50
−60
−70
−80
−90
PSRR − Power Supply Rejection Ratio − dB
0
Inputs AC−Grounded
CI = 2 µF
RL = 8 Ω + 33 µH
−10
−100
Inputs AC−Grounded
CI = 2 µF
RL = 4 Ω + 33 µH
−10
−20
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
f − Frequency − Hz
10k
20k
20
Figure 21.
8
PO = 50 mW
PO = 250 mW
PO = 1 W
VDD = 3.6 V
RL = 4 Ω + 33 µH
20
0
PSRR − Power Supply Rejection Ratio − dB
10
20k
10
20
THD+N − Total Harmonic Distortion + Noise − %
10
20
THD+N − Total Harmonic Distortion + Noise − %
THD + NOISE
vs FREQUENCY
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
THD + NOISE
vs FREQUENCY
100
1k
f − Frequency − Hz
10k
20k
Figure 22.
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TYPICAL CHARACTERISTICS (continued)
VDD = 3.6 V, CI = 0.1 μF, CS1 = 0.1 μF, CS2 = 10 μF, TA = 25°C, RL = 8 Ω (unless otherwise noted)
POWER SUPPLY REJECTION RATIO
vs COMMON MODE INPUT VOLTAGE
RL = 8 Ω + 33 µH
Frequency = 217 Hz
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−20
−30
−40
−50
−60
−70
−80
−90
−100
0.0
−30
CMRR − Common Mode Rejection Ratio − dB
PSRR − Power Supply Rejection Ratio − dB
0
−10
COMMON MODE REJECTION RATIO
vs FREQUENCY
VIC = 1 VPP
RL = 8 Ω + 33 µH
−40
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−50
−60
−70
−80
−90
−100
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
20
100
1k
f − Frequency − Hz
CMRR − Common Mode Rejection Ratio − dB
VIC − Common Mode Input Voltage − V
0
−10
Figure 23.
Figure 24.
COMMON MODE REJECTION RATIO
vs COMMON MODE INPUT VOLTAGE
GSM POWER SUPPLY REJECTION
vs TIME
RL = 8 Ω + 33 µH
Frequency = 217 Hz
VDD = 2.5 V
VDD = 3.6 V
VDD = 5.0 V
−20
10k
20k
C1 - High
3.6 V
VDD
500 mV/div
C1 - Amplitude
500 mV
C1 - Duty Cycle
20%
−30
−40
VOUT
500 mV/div
−50
−60
−70
−80
−90
−100
0.0
t − Time − 2.5 ms/div
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
G026
VIC − Common Mode Input Voltage − V
Figure 25.
Figure 26.
25
0
−25
−50
−75
VO − Output Voltage − dBV
−100
0
−125
−25
−150
VDD − Supply Voltage − dBV
GSM POWER SUPPLY REJECTION
vs FREQUENCY
−50
−75
−100
−125
−150
−175
0
200
400
600
800
1k
1.2k
1.4k
1.6k
1.8k
2k
f − Frequency −Hz
G027
Figure 27.
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TPA2037D1
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APPLICATION INFORMATION
SHORT CIRCUIT AUTO-RECOVERY
When a short-circuit event occurs, the TPA2037D1 goes to shutdown mode and activates the integrated
auto-recovery process whose aim is to return the device to normal operation once the short-circuit is removed.
This process repeatedly examines (once every 100ms) whether the short-circuit condition persists, and returns
the device to normal operation immediately after the short-circuit condition is removed. This feature helps protect
the device from large currents and maintain a good long-term reliability.
INTEGRATED IMAGE REJECT FILTER FOR DAC NOISE REJECTION
In applications which use a DAC to drive Class-D amplifiers, out-of-band noise energy present at the DAC's
image frequencies fold back into the audio-band at the output of the Class-D amplifier. An external low-pass filter
is often placed between the DAC and the Class-D amplifier in order to attenuate this noise.
The TPA2037D1 has an integrated Image Reject Filter with a low-pass cutoff frequency of 130 kHz, which
significantly attenuates this noise. Depending on the system noise specification, the integrated Image Reject
Filter may help eliminate external filtering, thereby saving board space and component cost.
COMPONENT SELECTION
Figure 28 shows the TPA2037D1 typical schematic with differential inputs, while Figure 29 shows the
TPA2037D1 with differential inputs and input capacitors. Figure 30 shows the TPA2037D1 with a single-ended
input.
Decoupling Capacitors (CS1, CS2)
The TPA2037D1 is a high-performance class-D audio amplifier that requires adequate power supply decoupling
to ensure the efficiency is high and total harmonic distortion (THD) is low. For higher frequency transients,
spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor CS1 = 0.1μF ,
placed as close as possible to the device VDD lead works best. Placing CS1 close to the TPA2037D1 is important
for the efficiency of the class-D amplifier, because any resistance or inductance in the trace between the device
and the capacitor can cause a loss in efficiency. For filtering lower-frequency noise signals, a 10 μF or greater
capacitor (CS2) placed near the audio power amplifier would also help, but it is not required in most applications
because of the high PSRR of this device. Typically, the smaller the capacitor's case size, the lower the
inductance and the closer it can be placed to the TPA2037D1. X5R and X7R dielectric capacitors are
recommended for both CS1 and CS2.
Input Capacitors (CI)
The TPA2037D1 does not require input coupling capacitors if the design uses a differential source that is biased
within the common-mode input voltage range. That voltage range is listed in the Recommended Operating
Conditions table. If the input signal is not biased within the recommended common-mode input range, such as in
needing to use the input as a high pass filter, shown in Figure 29, or if using a single-ended source, shown in
Figure 30, input coupling capacitors are required. The same value capacitors should be used on both IN+ and
IN– for best pop performance. The 3-dB high-pass cutoff frequency fC of the filter formed by the input coupling
capacitor CI and the input resistance RI (typically 150 kΩ) of the TPA2037D1 is given by Equation 1:
1
fC =
(2πRICI )
(1)
The value of the input capacitor is important to consider as it directly affects the bass (low frequency)
performance of the circuit. Speaker response may also be taken into consideration when setting the corner
frequency using input capacitors. Solving for the input coupling capacitance, we get:
1
CI =
2πR
( IfC )
(2)
If the corner frequency is within the audio band, the capacitors should have a tolerance of ±10% or better,
because any mismatch in capacitance causes an impedance mismatch at the corner frequency and below.
10
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For a flat low-frequency response, use large input coupling capacitors (0.1 μF or larger). X5R and X7R dielectric
capacitors are recommended.
To Battery
Internal
Oscillator
VDD
CS
IN−
PWM
_
Differential
Input
H−
Bridge
VO−
VO+
+
IN+
GND
Bias
Circuitry
EN
TPA2037D1
Filter-Free Class D
Figure 28. Typical TPA2037D1 Application Schematic With DC-coupled Differential Input
To Battery
CI
Internal
Oscillator
CS
IN−
PWM
_
Differential
Input
VDD
CI
H−
Bridge
VO−
VO+
+
IN+
GND
EN
Bias
Circuitry
TPA2037D1
Filter-Free Class D
Figure 29. TPA2037D1 Application Schematic With Differential Input and Input Capacitors
CI
Single-ended
Input
To Battery
Internal
Oscillator
VDD
IN−
_
PWM
H−
Bridge
CS
VO−
VO+
+
IN+
CI
GND
EN
Bias
Circuitry
TPA2037D1
Filter-Free Class D
Figure 30. TPA2037D1 Application Schematic With Single-Ended Input
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EFFICIENCY AND THERMAL INFORMATION
The maximum ambient operating temperature of the TPA2037D1 depends on the load resistance, power supply
voltage and heat-sinking ability of the PCB system. The derating factor for the YFF package is shown in the
dissipation rating table. Converting this to θJA:
1
q
+
JA
Derating Factor
(3)
Given θJA (from the Package Dissipation ratings table), the maximum allowable junction temperature (from the
Absolute Maximum ratings table), and the maximum internal dissipation (from Power Dissipation vs Output
Power figures) the maximum ambient temperature can be calculated with the following equation. Note that the
units on these figures are Watts RMS. Because of crest factor (ratio of peak power to RMS power) from 9–15
dB, thermal limitations are not usually encountered.
T Max + T Max * q P
A
J
JA Dmax
(4)
The TPA2037D1 is designed with thermal protection that turns the device off when the junction temperature
surpasses 150°C to prevent damage to the IC. Note that the use of speakers less resistive than 4-Ω (typ) is not
advisable. Below 4-Ω (typ) the thermal performance of the device dramatically reduces because of increased
output current and reduced amplifier efficiency. The Absolute Maximum rating of 3.2-Ω covers the manufacturing
tolerance of a 4-Ω speaker and speaker impedance decrease due to frequency. θJA is a gross approximation of
the complex thermal transfer mechanisms between the device and its ambient environment. If the θJA calculation
reveals a potential problem, a more accurate estimate should be made.
WHEN TO USE AN OUTPUT FILTER
Design the TPA2037D1 without an Inductor / Capacitor (LC) output filter if the traces from the amplifier to the
speaker are short. Wireless handsets and PDAs are great applications for this class-D amplifier to be used
without an output filter.
The TPA2037D1 does not require an LC output filter for short speaker connections (approximately 100 mm long
or less). A ferrite bead can often be used in the design if failing radiated emissions testing without an LC filter;
and, the frequency-sensitive circuit is greater than 1 MHz. If choosing a ferrite bead, choose one with high
impedance at high frequencies, but very low impedance at low frequencies. The selection must also take into
account the currents flowing through the ferrite bead. Ferrites can begin to loose effectiveness at much lower
than rated current values. See the EVM User's Guide (SLOU266) for components used successfully by TI.
Figure 31 shows a typical ferrite-bead output filter.
Ferrite
Chip Bead
VO−
1 nF
Ferrite
Chip Bead
VO+
1 nF
Figure 31. Typical Ferrite Chip Bead Filter
12
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PRINTED CIRCUIT BOARD LAYOUT
In making the pad size for the WCSP balls, it is recommended that the layout use nonsolder mask defined
(NSMD) land. With this method, the solder mask opening is made larger than the desired land area, and the
opening size is defined by the copper pad width. Figure 32 shows the appropriate diameters for a WCSP layout.
Figure 32. Land Pattern Image and Dimensions
SOLDER PAD
DEFINITIONS
COPPER PAD
SOLDER MASK
OPENING(5)
COPPER
THICKNESS
STENCIL OPENING(6) (7)
STENCIL
THICKNESS
Nonsolder mask
defined (NSMD)
0.23 mm
0.310 mm
1 oz max
(0.032 mm)
0.275 mm x 0.275 mm Sq.
(rounded corners)
0.1 mm thick
1. Circuit traces from NSMD defined PWB lands should be 75 μm to 100 μm wide in the exposed area inside
the solder mask opening. Wider trace widths reduce device stand off and impact reliability.
2. Best reliability results are achieved when the PWB laminate glass transition temperature is above the
operating the range of the intended application.
3. Recommend solder paste is Type 3 or Type 4.
4. For a PWB using a Ni/Au surface finish, the gold thickness should be less 0.5 mm to avoid a reduction in
thermal fatigue performance.
5. Solder mask thickness should be less than 20 μm on top of the copper circuit pattern
6. Best solder stencil performance is achieved using laser cut stencils with electro polishing. Use of chemically
etched stencils give inferior solder paste volume control.
7. Trace routing away from WCSP device should be balanced in X and Y directions to avoid unintentional
component movement due to solder wetting forces.
Figure 33. Layout Snapshot
An on-pad via is not required to route the middle ball B2 (PVDD) of the TPA2037D1. Just short ball B2 (PVDD) to
ball B1 (VDD) and connect both to the supply trace as shown in Figure 33. This simplifies board routing and
saves manufacturing cost.
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PACKAGE OPTION ADDENDUM
www.ti.com
3-Nov-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPA2037D1YFFR
PREVIEW
DSBGA
YFF
9
3000
TBD
Call TI
Call TI
TPA2037D1YFFT
PREVIEW
DSBGA
YFF
9
250
TBD
Call TI
Call TI
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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