TPA6040A4
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SLOS519A – APRIL 2007 – REVISED APRIL 2007
2-W STEREO AUDIO POWER AMPLIFIER
WITH DirectPath™ STEREO HEADPHONE DRIVE AND REGULATOR
FEATURES
•
•
•
•
•
•
•
•
DESCRIPTION
Microsoft™Windows Vista™ Compliant
Fully Differential Architecture and High PSRR
Provide Excellent RF Rectification Immunity
2-W, 10% THD+N Into 4-Ω Speakers and
85-mW, 1% THD+N Into 16-Ω Headphones
From 5-V Supply
DirectPath™ Headphone Amplifier Eliminates
Output Capacitors (1)
Internal 4-Step Speaker Gain Control: 6, 10,
15.6, 21.6 dB and Fixed –1.5-V/V Headphone
4.75-V Low Dropout Regulator for CODEC
Independent Shutdown Controls for Speaker,
Headphone Amplifier, and Low Dropout
Regulator (LDO)
Output Short-Circuit and Thermal Protection
The TPA6040A4 is a stereo audio power amplifier
and DirectPath™ headphone amplifier in a thermally
enhanced, space-saving, 32-pin QFN package. The
speaker amplifier is capable of driving 2 W per
channel continuously into 4-Ω loads at 5 V. The
headphone amplifier achieves a minimum of 85 mW
at 1% THD+N from a 5-V supply. A built-in internal
4-step gain control for the speaker amplifier and a
fixed –1.5 V/V gain for the headphone amplifier
minimizes external components needed.
Independent shutdown control and dedicated inputs
for the speaker and headphone allow the
TPA6040A4
to
simultaneously
drive
both
headphones and internal speakers. Differential inputs
to the speaker amplifiers offer superior power-supply
and common-mode noise rejection.
APPLICATIONS
•
•
(1)
Notebook Computers
Portable DVD
US Patent Number 5289137
SIMPLIFIED APPLICATION CIRCUIT
TPA6040A4
CODEC
SPKR
SPKR_RIN+
HPR
SPKR_RIN–
HPL
SPKL
VDD
ROUT+
ROUT–
LOUT+
LOUT–
SPKR_LIN+
SPKR_LIN–
SPVDD
BYPASS
SPGND
GAIN0
Shutdown
Control
HP_EN
SPKR_EN
HP_INR
SGND
HP_INL
3 V – 5.5 V
GAIN1
HPVDD
CPVDD
Gain
Control
OUTL
OUTR
HPVSS
CPVSS
CPGND
VDD
4.5 V – 5.5 V
Regulator Enable
4.5 V – 5.5 V
C1P
C1N
REG_EN
REG_OUT
4.75 V (To CODEC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DirectPath, PowerPAD are trademarks of Texas Instruments.
Microsoft, Windows Vista are trademarks of Microsoft Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
TPA6040A4
www.ti.com
SLOS519A – APRIL 2007 – REVISED APRIL 2007
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Functional Block Diagram
REG_EN
BYPASS
(4.75 V Output)
REG_OUT
SPKR_EN
Bias Control
0.47 mF
LDO
HP_EN
1 mF
VDD
SPVDD
1 mF
SPKR_RIN+
1 mF
+
ROUT+
–
+
SPKR_RIN–
ROUT–
–
1 mF
GAIN0
SPGND
Gain Control
GAIN1
SPVDD
SPKR_LIN+
1 mF
SPKR_LIN–
1 mF
4.5 V – 5.5 V
+
–
–
+
LOUT+
LOUT–
SPVDD
SPGND
1 mF
HPVDD
HP_INL
–
HP_OUTL
1 mF
+
HPVSS
+
HP_INR
HP_OUTR
–
3 V – 5.5 V 1 mF
HPVDD
HPVDD
CPVDD
1 mF
Charge Pump
CPGND
C1P
GND
HPVSS
C1N
CPVSS
1 mF
1 mF
2
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SPGND
TPA6040A4
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SLOS519A – APRIL 2007 – REVISED APRIL 2007
AVAILABLE PACKAGE OPTIONS
(1)
(2)
TA
PACKAGED DEVICE (1) (2)
32-Pin QFN (RHB)
SYMBOL
–40°C to 85°C
TPA6040A4RHB
RHB
The RHB package is available taped and reeled. To order a taped and reeled part, add the suffix R to
the part number (e.g., TPA6040A4RHBR).
For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI website at www.ti.com.
VDD
REG_OUT
SGND
HP_INL
HP_INR
REG_EN
31
30
29
28
27
26
25
24
1
SPKR_RIN+
2
23
SPKR_EN
SPKR_LIN+
3
22
HP_EN
SPKR_LIN–
4
21
SPGND
SPGND
5
20
ROUT+
LOUT+
6
19
ROUT–
LOUT–
7
18
SPVDD
SPVDD
8
15
17
16
HPVDD
HP_OUTL
GAIN0
32
SPKR_RIN–
HP_OUTR
GAIN1
TPA6040A4RHB
(TOP VIEW)
10
11
12 13
14
C1P
C1N
CPVSS
HPVSS
CPVDD
9
CPGND
Thermal
Pad
BYPASS
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
I/O/P
DESCRIPTION
SPKR_RIN–
1
I
Right-channel negative differential audio input for speaker amplifier
SPKR_RIN+
2
I
Right-channel positive differential audio input for speaker amplifier
SPKR_LIN+
3
I
Left-channel positive differential audio input for speaker amplifier
SPKR_LIN–
4
I
Left-channel negative differential audio input for speaker amplifier
SPGND
5, 21
P
Speaker power ground
LOUT+
6
O
Left-channel positive audio output
LOUT–
7
O
Left-channel negative audio output
SPVDD
8, 18
P
Supply voltage terminal for speaker amplifier
Charge pump positive supply, connect to HPVDD via star connection
CPVDD
9
P
C1P
10
I/O
CPGND
11
P
C1N
12
I/O
CPVSS
13
P
Charge pump output (negative supply for headphone amplifier), connect to HPVSS
HPVSS
14
P
Headphone amplifier negative supply, connect to CPVSS
HP_OUTR
15
O
Right-channel capacitor-free headphone output
HP_OUTL
16
O
Left-channel capacitor-free headphone output
HPVDD
17
P
Headphone amplifier supply voltage, connect to CPVDD
ROUT–
19
O
Right-channel negative audio output
Charge pump flying capacitor positive terminal
Charge pump ground
Charge pump flying capacitor negative terminal
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SLOS519A – APRIL 2007 – REVISED APRIL 2007
TERMINAL FUNCTIONS (continued)
TERMINAL
I/O/P
DESCRIPTION
NAME
NO.
ROUT+
20
O
Right-channel positive audio output
HP_EN
22
I
Headphone channel enable logic input; active high enable. HIGH=ENABLE.
SPKR_EN
23
I
Speaker channel enable logic input; active low enable. LOW=ENABLE.
BYPASS
24
P
Common-mode bias voltage for speaker preamplifiers
REG_EN
25
I
Enable pin (Active HIGH) for turning on/off LDO. HIGH=ENABLE
HP_INR
26
I
Headphone right-channel audio input
HP_INL
27
I
Headphone left-channel audio input
SGND
28
P
Signal ground, connect to CPGND and SPGND
REG_OUT
29
O
Regulated 4.75-V output
VDD
30
P
Positive power supply
GAIN0
31
I
Bit 0, MSB, of gain select bits
GAIN1
32
I
Bit 1, LSB, of gain select bits
Die Pad
P
Solder the thermal pad on the bottom of the QFN package to the GND plane of the PCB. It is required for
mechanical stability and will enhance thermal performance.
Thermal Pad
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
Supply voltage
VI
Input voltage
HPVDD, VDD, SPVDD, CPVDD
VALUE
UNIT
-0.3 to 6
V
SPKR_LIN+, SPKR_LIN-, SPKR_RIN+, SPKR_RIN-,
HP_EN,GAIN0, GAIN1, SPK_EN, REG_EN
-0.3 to 6.3
HP_INL, HP_INR HP Enabled
-3.5 to 3.5
HP_INL, HP_INR HP not Enabled
-0.3 to 3.5
Continuous total power dissipation
V
See Dissipation Rating Table
TA
Operating free-air temperature range
-40 to 85
°C
TJ
Operating junction temperature range
-40 to 150
°C
Tstg
Storage temperature range
-65 to 150
°C
260
°C
8
kV
CDM
500
V
HBM
2
kV
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1)
Electrostatic discharge
HBM for HP_OUTL and HP_OUTR
Electrostatic discharge,
all other pins
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
(1)
PACKAGE (1)
TA≤ 25°C
DERATING FACTOR
TA = 70°C
TA = 85°C
RHB
5.06 W
40 mW/°C
4.04 W
3.23 W
The PowerPAD™ must be soldered to a thermal land on the printed-circuit board. Refer to the Texas Instruments document,
PowerPAD™ Thermally Enhanced Package application report (literature number SLMA002) for more information regarding the
PowerPAD™ package.
RECOMMENDED OPERATING CONDITIONS
4
Supply voltage
VDD, SPVDD
Supply voltage
HPVDD, CPVDD
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MIN
MAX
4.5
5.5
UNIT
V
3
5.5
V
TPA6040A4
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SLOS519A – APRIL 2007 – REVISED APRIL 2007
RECOMMENDED OPERATING CONDITIONS (continued)
MIN
VIH
High-level input voltage
SPKR_EN, HP_EN, GAIN0, GAIN1, REG_EN
VIL
Low-level input voltage
SPKR_EN, HP_EN, GAIN0, GAIN1, REG_EN
TA
Operating free-air temperature
MAX
2
UNIT
V
0.8
V
-40
85
°C
TYP
MAX
GENERAL DC ELECTRICAL CHARACTERISTICS
TA = 25°C, VDD = SPVDD = HPVDD = CPVDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
UNIT
IIH
High-level input current
SPKR_EN, HP_EN, GAIN0, GAIN1,
REG_EN = VDD
0.02
1
µA
IIL
Low-level input current
SPKR_EN, HP_EN, GAIN0, GAIN1,
REG_EN = 0 V
0.02
1
µA
IDD(Speaker)
Supply current, speaker amplifier
ONLY enabled
SPKR_EN = 0 V, HP_EN = REG_EN = 0 V
5
12
mA
IDD(HP)
Supply current, headphone
amplifier ONLY enabled
SPKR_EN = HP_EN = 2 V, REG_EN = 0 V
7.5
14
mA
IDD(REG)
Supply current, regulator ONLY
enabled
SPKR_EN = REG_EN = 2 V, HP_EN = 0 V
0.65
1
mA
IDD(SD)
Supply current, shutdown mode
SPKR_EN = 2 V, HP_EN = REG_EN = 0 V
2.5
5
µA
MIN
TYP
MAX
0.5
10
-60
-74
SPEAKER AMPLIFIER DC CHARACTERISTICS
TA = 25°C, VDD = SPVDD = 5 V, RL = 4 kΩ, Gain = 6 dB (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| VOO |
Output offset voltage (measured differentially)
Inputs AC-coupled to GND, Gain = 6 dB
PSRR
Power supply rejection ratio
VDD = SPVDD = 4.5 V to 5.5 V
UNIT
mV
dB
SPEAKER AMPLIFIER AC CHARACTERISTICS
TA = 25°C, VDD = SPVDD = 5 V, RL = 4 Ω, Gain = 6 dB (unless otherwise noted)
PARAMETER
PO
Output power
TEST CONDITIONS
MIN
1.25
THD+N = 10%, f = 1 kHz, RL = 8 Ω
1.5
THD+N = 1%, f = 1 kHz, RL = 4 Ω
Total harmonic distortion plus noise
Supply ripple rejection ratio
SNR
Signal-to-noise rejection ratio
Maximum output at THD+N <1%, f = 1 kHz,
Gain = 6 dB
Crosstalk (Left-Right; Right-Left)
W
0.1%
PO = 0.5 W, RL = 8 Ω, f = 20 Hz to 20 kHz
kSVR
0.08%
-60
dB
90
dB
f = 1 kHz, Po = 1 W, Gain = 6 dB
-80
dB
f = 10 kHz, Po = 1 W, Gain = 6 dB
-75
dB
30
µVrms
Vn
Noise output voltage
CBYPASS = 0.47 µF, f = 20 Hz to 20 kHz,
Gain = 6 dB, No weighting
ZI
Input Impedance
Gain = 21.6 dB
15
20
GAIN0, GAIN1 = 0.8 V
5.4
6
6.6
GAIN0 = 0.8 V; GAIN1 = 2 V
9.4
10
10.6
GAIN0 = 2 V, GAIN1 = 0.8 V
15
15.6
16.2
GAIN0, GAIN1 = 2 V
21
21.6
22.2
G
Gain
UNIT
2.3
PO = 1 W, RL = 8 Ω, f = 20 Hz to 20 kHz
f = 1 kHz, CBYPASS = 0.47 µF,
VRIPPLE = 200 mVp-p
MAX
2
THD+N = 10%, f = 1 kHz, RL = 4 Ω
THD+N
TYP
THD+N = 1%, f = 1 kHz, RL = 8 Ω
Gain Matching
Channel-to Channel
Start-up time from shutdown
CBYPASS = 0.47 µF
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kΩ
dB
0.01
dB
30
ms
5
TPA6040A4
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SLOS519A – APRIL 2007 – REVISED APRIL 2007
HEADPHONE AMPLIFIER DC ELECTRICAL CHARACTERISTICS
TA = 25°C, HPVDD = CPVDD = VDD = 5 V, RL = 16 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
| VOS |
Output offset voltage
Inputs grounded
PSRR
Power supply rejection ratio
HPVDD = 4.5 V to 5.5 V
MIN
TYP
MAX
1
3
-75
-100
MIN
TYP
UNIT
mV
dB
HEADPHONE AMPLIFIER AC CHARACTERISTICS
TA = 25°C, HPVDD = 5 V, RL = 16 Ω (unless otherwise noted)
PARAMETER
PO
THD+N
TEST CONDITIONS
Output power (outputs in phase)
Total harmonic distortion plus noise
THD+N = 10%, Rl = 16 Ω, f = 1 kHz
200
THD+N = 10%, Rl = 32 Ω, f = 1 kHz
100
PO = 85 mW, f = 20 Hz to 20 kHz,
RL = 16 Ω
0.03%
PO = 50 mW, f = 20 Hz to20 kHz,
RL = 32 Ω
0.04%
Dynamic Range with Signal Present
A-Weighted, f = 20 Hz to 20 kHz
Supply ripple rejection ratio
Crosstalk
SNR
Signal-to-noise ratio
Maximum output at THD+N 1%, f = 1 kHz
Vn
Noise output voltage
f = 20 Hz to 20 kHz, No weighting
ZI
Input Impedance
Gain
Closed-loop voltage gain
kSVR
MAX
UNIT
mW
-100
dB FS
f = 1 kHz, 200-mVpp ripple
-60
dB
Po = 35 mW, f = 20 Hz to 20 kHz
-80
dB
95
dB
20
µVrms
RL = 16 Ω
15
20
-1.45
-1.5
Start-up time from shutdown
kΩ
-1.55
5
V/V
ms
LDO CHARACTERISTICS
TA = 25°C, VDD = 5 V (unless otherwise noted)
PARAMETER
6
TEST CONDITIONS
VI
Input voltage
IO
Continuous output current
VO
Output voltage
0 < IO < 120 mA; 4.9 V < Vin < 5.5 V
Dropout voltage
IO = 120 mA
Line regulation
IL = 5 mA; 4.9 V < Vin < 5.5 V
Load regulation
IL = 0 – 120 mA, Vin = 5 V
Power supply ripple rejection
VDD = 4.9V, IL = 10 mA
MIN
VDD
TYP
4.5
MAX
5.5
120
4.65
f = 100 Hz
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UNIT
V
mA
4.75
4.85
V
60
100
mV
3
12
0.13
0.23
46
mV
mV/ mA
dB
TPA6040A4
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SLOS519A – APRIL 2007 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS
Default graph conditions: Vcc = 5 V, Freq = 1 kHz, AES17 Filter.
TOTAL HARMONIC DISTORTION + NOISE (SP)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (SP)
vs
FREQUENCY
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
Gain = 6 dB
RL = 4 Ω
VCC = 5 V
0.1
PO = 0.25 W
0.01
0.005
20
PO = 1 W
PO = 1.5 W
100
1k
Gain = 6 dB
RL = 8 Ω
VCC = 5 V
0.1
PO = 0.1 W
0.01
PO = 0.25 W
PO = 1 W
0.005
20
10k 20k
100
f − Frequency − Hz
1k
10k 20k
f − Frequency − Hz
G001
G002
Figure 1.
Figure 2.
TOTAL HARMONIC DISTORTION + NOISE (HP)
vs
FREQUENCY
TOTAL HARMONIC DISTORTION + NOISE (HP)
vs
FREQUENCY
1
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
1
Gain = 3.5 dB
RL = 16 Ω
VCC = 5 V
0.1
0.01
0.001
10
PO = 2.8 mW
PO = 100 mW
PO = 50 mW
100
1k
10k
100k
Gain = 3.5 dB
RL = 32 Ω
VCC = 5 V
0.1
PO = 50 mW
PO = 1.4 mW
PO = 25 mW
0.01
0.001
10
f − Frequency − Hz
100
1k
10k
100k
f − Frequency − Hz
G003
Figure 3.
G004
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
TOTAL HARMONIC DISTORTION + NOISE (SP)
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE (SP)
vs
OUTPUT POWER
20
Gain = 6 dB
RL = 4 Ω
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
20
VCC = 5.5 V
VCC = 5 V
1
VCC = 4.5 V
0.1
0.01
10m
100m
1
VCC = 4.5 V
0.1
100m
G005
1
Figure 5.
Figure 6.
TOTAL HARMONIC DISTORTION + NOISE (HP)
vs
OUTPUT POWER
TOTAL HARMONIC DISTORTION + NOISE (HP)
vs
OUTPUT POWER
Gain = 3.5 dB
RL = 16 Ω
VCC = 5 V
1
0.1
VCC = 5 V
In Phase
0.01
0.001
100µ
4
G006
10
THD+N − Total Harmonic Distortion + Noise − %
THD+N − Total Harmonic Distortion + Noise − %
VCC = 5 V
PO − Output Power − W
10
1m
10m
100m
PO − Output Power − W
1
Gain = 3.5 dB
RL = 32 Ω
VCC = 5 V
1
0.1
In Phase
0.01
VCC = 5 V
0.001
100µ
G007
Figure 7.
8
VCC = 5.5 V
1
0.01
10m
4
PO − Output Power − W
Gain = 6 dB
RL = 8 Ω
10
1m
10m
Figure 8.
Submit Documentation Feedback
100m
PO − Output Power − W
1
G008
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SLOS519A – APRIL 2007 – REVISED APRIL 2007
TYPICAL CHARACTERISTICS (continued)
CROSSTALK (SP)
vs
FREQUENCY
CROSSTALK (SP)
vs
FREQUENCY
0
−10
−20
−10
−20
−30
−40
−40
−50
−50
Crosstalk − dB
Crosstalk − dB
−30
0
Gain = 6 dB
PO = 1 W
RL = 4 Ω
VCC = 5 V
−60
−70
−80
L to R
−90
−60
−70
−80
−90
−100
−100
−110
−110
−120
L to R
−120
R to L
−130
−140
10
Gain = 6 dB
PO = 1 W
RL = 8 Ω
VCC = 5 V
100
1k
10k
R to L
−130
−140
10
100k
100
f − Frequency − Hz
1k
10k
G009
G010
Figure 9.
Figure 10.
CROSSTALK (LDO)
vs
FREQUENCY
CROSSTALK (HP)
vs
FREQUENCY
0
−10
−20
−30
0
Gain = 6 dB
PO = 2 W
RL = 4 Ω
VCC = 5 V
−10
−20
−30
−50
Crosstalk − dB
Crosstalk − dB
−40
−60
−70
Left SPKR to LDO
−80
−90
−40
−50
−60
−70
R to L
−90
Right SPKR to LDO
−100
−120
L to R
−110
−130
−140
10
Gain = 3.5 dB
PO = 35 mW
RL = 16 Ω
VCC = 5 V
−80
−100
−110
100k
f − Frequency − Hz
100
1k
10k
100k
−120
10
f − Frequency − Hz
100
1k
10k
100k
f − Frequency − Hz
G011
Figure 11.
G012
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
CROSSTALK (HP)
vs
FREQUENCY
OUTPUT POWER (SP)
vs
SUPPLY VOLTAGE
0
−20
Crosstalk − dB
−30
Gain = 3.5 dB
PO = 35 mW
RL = 32 Ω
VCC = 5 V
PO − Output Power − W
−10
−40
−50
−60
−70
−80
R to L
−90
−100
−110
−120
10
L to R
100
1k
10k
100k
3.2
3.1
Gain = 6 dB
RL = 4 Ω
3.0
2.9
2.8
THD+N = 10%
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
THD+N = 1%
1.9
1.8
1.7
1.6
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
f − Frequency − Hz
VCC − Supply Voltage − V
G013
Figure 13.
Figure 14.
OUTPUT POWER (SP)
vs
SUPPLY VOLTAGE
OUTPUT POWER (HP)
vs
SUPPLY VOLTAGE
2.0
1.9
0.30
Gain = 6 dB
RL = 8 Ω
THD+N = 10%
0.25
PO − Output Power − W
PO − Output Power − W
1.8
1.7
THD+N = 10%
1.6
1.5
1.4
1.3
1.2
THD+N = 1%
0.20
0.15
THD+N = 1%
0.10
0.05
Gain = 3.5 dB
RL = 16 Ω
1.1
1.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
VCC − Supply Voltage − V
0.00
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
G015
Figure 15.
10
G014
VCC − Supply Voltage − V
Figure 16.
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G016
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TYPICAL CHARACTERISTICS (continued)
SUPPLY CURRENT (SP)
vs
OUTPUT POWER
SUPPLY CURRENT (SP)
vs
OUTPUT POWER
1.6
0.8
1.2
1.0
VCC = 4.5 V
0.8
0.6
0.4
0.5
1.0
1.5
2.0
2.5
VCC = 4.5 V
0.5
0.4
0.3
PO − Output Power − W
G017
Figure 17.
Figure 18.
POWER DISSIPATION (SP)
vs
OUTPUT POWER
POWER DISSIPATION (SP)
vs
OUTPUT POWER
G018
3.2
Gain = 6 dB
RL = 4 Ω
2.8
4.5
PD − Power Dissipation − W
PD − Power Dissipation − W
0.6
0.0
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
3.0
6.0
5.0
VCC = 5.5 V
0.1
PO − Output Power − W
5.5
VCC = 5 V
0.2
0.2
0.0
0.0
Gain = 6 dB
RL = 8 Ω
0.7
VCC = 5.5 V
ICC − Supply Current − A
ICC − Supply Current − A
1.4
0.9
VCC = 5 V
Gain = 6 dB
RL = 4 Ω
4.0
3.5
VCC = 5.5 V
3.0
VCC = 5 V
2.5
VCC = 4.5 V
2.0
1.5
Gain = 6 dB
RL = 8 Ω
2.4
2.0
VCC = 5.5 V
1.6
VCC = 5 V
VCC = 4.5 V
1.2
0.8
1.0
0.4
0.5
0.0
0.0
0.5
1.0
1.5
2.0
PO − Output Power − W
2.5
3.0
0.0
0.00 0.25 0.50
G019
Figure 19.
0.75 1.00 1.25
1.50 1.75 2.00
PO − Output Power − W
G020
Figure 20.
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TYPICAL CHARACTERISTICS (continued)
SUPPLY VOLTAGE (LDO)
vs
LOAD CURRENT
5.0
5.0
4.9
4.8
4.6
4.7
4.6
IL = −10 mA
4.5
IL = −50 mA
4.4
IL = −120 mA
4.3
4.4
VDD = 5.5 V
4.2
VDD = 4.5 V
4.0
3.8
3.6
4.2
3.4
4.1
3.2
4.0
4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5
3.0
VDD − V
0
25
G021
75
100
125
150
175
200
G022
Figure 21.
Figure 22.
DROPOUT VOLTAGE (LDO)
vs
LOAD CURRENT
COMMON-MODE REJECTION RATIO (SP)
vs
FREQUENCY
0
CMRR − Common−Mode Rejection Ratio − dB
LDO Voltage = 4.65 V
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0
20
40
60
80
IL − Load Current − mA
100
120
−10
−20
Input Level = 0.2 Vpp
RL = 4 Ω
VCC = 5 V
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
10k 20k
f − Frequency − Hz
G023
Figure 23.
12
50
IL − Load Current − mA
0.10
Dropout Voltage − V
VDD = 5 V
IL = −1 mA
4.8
VCC − Supply Voltage − V
VCC − Regulator Output Voltage − V
REGULATOR OUTPUT VOLTAGE (LDO)
vs
SUPPLY VOLTAGE
G024
Figure 24.
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TYPICAL CHARACTERISTICS (continued)
COMMON-MODE REJECTION RATIO (SP)
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO (LDO)
vs
FREQUENCY
0
−10
−20
Input Level = 0.2 Vpp
RL = 8 Ω
VCC = 5 V
PSRR − Power Supply Rejection Ratio − dB
CMRR − Common−Mode Rejection Ratio − dB
0
−30
−40
−50
−60
−70
−80
−90
−100
20
100
1k
−10
IO = 10 mA
VRipple = 0.2 Vpp
−20
−30
−40
−50
−60
−70
−80
20
10k 20k
100
f − Frequency − Hz
1k
10k 20k
f − Frequency − Hz
G025
G026
Figure 25.
Figure 26.
POWER SUPPLY REJECTION RATIO (SP)
vs
FREQUENCY
POWER SUPPLY REJECTION RATIO (SP)
vs
FREQUENCY
−10
0
Gain = 6 dB
RL = 8 Ω
VCC = 5 V
PSRR − Power Supply Rejection Ratio − dB
PSRR − Power Supply Rejection Ratio − dB
0
−20
−30
−40
−50
−60
−70
−80
20
100
1k
10k 20k
−10
−20
Gain = 3.5 dB
RL = 16 Ω
VCC = 5 V
−30
−40
−50
−60
−70
−80
−90
−100
10
f − Frequency − Hz
100
1k
10k
100k
f − Frequency − Hz
G027
Figure 27.
G028
Figure 28.
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TYPICAL CHARACTERISTICS (continued)
OUTPUT POWER (HP)
vs
LOAD RESISTANCE
OUTPUT POWER (SP)
vs
LOAD RESISTANCE
500
2.8
fIN = 1 kHz
Gain = 3.5 dB
VDD = 5 V
450
2.4
400
2.2
PO − Output Power − W
PO − Output Power − mW
fIN = 1 kHz
Gain = 6 dB
VDD = 5 V
2.6
350
300
THD+N = 10%
250
200
150
THD+N = 1%
100
1.8
THD+N = 10%
1.6
1.4
THD+N = 1%
1.2
1.0
0.8
50
0
10
2.0
0.6
0.4
100
RL − Load Resistance − Ω
1k
4
6
G029
Figure 29.
14
8 10 12 14 16 18 20 22 24 26 28 30
RL − Load Resistance − Ω
Figure 30.
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APPLICATION INFORMATION
4.75 V
(Output)
4.5 V - 5.5 V
0.1 mF
2.2 mF
HP Left Input
HP Right Input
1 mF
1 mF
1 mF
{
0.47 mF
SPKR Right Input
SPKR Left Input
0.47 mF
HP_INR
SGND
HP_INL
REG_EN
SPKR_RIN–
REG_OUT
VDD
GAIN1
Regulator Enable
GAIN0
4-Step
Gain Control
SPKR_RIN+
SPKR_LIN–
ROUT+
HP_OUTL
HPVSS
SPVDD
HP_OUTR
SPVDD
CPVSS
LOUT-
CPGND
ROUT-
C1N
LOUT+
CPVDD
4.5 V - 5.5 V
SPGND
TPA6040A4
C1P
Left
Speaker
Headphone Enable
HP_EN
0.47 mF
SPGND
Speaker Enable
SPKR_EN
SPKR_LIN+
0.47 mF
0.47 mF
BYPASS
Right
Speaker
4.5 V - 5.5 V
3 V - 5.5 V
HPVDD
1 mF
3 V - 5.5 V
10 mF
1 mF
1 mF
1 mF
Headphone
Output
Figure 31. Single-Ended Input Application Circuit
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APPLICATION INFORMATION (continued)
4.75 V
(Output)
4.5 V - 5.5 V
0.1 mF
2.2 mF
HP Left Input
HP Right Input
1 mF
1 mF
1 mF
{
0.47 mF
SPKR Right (+) Input
0.47 mF
SPKR Left (+) Input
HP_INR
REG_EN
SGND
HP_INL
VDD
SPKR_RIN–
REG_OUT
SPKR Right (–) Input
GAIN0
Regulator Enable
GAIN1
SPKR_LIN–
SPGND
TPA6040A4
SPGND
ROUT+
LOUT+
Left
Speaker
SPVDD
HP_OUTR
HP_OUTL
CPVSS
HPVSS
CPGND
C1N
CPVDD
4.5 V - 5.5 V
Right
Speaker
ROUT-
LOUTSPVDD
Headphone Enable
HP_EN
0.47 mF
0.47 mF
Speaker Enable
SPKR_EN
SPKR_LIN+
SPKR Left (–) Input
0.47 mF
BYPASS
SPKR_RIN+
C1P
4-Step
Gain Control
3 V - 5.5 V
HPVDD
1 mF
10 mF
1 mF
1 mF
1 mF
Headphone
Output
Figure 32. Differential Input Application Circuit
Power Enable Modes
The TPA6040A4 allows disable of any or all of the main circuit blocks when not in use in order to reduce
operating power to an absolute minimum. The SPKR_EN control can be used to disable the speaker amplifier
while the HP_EN can be used separately to turn off the headphone amplifier. The LDO also has an independent
power control, REG_EN. With all circuit blocks disabled, the supply current in shutdown mode is only 5 µA. See
the General DC Electrical Characteristics for operating currents with each circuit block operating independently.
Speaker Amplifier Description
The speaker amplifier is capable of driving 2 W/ch of continuous RMS power into a 4-Ω load at 5 V. An internal
4-step control allows variation of the gain from 6 dB to 21.6 dB.
Fully Differential Amplifier
The TPA6040A4 speaker amplifier is a fully differential amplifier with differential inputs and outputs. The fully
differential architecture consist of a differential amplifier and a common mode amplifier. The differential amplifier
ensures that the amplifier outputs a differential voltage that is equal to the differential input times the gain. The
common-mode voltage at the output is biased around VDD/2 regardless of the common-mode voltage at the
input.
16
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APPLICATION INFORMATION (continued)
One of the primary advantages of the fully differential amplifier is improved RF immunity. GSM handsets save
power by turning on and off the RF transmitter at a rate of 217 Hz. The transmitted signal is picked up on input
and output traces. The fully differential amplifier cancels the signal and others of this type much better than
typical audio amplifiers.
Gain Setting via GAIN0 and GAIN1 Inputs
The gain of the TPA6040A4 is set by two terminals, GAIN0 and GAIN1. The gains listed in Table 1 are realized
by changing the taps on the input resistors and feedback resistors inside the amplifier. This causes the input
impedance (ZI) to vary as a function of the gain setting.
Gain Setting
GAIN1
GAIN0
AMPLIFIER GAIN
(dB)
INPUT IMPEDANCE (kΩ)
TYPICAL
TYPICAL
0
0
6
108
0
1
10
78
1
0
15.6
46
1
1
21.6
25
Input Capacitor, CI
The input capacitor allows the amplifier to bias the input signal to the proper dc level for proper operation. In this
case, the input capacitor, CI, and the input impedance of the amplifier, RI, form a high-pass filter with the corner
frequency determined in Equation 1. Figure 33 shows how the input capacitor and the input resistor within the
amplifier interact.
Figure 33. Input Resistor and Input Capacitor
(1)
The value of CI is important to consider as it directly affects the low-frequency, or bass, performance of the
circuit. Furthermore, the input impedance changes with a change in volume. The higher the volume, the lower
the input impedance is. To determine the appropriate capacitor value, reconfigure Equation 1 into Equation 2.
The value of the input resistor, RI, can be determined from Equation 2.
1
CI +
2pRI f c
(2)
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Low-leakage tantalum or ceramic capacitors are recommended. When polarized capacitors are used, the
positive side of the capacitor should face the amplifier input in most applications as the dc level there is held at
VCC/2, which is likely higher than the source dc level. Note that it is important to confirm the capacitor polarity in
each specific application. Recommended capacitor values are between 0.1 µF and 1 µF.
Windows Vista™ Premium Mode Specifications
Device Type
Requirement
Windows Premium Mobile Vista
Specifications
TPA6040A4 Typical Performance
THD+N
≤ -65 dB FS [20 Hz, 20 kHz]
-74 dB FS[20 Hz, 20 kHz]
Analog Speaker Output Jack
(RL = 8Ω, FS = 0.707 Vrms)
Dynamic Range with Signal
Present
≤ -80 dB FS A-Weight
-89 dB FS A-Weight
Analog Headphone Out Jack
(RL = 32Ω, FS = 0.300Vrms)
Line Output Crosstalk
≤ -60 dB [20 Hz, 20 kHz]
-100 dB [20 Hz, 20 kHz]
THD+N
≤ -45 dB FS [20 Hz, 20 kHz]
-81 dB FS [20 Hz, 20 kHz]
Dynamic Range with Signal
Present
≤ -80 dB FS A-Weight
-100 dB FS A-Weight
Headphone Output
Crosstalk
≤ -60 dB [20 Hz, 20 kHz]
-82 dB [20 Hz, 20 kHz]
Bridge-Tied Load Versus Single-Ended Mode
Figure 34 shows a Class-AB audio power amplifier (APA) in a bridge-tied-load (BTL) configuration. The
TPA6040A4 speaker amplifier consists of two Class-AB differential amplifiers per channel driving the positive
and negative terminals of the load. Specifically, differential drive means that as one side of the amplifier (the
positive terminal, for example) is slewing up, the other side is slewing down, and vice versa. This doubles the
voltage swing across the load as opposed to a ground-referenced load, or a single-ended load. Power is
proportional to the square of the voltage. Plugging 2x VO(PP) into the power equation yields 4X the output
power from the same supply rail and load impedance as would have been obtained with a ground-referenced
load (see Equation 3).
VO(PP)
V (RMS) +
2 Ǹ2
Power +
V (RMS)
2
RL
(3)
VDD
VO(PP)
RL
VDD
2x VO(PP)
−VO(PP)
Figure 34. Differential Output Configuration
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VDD
–3 dB
VO(PP)
CC
RL
VO(PP)
fc
Figure 35. Single-Ended Configuration and Frequency Response
Bridge-tying the outputs in a typical computer audio, LCD TV, or multimedia LCD monitor application drastically
increases output power. For example, if an amplifier in a single-ended configuration was capable of outputting a
maximum of 250 mW for a given load with a supply voltage of 12 V, then that same amplifier would be able to
output 1 W of power in a BTL configuration with the same supply voltage and load. In addition to the increase in
output power, the BTL configuration does not suffer from the same low-frequency issues that plague the
single-ended configuration. In a BTL configuration, there is no need for an output capacitor to block dc, so no
unwanted filtering occurs. In addition, the BTL configuration saves money and space, as the dc-blocking
capacitors needed for single-ended operation are large and expensive. For example, with an 8-Ω load in SE
operation, the user needs a 1000-µF capacitor to obtain a cutoff frequency below 20 Hz. This capacitor is
expensive and large.
Headphone Amplifier Description
The headphone amplifier has a fixed gain of -1.5 V/V. It uses single-ended (SE) inputs. The DirectPath™
amplifier architecture operates from a single supply but makes use of an internal charge pump to provide a
negative voltage rail. Combining the user-provided positive rail and the negative rail generated by the IC, the
device operates in what is effectively a split supply mode. The output voltages are now centered at zero volts
with the capability to swing to the positive rail or negative rail. The DirectPath™ amplifier requires no output dc
blocking capacitors and does not place any voltage on the sleeve. The block diagram and waveform of
Figure 36 illustrate the ground-referenced headphone architecture. This is the architecture of the TPA6040A4.
Single-supply headphone amplifiers typically require dc-blocking capacitors. The capacitors are required
because most headphone amplifiers have a dc bias on the outputs pin. If the dc bias is not removed, the output
signal is severely clipped, and large amounts of dc current rush through the headphones, potentially damaging
them. The left-side drawing in Figure 36 illustrates the conventional headphone amplifier connection to the
headphone jack and output signal.
DC blocking capacitors are often large in value. The headphone speakers (typical resistive values of 16 Ω or
32 Ω) combine with the dc blocking capacitors to form a high-pass filter. Equation 4 shows the relationship
between the load impedance (RL), the capacitor (CO), and the cutoff frequency (fC).
1
fc +
2pRLC O
(4)
CO can be determined using Equation 5, where the load impedance and the cutoff frequency are known.
1
CO +
2pRLf c
(5)
If fc is low, the capacitor must then have a large value because the load resistance is small. Large capacitance
values require large package sizes. Large package sizes consume PCB area, stand high above the PCB,
increase cost of assembly, and can reduce the fidelity of the audio output signal.
Two different headphone amplifier applications are available that allow for the removal of the output dc blocking
capacitors. The capacitor-less amplifier architecture is implemented in the same manner as the conventional
amplifier with the exception of the headphone jack shield pin. This amplifier provides a reference voltage, which
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is connected to the headphone jack shield pin. This is the voltage on which the audio output signals are
centered. This voltage reference is half of the amplifier power supply to allow symmetrical swing of the output
voltages. Do not connect the shield to any GND reference, or large currents will result. The scenario can happen
if, for example, an accessory other than a floating GND headphone is plugged into the headphone connector.
See the second block diagram and waveform in Figure 36.
Conventional
VDD
CO
VOUT
CO
VDD/2
GND
Capacitor-Less
VDD
VOUT
VBIAS
GND
VBIAS
DirectPathTM
VDD
GND
VSS
Figure 36. Amplifier Applications
Input-Blocking Capacitors
DC input-blocking capacitors block the dc portion of the audio source and allow the inputs to properly bias.
Maximum performance is achieved when the inputs of the TPA6040A4 are properly biased. Performance issues
such as pop are optimized with proper input capacitors.
The dc input-blocking capacitors can be removed, provided the inputs are connected differentially and within the
input common-mode range of the amplifier, the audio signal does not exceed ±3 V, and pop performance is
sufficient.
CIN is a theoretical capacitor used for mathematical calculations only. Its value is the series combination of the
dc input-blocking capacitors, C(DCINPUT-BLOCKING). Use Equation 6 to determine the value of C(DCINPUT-BLOCKING).
For example, if CIN is equal to 0.22 µF, then C(DCINPUT-BLOCKING) is equal to about 0.47 µF.
1 C
CIN =
(DCINPUT-BLOCKING)
2
(6)
The two C(DCINPUT-BLOCKING) capacitors form a high-pass filter with the input impedance of the TPA6040A4. Use
Equation 6 to calculate CIN, then calculate the cutoff frequency using CIN and the differential input impedance of
the TPA6040A4, RIN, using Equation 7. Note that the differential input impedance changes with gain. See
Figure 32 for input impedance values. The frequency and/or capacitance can be determined when one of the
two values are given.
1
1
fc IN +
or C IN + 2p fc R
2p RIN C IN
IN IN
(7)
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If a high-pass filter with a -3-dB point of no more than 20 Hz is desired over all gain settings, the minimum
impedance would be used in the Equation 7. The minimum input impedance for TPA6040A4 is 20 kΩ. The
capacitor value by Equation 7 would be 0.399 µF. However, this is CIN, and the desired value is for
C(DCINPUT-BLOCKING). Multiplying CIN by 2 yields 0.80 µF, which is close to the standard capacitor value of 1 µF.
Place 1-µF capacitors at each input terminal of the TPA6040A4 to complete the filter.
Charge Pump Flying Capacitor and CPVSS Capacitor
The charge pump flying capacitor serves to transfer charge during the generation of the negative supply voltage.
The CPVSS capacitor must be at least equal to the flying capacitor in order to allow maximum charge transfer.
Low ESR capacitors are an ideal selection, and a value of 1 µF is typical.
Decoupling Capacitors
The TPA6040A4 is a DirectPath™ headphone amplifier that requires adequate power supply decoupling to
ensure that the noise and total harmonic distortion (THD) are as low as possible. To filter high-frequency
transients, spikes, and digital hash on the power line, use good low equivalent-series-resistance (ESR) ceramic
capacitors, typically 1 µF. Find the smallest package possible, and place as close as possible to the device VDD
lead. Placing the decoupling capacitors close to the TPA6040A4 is important for the performance of the
amplifier. Use a 10 µF or greater capacitor near the TPA6040A4 to filter lower frequency noise signals; however,
the high PSRR of the TPA6040A4 makes the 10-µF capacitor unnecessary in most applications.
Midrail Bypass Capacitor, CBYPASS
The midrail bypass capacitor, C(BYPASS), has several important functions. During start-up or recovery from
shutdown mode, CBYPASS determines the rate at which the amplifier starts up. A 1-µF capacitor yields a start-up
time of approximately 30 ms. CBYPASS also reduces the noise coupled into the output signal by the power supply.
This improves the power supply ripple rejection (PSRR) of the amplifier. Ceramic or polyester capacitors with
low ESR and values in the range of 0.47 µF to 1 µF are recommended.
LOW DROPOUT REGULATOR (LDO) DESCRIPTION
The TPA6040A4 contains a 4.75-V output low dropout regulator (LDO) capable of providing a maximum of 120
mA with a drop of less than 150 mV from the 5-V supply. This can be used to power an external CODEC. A
10-µF decoupling capacitor is recommended at the output of the LDO as well as 0.1-µF capacitor to filter
high-frequency noise from the supply line.
LAYOUT RECOMMENDATIONS
Solder the exposed thermal pad (metal pad on the bottom of the part) on the TPA6040A4 QFN package to a
pad on the PCB.
It is important to keep the TPA6040A4 external components close to the body of the amplifier to limit noise
pickup. One should lay out the differential input leads symmetrical and close together to take advantage of the
inherent common mode rejection of the TPA6040A4. The layout of the TPA6040A4 evaluation module (EVM) is
a good example of component placement and the layout files are available at ti.com.
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PACKAGE OPTION ADDENDUM
www.ti.com
7-May-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPA6040A4RHBR
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
TPA6040A4RHBRG4
ACTIVE
QFN
RHB
32
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2007
TAPE AND REEL INFORMATION
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
Device
TPA6040A4RHBR
17-May-2007
Package Pins
RHB
32
Site
Reel
Diameter
(mm)
Reel
Width
(mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
MLA
330
12
5.3
5.3
1.5
8
TAPE AND REEL BOX INFORMATION
Device
Package
Pins
Site
Length (mm)
Width (mm)
Height (mm)
TPA6040A4RHBR
RHB
32
MLA
346.0
346.0
29.0
Pack Materials-Page 2
W
Pin1
(mm) Quadrant
12
PKGORN
T2TR-MS
P
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