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SLVS443 – DECEMBER 2002
FEATURES
D Two-Input, One-Output Power Multiplexer
D
D
APPLICATIONS
D
D
D
D
D
D
D
With Low rDS(on) Switches:
– 84 mΩ Typ (TPS2111)
– 120 mΩ Typ (TPS2110)
Reverse and Cross-Conduction Blocking
Wide Operating Voltage Range . . . .2.8 V to
5.5 V
Low Standby Current . . . . 0.5-µA Typ
D
D Low Operating Current . . . . 55-µA Typ
D Adjustable Current Limit
D Controlled Output Voltage Transition Times,
PCs
PDAs
Digital Cameras
Modems
Cell phones
Digital Radios
MP3 Players
PW PACKAGE
(TOP VIEW)
D0
D1
VSNS
ILIM
Limits Inrush Current and Minimizes Output
Voltage Hold-Up Capacitance
D
D
D
D
CMOS and TTL Compatible Control Inputs
Manual and Auto-Switching Operating Modes
Thermal Shutdown
Available in a TSSOP-8 Package
1
2
3
4
8
7
6
5
IN1
OUT
IN2
GND
DESCRIPTION
The TPS211x family of power multiplexers enables seamless transition between two power supplies, such as a battery and
a wall adapter, each operating at 2.8–5.5 V and delivering up to 1 A. The TPS211x family includes extensive protection
circuitry, including user-programmable current limiting, thermal protection, inrush current control, seamless supply
transition, cross-conduction blocking, and reverse-conduction blocking. These features greatly simplify designing power
multiplexer applications.
TYPICAL APPLICATION
IN1: 2.8 – 5.5 V
TPS2110/1
1
EN1
2
3
4
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
C1
0.1 µF
8
7
6
5
CL
RL
RILIM
IN2: 2.8 – 5.5 V
C2
0.1 µF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
% % &'() (& * ))& * (' +,(& -. )(-*
(&'() ( *+'(&* +) / ) * (' !* &*) &* *&-)- 0))&1.
)(-(& +)(**&2 -(* &( &**)1 &- *&2 (' +) )*.
Copyright 2002, Texas Instruments Incorporated
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SLVS443 – DECEMBER 2002
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
AVAILABLE OPTIONS
FEATURE
TPS2110
TPS2111
TPS2112
TPS2113
TPS2114
TPS2115
0.31–0.75A
0.63–1.25A
0.31–0.75A
0.63–1.25A
0.31–0.75A
0.63–1.25A
Manual
Yes
Yes
No
No
Yes
Yes
Automatic
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
TSSOP-8
Current Limit Adjustment Range
Switching modes
Switch Status Output
Package
ORDERING INFORMATION
TA
PACKAGE
–40°C
40°C to 85°C
ORDERING NUMBER(1)
MARKINGS
TPS2110PW
2110
TSSOP 8 (PW)
TSSOP-8
TPS2111PW
2111
(1) The PW package is available taped and reeled. Add an R suffix to the device type (e.g., TPS2110PWR) to indicate tape and reel.
PACKAGE DISSIPATION RATINGS
PACKAGE
TSSOP-8 (PW)
DERATING FACTOR ABOVE
TA = 25°C
3.87 mW/°C
TA ≤ 25°C
POWER RATING
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
386.84 mW
212.76 mW
154.73 mW
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
TPS2110, TPS2111
Input voltage range at pins IN1, IN2, D0, D1, VSNS, ILIM(2)
Output voltage range, VO(OUT)(2)
Continuous output current
current, IO
TPS2110
–0.3 V to 6 V
–0.3 V to 6 V
0.9 A
TPS2111
1.5 A
Continuous total power dissipation
See Dissipation Rating Table
Operating virtual junction temperature range, TJ
–40°C to 125°C
Storage temperature range, Tstg
–65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND.
RECOMMENDED OPERATING CONDITIONS
MIN
MAX UNIT
1.5
5.5
Input voltage at IN1
IN1, VI(IN1)
VI(IN2) ≥ 2.8 V
VI(IN2) < 2.8 V
2.8
5.5
VI(IN1) ≥ 2.8 V
VI(IN1) < 2.8 V
1.5
5.5
Input voltage at IN2,
IN2 VI(IN2)
2.8
5.5
Input voltage, VI(DO), VI(D1), VI(VSNS)
C
Current
t lilimitit adjustment
dj t
t range, IO(OUT)
0
5.5
TPS2110
0.31
0.75
TPS2111
0.63
1.25
–40
125
Operating virtual junction temperature, TJ
V
V
V
A
°C
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN
Human body model
CDM
2
MAX UNIT
2
kV
500
V
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SLVS443 – DECEMBER 2002
ELECTRICAL CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
TPS2110
PARAMETER
TEST CONDITIONS
MIN
TPS2111
TYP
MAX
VI(IN1) = VI(IN2) = 5.0 V
VI(IN1) = VI(IN2) = 3.3 V
120
120
VI(IN1) = VI(IN2) = 2.8 V
VI(IN1) = VI(IN2) = 5.0 V
120
MIN
TYP
MAX
140
84
110
140
84
110
140
84
110
UNIT
POWER SWITCH
rDS(on)
DS( )(1)
Drain-source
D
i
on state resistance
on-state
(INx–OUT)
TJ = 25°C,
25°C
IL = 500 mA
TJ = 125°C
125°C,
IL = 500 mA
VI(IN1) = VI(IN2) = 3.3 V
VI(IN1) = VI(IN2) = 2.8 V
220
150
220
150
220
150
mΩ
mΩ
(1) The TPS211x can switch a voltage as low as 1.5 V as long as there is a minimum of 2.8 V at one of the input power pins. In this specific case,
the lower supply voltage has no effect on the IN1 and IN2 switch on-resistances.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LOGIC INPUTS (D0 AND D1)
VIH
VIL
High-level input voltage
2
V
Low-level input voltage
Input current at D0 or D1
0.7
D0 or D1 = High, sink current
D0 or D1 = Low, source current
1
0.5
1.4
5
55
90
1
12
V
µA
SUPPLY AND LEAKAGE CURRENTS
Su ly current from IN1
Supply
(operating)
Su ly current from IN2
Supply
(operating)
Quiescent current from IN1
(STANDBY)
Quiescent current from IN2
(STANDBY)
Forward leakage current from IN1
(measured from OUT to GND)
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A
D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A
D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A
D1 = High, D0 = Low (IN1 active), VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
IO(OUT) = 0 A
D1 = High, D0 = Low (IN1 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A
D0 = D1 = Low (IN2 active), VI(IN1) = 5.5 V, VI(IN2)= 3.3 V,
IO(OUT) = 0 A
D0 = D1 = Low (IN2 active), VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
IO(OUT) = 0 A
D0 = D1 = High (inactive),
IO(OUT) = 0 A
D0 = D1 = High (inactive),
IO(OUT) = 0 A
D0 = D1 = High (inactive),
IO(OUT) = 0 A
D0 = D1 = High (inactive),
IO(OUT) = 0 A
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
µA
75
1
1
75
µA
1
12
55
90
0.5
2
µA
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
1
VI(IN1) = 5.5 V, VI(IN2) = 3.3 V,
1
VI(IN1) = 3.3 V, VI(IN2) = 5.5 V,
Forward leakage current from IN2
(measured from OUT to GND)
D0 = D1 = High (inactive), VI(IN1) = 5.5 V, IN2 open,
VO(OUT) = 0 V (shorted), TJ = 25°C
D0 =D1= High (inactive), VI(IN2) = 5.5 V, IN1 open,
VO(OUT) = 0 V (shorted), TJ = 25°C
Reverse leakage current to INx
(measured from INx to GND)
D0 = D1 = High (inactive), VI(INx) = 0 V, VO(OUT) = 5.5 V, TJ = 25°C
µA
0.5
2
0.1
5
µA
0.1
5
µA
0.3
5
µA
3
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SLVS443 – DECEMBER 2002
ELECTRICAL CHARACTERISTICS Continued
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
CURRENT LIMIT CIRCUIT
TPS2110
RILIM = 400 Ω
RILIM = 700 Ω
0.51
0.63
0.80
0.30
0.36
0.50
TPS2111
RILIM = 400 Ω
RILIM = 700 Ω
0.95
1.25
1.56
0.47
0.71
0.99
Current limit accuracy
td
Current limit settling time(1)
Time for short–circuit output current to
settle within 10% of its steady state value.
Input current at ILIM
VI(ILIM) = 0 V, IO(OUT) = 0 A
1
–15
A
ms
0
µA
(1) Not tested in production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VSNS COMPARATOR
VI(VSNS) ↑
VI(VSNS) ↓
VSNS threshold voltage
0.78
0.8
0.82
0.735
0.755
0.775
150
220
µs
1
µA
VSNS comparator hysteresis(1)
30
Deglitch of VSNS comparator (both ↑↓)(1)
90
0 V ≤ VI(VSNS) ≤ 5.5 V
Input current
60
–1
V
mV
UVLO
Falling edge
IN1 and IN2 UVLO
1.15
Rising edge
IN1 and IN2 UVLO hysteresis(1)
Falling edge
Internal VDD UVLO (the higher of IN1 and IN2)
Internal VDD UVLO hysteresis(1)
UVLO deglitch for IN1, IN2(1)
1.25
1.30
1.35
30
57
65
2.4
2.53
Rising edge
30
Falling edge
2.58
2.8
50
75
V
mV
V
mV
µs
110
(1) Not tested in production.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
80
100
120
mV
MIN
TYP
MAX
UNIT
REVERSE CONDUCTION BLOCKING
∆VO(I_block)
Minimum output-to-input voltage
difference to block switching
PARAMETER
D0 = D1 = high, VI(INx) = 3.3 V. Connect OUT to a 5 V
supply through a series 1-kΩ resistor. Let D0 = low.
Slowly decrease the supply voltage until OUT connects
to IN1.
TEST CONDITIONS
THERMAL SHUTDOWN
Thermal shutdown threshold(1)
TPS211x is in current limit.
135
Recovery from thermal shutdown(1)
Hysteresis(1)
TPS211x is in current limit.
125
°C
C
10
IN2–IN1 COMPARATORS
Hysteresis of IN2–IN1 comparator
0.1
Deglitch of IN2–IN1 comparator, (both ↑↓)(1)
(1) Not tested in production.
90
4
150
0.2
V
220
µs
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SLVS443 – DECEMBER 2002
SWITCHING CHARACTERISTICS
over recommended operating junction temperature range, VI(IN1) = VI(IN2) = 5.5 V, RILIM = 400 Ω (unless otherwise noted)
TPS2110
PARAMETER
TEST CONDITIONS
TPS2111
MIN
TYP
MAX
MIN
TYP
MAX
UNIT
POWER SWITCH
tr
Output rise time from
an enable(1)
VI(IN1) = VI(IN2) = 5 V
TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a)
0.5
1.0
1.5
1
1.8
3
ms
tf
Output fall time from
a disable(1)
VI(IN1) = VI(IN2) = 5 V
TJ = 25°C, CL = 1 µF,
IL = 500 mA,
See Figure 1(a)
0.35
0.5
0.7
0.5
1
2
ms
40
60
40
60
tt
Transition time(1)
IN1 to IN2 transition,
VI(IN1) = 3.3 V,
VI(IN2) = 5 V
IN2 to IN1 transition,
VI(IN1) = 5 V,
VI(IN2) = 3.3 V
tPLH1
Turn-on propagation
delay from enable(1)
tPHL1
Turn-off propagation
delay from a
disable(1)
tPLH2
Switch-over rising
propagation delay(1)
tPHL2
Switch-over falling
propagation delay(1)
VI(IN1) = VI(IN2) = 5 V
Measured from enable to
10% of VO(OUT)
VI(IN1) = VI(IN2) = 5 V,
Measured from disable
to 90% of VO(OUT)
Logic 1 to Logic 0
transition on D1,
VI(IN1) = 1.5 V,
VI(IN2) = 5 V,
VI(D0) = 0 V,
Measured from D1 to
10% of VO(OUT)
Logic 0 to Logic 1
transition on D1,
VI(IN1) = 1.5V,
VI(IN2) = 5V,
VI(D0) = 0 V,
Measured from D1 to
90% of VO(OUT)
TJ = 125°C, CL = 10 µF,
IL = 500 mA
[Measure transition time
as 10
10–90%
90% rise time or
from 3.4 V to 4.8 V on
VO(OUT)],
See Figure 1(b)
µs
40
60
40
60
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(a)
0.5
1
ms
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(a)
3
5
ms
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(c)
0.17
1
3
10
TJ = 25°C, CL = 10 µF,
IL = 500 mA,
See Figure 1(c)
2
2
0.17
1
ms
5
10
ms
(1) Not tested in production.
5
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SLVS443 – DECEMBER 2002
TRUTH TABLE
VI(IN2) > VI(IN1)
X
OUT(1)
YES
X
IN1
NO
NO
IN1
1
NO
YES
IN2
1
0
X
X
IN1
1
1
X
X
Hi-Z
D1
D0
0
0
VI(VSNS) > 0.8V
X
0
1
0
1
0
IN2
(1)The under-voltage lockout circuit causes the output to go Hi-Z if the
selected power supply does not exceed the IN1/IN2 UVLO, or if neither
of the supplies exceeds the internal VDD UVLO.
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
D0
1
I
D1
2
I
TTL and CMOS compatible input pins. Each pin has a 1-µA
µ pull-up. The truth table shown above illustrates the
functionality of D0 and D1.
GND
5
I
Ground
IN1
8
I
Primary power switch input. The IN1 switch can be enabled only if the IN1 supply is above the UVLO threshold and at
least one supply exceeds the internal VDD UVLO.
IN2
6
I
Secondary power switch input. The IN2 switch can be enabled only if the IN2 supply is above the UVLO threshold and
at least one supply exceeds the internal VDD UVLO.
ILIM
4
I
A resistor RILIM from ILIM to GND sets the current limit IL to 250/RILIM and 500/RILIM for the TPS2110 and TPS2111,
respectively.
OUT
7
O
Power switch output
VSNS
3
I
In the auto-switching mode (D0 = 1, D1 = 0), an internal power FET connects OUT to IN1 if the VSNS voltage is greater
than 0.8 V. Otherwise, the FET connects OUT to the higher of IN1 and IN2. The truth table shown above illustrates the
functionality of VSNS.
6
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SLVS443 – DECEMBER 2002
FUNCTIONAL BLOCK DIAGRAM
1 µA
IN1
IN2
1 µA
Internal VDD
Vf = 0 V
Vf = 0 V
IO(OUT)
Q1
8
Q2
6
7
Charge
Pump
VDD
ULVO
_
+
IN2
ULVO
Cross-Conduction
Detector
IN1
ULVO
+
_
0.6 V
+
EN2
D0
D1
VSNS
GND
1
D0
2
3
D1
5
0.8 V
+
_
VI(VSNS) >0.8 V
TPS2110: k = 0.2%
TPS2111: k = 0.1%
4
ILIM
0.5 V
+
_
Q1 is ON
UVLO (VDD)
UVLO (IN1)
k × IO(OUT)
EN1
Q2 is ON
UVLO (IN2)
OUT
VO(OUT) > VI(INx)
Control
Logic
+
_
100 mV
+
EN1
Thermal
Sense
+
_
IN2
IN1
7
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SLVS443 – DECEMBER 2002
PARAMETER MEASUREMENT INFORMATION
90%
90%
VO(OUT)
10%
10%
0V
tr
tf
tPLH1
tPHL1
DO–D1
Switch Off
Switch Enabled
Switch Off
(a)
5V
4.8 V
VO(OUT)
3.4 V
3.3 V
tt
DO–D1
Switch #2 Enabled
Switch #1 Enabled
(b)
5V
VO(OUT)
1.5 V
4.65 V
1.85 V
tPLH2
tPHL2
DO–D1
Switch #1 Enabled
Switch #2 Enabled
Switch #1 Enabled
(c)
Figure 1. Propagation Delays and Transition Timing Waveforms
8
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SLVS443 – DECEMBER 2002
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER RESPONSE
VI(DO)
2V/Div
5V
TPS2111PW
1
f = 28 Hz
78% Duty Cycle
VI(D1)
2V/Div
2
3
4
D0
D1
VSNS
ILIM
400 Ω
0.1 µF
8
IN1
7
OUT
6
IN2
5
GND
50 Ω
1
µF
3.3 V
VO(OUT)
0.1 µF
2V/Div
Output Switchover Response Test Circuit
t – Time – 1 ms/div
Figure 2
OUTPUT TURN-ON RESPONSE
VI(DO)
2V/Div
5V
TPS2111PW
f = 28 Hz
78% Duty Cycle
1
2
VI(D1)
2V/Div
3
4
400 Ω
D0
IN1
D1
OUT
VSNS
IN2
ILIM
GND
0.1 µF
8
7
6
5
1
µF
50 Ω
3.3 V
VO(OUT)
2V/Div
0.1 µF
Output Turn-On Response Test Circuit
t – Time – 2 ms/div
Figure 3
9
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SLVS443 – DECEMBER 2002
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER VOLTAGE DROOP
VI(DO)
2V/Div
5V
TPS2111PW
f = 580 Hz
90% Duty Cycle
VI(D1)
2V/Div
2
3
4
CL = 1 µF
VO(OUT)
2V/Div
1
400 Ω
D0
D1
VSNS
ILIM
8
IN1
7
OUT
6
IN2
5
GND
0.1 µF
CL
0.1 µF
CL = 0 µF
Output Switchover Voltage Droop Test Circuit
t – Time – 40 µs/div
Figure 4
10
50 Ω
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SLVS443 – DECEMBER 2002
TYPICAL CHARACTERISTICS
OUTPUT SWITCHOVER VOLTAGE DROOP
vs
LOAD CAPACITANCE
5
VI = 5 V
∆ VO(OUT) – Output Voltage Droop – V
4.5
4
3.5
RL = 10 Ω
3
2.5
2
1.5
RL = 50 Ω
1
0.5
0
0.1
VI
1
10
CL – Load Capacitance – µF
100
TPS2111PW
f = 28 Hz
50% Duty Cycle
1
2
3
4
400 Ω
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
8
0.1 µF
7
6
5
50 Ω
0.1 µF
0.1 µF
1 µF
10 µF
47 µF
10 Ω
100 µF
Output Switchover Voltage Droop Test Circuit
Figure 5
11
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SLVS443 – DECEMBER 2002
TYPICAL CHARACTERISTICS
INRUSH CURRENT
vs
LOAD CAPACITANCE
300
200
VI = 5 V
150
VI = 3.3 V
100
I
I
– Inrush Current – mA
250
50
0
0
VI
20
40
60
80
CL – Load Capacitance – µF
100
TPS2111PW
f = 28 Hz
90% Duty Cycle
1
NC
2
3
4
400 Ω
D0
D1
VSNS
ILIM
IN1
OUT
IN2
GND
8
0.1 µF
To Oscilloscope
7
6
5
50 Ω
0.1 µF
0.1 µF
1 µF
Output Capacitor Inrush Current Test Circuit
Figure 6
12
10 µF
47 µF
100 µF
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SLVS443 – DECEMBER 2002
TYPICAL CHARACTERISTICS
SWITCH ON-RESISTANCE
vs
SUPPLY VOLTAGE
SWITCH ON-RESISTANCE
vs
JUNCTION TEMPERATURE
120
rDS(on) – Switch On-Resistance – m Ω
rDS(on) – Switch On-Resistance – m Ω
180
160
TPS2110
140
120
TPS2111
100
80
60
–50
TPS2110
115
110
105
100
95
90
TPS2111
85
80
0
50
100
TJ – Junction Temperature – °C
2
150
3
4
5
VI(INx) – Supply Voltage – V
Figure 7
Figure 8
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
IN1 SUPPLY CURRENT
vs
SUPPLY VOLTAGE
0.96
60
Device Disabled
VI(IN2) = 0 V
IO(OUT) = 0 A
IN1 Switch is ON
VI(IN2) = 0 V,
IO(OUT) = 0 A
58
I(IN1) – IN1 Supply Current – µ A
0.94
0.92
0.90
0.88
0.86
I
I I(IN1) – IN1 Supply Current – µ A
6
56
54
52
50
48
46
44
0.84
42
40
0.82
2
3
4
5
VI(IN1)– IN1 Supply Voltage – V
Figure 9
6
2
3
4
5
VI(IN1) – Supply Voltage – V
6
Figure 10
13
www.ti.com
SLVS443 – DECEMBER 2002
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
SUPPLY CURRENT
vs
JUNCTION TEMPERATURE
1.2
70
VI(IN2) = 3.3 V
IO(OUT) = 0 A
I I(INx) – Supply Current – µ A
I I(INx) – Supply Current – µ A
1
80
Device Disabled
VI(IN1) = 5.5 V
II(IN1) = 5.5 V
0.8
0.6
0.4
60
IN1 Switch is ON
VI(IN1) = 5.5 V,
VI(IN2) = 3.3 V
IO(OUT) = 0 A
II(IN1)
50
40
30
20
0.2
10
II(IN2) = 3.3 V
0
–50
0
50
100
TJ – Junction Temperature – °C
Figure 11
14
150
0
–50
II(IN2)
0
50
100
TJ – Junction Temperature – °C
Figure 12
150
www.ti.com
SLVS443 – DECEMBER 2002
APPLICATION INFORMATION
Some applications have two energy sources, one of which should be used in preference to another. Figure 13
shows a circuit that will connect IN1 to OUT until the voltage at IN1 falls below a user-specified threshold. Once
the voltage on IN1 falls below this threshold, the TPS2110/1 will select the higher of the two supplies. This
usually means that the TPS2110/1 will swap to IN2.
IN1: 2.8 – 5.5 V
TPS2110/1
NC
R1
1
2
3
4
R2
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
C1
0.1 µF
8
7
6
5
RL
CL
RILIM
IN2: 2.8 – 5.5 V
C2
0.1 µF
Figure 13. Auto-Selecting for a Dual Power Supply Application
In Figure 14, the multiplexer selects between two power supplies based upon the EN1 logic signal. OUT
connects to IN1 if EN1 is logic 1, otherwise OUT connects to IN2. The logic thresholds for the D1 terminal are
compatible with both TTL and CMOS logic.
IN1: 2.8 – 5.5 V
TPS2110/1
1
EN1
2
3
4
D0
IN1
D1
OUT
VSNS
ILIM
IN2
GND
C1
0.1 µF
8
7
6
5
CL
RL
RILIM
IN2: 2.8 – 5.5 V
C2
0.1 µF
Figure 14. Manually Switching Power Sources
15
www.ti.com
SLVS443 – DECEMBER 2002
DETAILED DESCRIPTION
AUTO-SWITCHING MODE
D0 equal to logic 1 and D1 equal to logic 0 selects the auto-switching mode. In this mode, OUT connects to
IN1 if VI(VSNS) is greater than 0.8 V, otherwise OUT connects to the higher of IN1 and IN2.
The VSNS terminal includes hysteresis equal to 3.75–7.5% of the threshold selected for transition from the
primary supply to the higher of the two supplies. This hysteresis helps avoid repeated switching from one supply
to the other due to resistive drops.
MANUAL SWITCHING MODE
D0 equal to logic 0 selects the manual-switching mode. In this mode, OUT connects to IN1 if D1 is equal to logic
1, otherwise OUT connects to IN2.
N-CHANNEL MOSFETs
Two internal high-side power MOSFETs implement a single-pole double-throw (SPDT) switch. Digital logic
selects the IN1 switch, IN2 switch, or no switch (Hi-Z state). The MOSFETs have no parallel diodes so
output-to-input current cannot flow when the FET is off. An integrated comparator prevents turn-on of a FET
switch if the output voltage is greater than the input voltage.
CROSS-CONDUCTION BLOCKING
The switching circuitry ensures that both power switches will never conduct at the same time. A comparator
monitors the gate-to-source voltage of each power FET and allows a FET to turn on only if the gate-to-source
voltage of the other FET is below the turn-on threshold voltage.
REVERSE-CONDUCTION BLOCKING
When the TPS211x switches from a higher-voltage supply to a lower-voltage supply, current can potentially flow
back from the load capacitor into the lower-voltage supply. To minimize such reverse conduction, the TPS211x
will not connect a supply to the output until the output voltage has fallen to within 100 mV of the supply voltage.
Once a supply has been connected to the output, it will remain connected regardless of output voltage.
CHARGE PUMP
The higher of supplies IN1 and IN2 powers the internal charge pump. The charge pump provides power to the
current limit amplifier and allows the output FET gate voltage to be higher than the IN1 and IN2 supply voltages.
A gate voltage that is higher than the source voltage is necessary to turn on the N-channel FET.
CURRENT LIMITING
A resistor RILIM from ILIM to GND sets the current limit to 250/ RILIM and 500/RILIM for the TPS2110 and
TPS2111, respectively. Setting resistor RILIM equal to zero is not recommended as that disables current limiting.
OUTPUT VOLTAGE SLEW-RATE CONTROL
The TPS2110/1 slews the output voltage at a slow rate when OUT switches to IN1 or IN2 from the Hi-Z state
(see Truth Table). ). A slow slew rate limits the inrush current into the load capacitor. High inrush currents can
glitch the voltage bus and cause a system to hang up or reset. It can also cause reliability issues—like pit the
connector power contacts, when hot plugging a load like a PCI card. The TPS2110/1 slews the output voltage
at a much faster rate when OUT switches between IN1 and IN2. The fast rate minimizes the output voltage
droop and reduces the output voltage hold-up capacitance requirement.
16
www.ti.com
SLVS443 – DECEMBER 2002
MECHANICAL DATA
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–ā8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
17
PACKAGE OPTION ADDENDUM
www.ti.com
17-Nov-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TPS2110PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2110PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2110PWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2110PWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2111PW
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2111PWG4
ACTIVE
TSSOP
PW
8
150
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2111PWR
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TPS2111PWRG4
ACTIVE
TSSOP
PW
8
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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