TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 1.6-A, 1.25-MHz BUCK CONVERTER IN A 3 mm × 3 mm SON PACKAGE FEATURES APPLICATIONS • • • • • • • • • • • • • • • • • Input Voltage Range 4.5 VDC to 8 VDC Output Voltage (0.8 V to 90% VIN) 0 A to 1.6 A Current Capability Fixed 1.25-MHz Switching Frequency Reference 0.8 V ±1% Internal 250 mΩ N-Channel MOSFET Switch Current Mode Control with Internal Slope Compensation Internal Soft-Start Internal Loop Compensation Short Circuit Protection Thermal Shutdown High Efficiency Up to 92% Small 3 mm × 3 mm SON Package Disk Drives Set Top Box Point of Load Power ASIC Power Supplies DESCRIPTION The TPS40222 is a fixed-frequency, current-mode, non-synchronous buck converter optimized for applications powered by a 5-V distributed source. With internally determined operating frequency, soft-start time, and control loop compensation, the TPS40222 provides many features with a minimum of external components. The TPS40222 operates at 1.25 MHz and supports up to 1.6-A output loads. The output voltage can be programmed to as low as 0.8 V. The TPS40222 utilizes pulse-by-pulse current limit as well as frequency foldback to protect the converter during a catastrophic short circuited output condition. SIMPLIFIED APPLICATION DIAGRAM TYPICAL EFFICIENCY vs LOAD CURRENT VIN 100 VIN = 5 V 95 C1 6 η − Efficiency − % 90 5 4 BOOST AVIN PVIN 85 C2 TPS40222 VOUT = 3.3 V 80 FB GND SW 1 2 3 VOUT L1 75 70 D1 VOUT = 1.25 V 65 C3 R1 R2 UDG−04135 60 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ILOAD − Load Current − A Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2006, Texas Instruments Incorporated TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TJ OUTPUT VOLTAGE -40°C to 125°C Adjustable PACKAGE Plastic SON (DRP) PART NUMBER MEDIUM TPS40222DRPT Small tape and reel QTY 250 TPS40222DRPR Large tape and reel 3000 ABSOLUTE MAXIMUM RATINGS over free-air temperature range unless otherwise noted (1) TPS40222 BOOST 19 SW (50 ns maximum) VIN Input voltage range –5 SW –2 to 16 AVIN, PVIN V 10 FB -0.3 to 2 IOUT Output current source TJ Operating junction temperature range –40 to 160 Tstg Storage temperature SW 3.5 –65 to 165 Case temperature for 10 seconds per JSTD-020C (1) UNIT A °C 260 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN VIN Input voltage IOUT SW node output current TJ Operating junction temperature NOM MAX UNIT 4.5 8.0 0 1.6 V A -40 125 °C ELECTROSTATIC DISCHARGE (ESD) PROTECTION MIN MAX Human body model 2500 CDM 1500 2 UNIT V TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 ELECTRICAL CHARACTERISTICS TJ = -40°C to 125°C, 4.5 ≤ VAVIN = VPVIN≤ 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX 800 808 UNIT FEEDBACK VOLTAGE TJ = 25°C, No load 792 VFB Feedback voltage -40°C ≤ TJ≤ 125°C, No load, 4.5V ≤ VDD≤ 7 V 788 IFB Feedback input bias current VFB = 0.9 V, VAVIN = VPVIN = 5 V 812 mV 30 100 nA 550 850 µs SOFT-START tSS Soft-start time VAVIN = VPVIN = 5 V 300 Gm AMPLIFIER Transconductance (1) Gm GBW Gain bandwidth product (1) 10 µS 12 MHz OSCILLATOR fSW Switching frequency VFB > 0.7 V fSWFB Minimum foldback frequency Startup/Overcurrent, VFB = 0 V Foldback frequency slope (1) 0 V < VFB < 0.4 V VFFB Frequency foldback VFB threshold voltage (1) 1.00 75 1.25 1.50 MHz 140 kHz 2200 Hz/mV 0.4 0.6 V OVERCURRENT DETECTION ICL Overcurrent threshold tON Minimum on-time in overcurrent (1) VAVIN = VPVIN = 5 V 2.1 2.6 3.1 A 90 200 ns HIGH SIDE MOSFET AND DRIVER TJ = 25°C 250 -40°C ≤ TJ≤ 125°C 250 RDS(on) Drain-to-source on-resistance DMAX Maximum duty cycle ISWL MOSFET SW leakage current VPVIN = 10 V -10 -30 µA IBOOST Boost current ISW = 100 mA, VAVIN = VPVIN = 5 V 0.5 1.0 mA Boost diode voltage drop IDIODE ≤ 5 mA 0.9 90% 550 mΩ 97% V UNDERVOLTAGE LOCKOUT (UVLO) VON Turn-on voltage VHYST Hysteresis voltage 3.6 3.8 0.4 IQ AVIN quiescent current 1.0 4.0 1.5 V mA THERMAL SHUTDOWN (1) Thermal shutdown voltage (1) 150 Thermal hysteresis (1) -10 °C Ensured by design. Not production tested. 3 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 DRP PACKAGE (BOTTOM VIEW) BOOST 6 1 FB AVIN 5 2 GND PVIN 4 3 SW A. Exposed pad provides a low thermal resistance of θJC= 2°C/W B. Connect exposed pad to GND. Table 1. TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION AVIN 5 I Input power to the control section of the device. Closely bypass this pin to GND with a low ESR ceramic capacitor of 1-µF or greater. BOOST 6 I/O This pin provides a bootstrapped supply for the high-side MOSFET driver for PWM, enabling the gate of the high-side MOSFET to be driven above the input supply rail. Connect a 33-nF capacitor from this pin to SW pin and (optionally) a Schottky diode from this pin to the PVIN pin. FB 1 I Inverting input of the error amplifier. In closed-loop operation, the voltage at this pin is the internal reference level of 800 mV. During startup or fault conditions, the voltage on this pin also affects the operating frequency of the converter. With 0 V on the pin, the operating frequency is approximately 140 kHz.The frequency increases linearly to approximately 1.25 MHz as the voltage on the pin is raised to 0.6 V. Above 0.6 V, the operating frequency remains at approximately 1.25 MHz. GND 2 - Ground connection to the device. PVIN 4 I Input to the power section of the device. Bypass this pin to GND with a low ESR capacitor of 10-µF or greater. SW 3 I/O 4 The source connection of the internal switching MOSFET. Connect this pin to the output inductor and an external catch diode to form the converter's switch node. TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 SIMPLIFIED BLOCK DIAGRAM BOOST PVIN 6 4 TPS40222 0.5 VREF FB f(VOSC) Oscillator TSD Soft Start 0.8 VREF f(IDRAIN) DC Bias Boost Diode IDRAIN Composite Ramp E/A + + PWM Comparator FB 1 2 MΩ Thermal Shutdown S Q R Q 3 SW 16 pF f(IDRAIN) + AVIN 5 References 0.8 VREF 0.5 VREF Overcurrent Comparator Current Limit Threshold 2 GND UDG−04129 5 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 TYPICAL CHARACTERISTICS FEEDBACK VOLTAGE vs JUNCTION TEMPERATURE 803 803 802 802 VFB − Feedback Voltage − V VFB − Feedback Voltage − mV FEEDBACK VOLTAGE vs INPUT VOLTAGE (NO LOAD) 801 800 799 798 801 800 799 798 797 4 5 6 7 8 797 −50 9 −25 0 25 50 75 100 125 TJ − Junction Temperature − °C VIN − Input Voltage − V Figure 1. Figure 2. OSCILLATOR FREQUENCY vs FEEDBACK VOLTAGE OSCILLATOR FREQUENCY vs INPUT VOLTAGE 1.3 1.30 VFB = 0.8 V VIN = 5 V 1.1 f − Frequency − MHz f − Frequency − MHz 1.28 0.9 0.7 0.5 1.24 1.22 0.3 0.1 1.20 0 0.1 0.2 0.3 0.4 0.5 0.6 VFB − Feedback Voltage − V Figure 3. 6 1.26 0.7 0.8 4 5 6 7 VIN − Input Voltage − V Figure 4. 8 9 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 TYPICAL CHARACTERISTICS (continued) OVERCURRENT vs JUNCTION TEMPERATURE (VIN=5V) 2.9 2.9 2.8 2.8 ICL − Overcurrent − A ICL − Overcurrent − A OVERCURRENT vs INPUT VOLTAGE 2.7 2.6 2.6 2.5 2.5 2.4 4.5 2.7 5.0 5.5 6.0 6.5 2.4 −50 7.0 −25 0 25 50 75 100 125 100 125 TJ − Junction Temperature − °C VIN − Input Voltage − V Figure 5. Figure 6. SWITCHING MOSFET ON-RESISTANCE vs JUNCTION TEMPERATURE SOFT-START TIME vs JUNCTION TEMPERATURE 700 0.35 0.30 TSS − Soft−Start TIme − µs RDS(on) − On−Resistance − Ω 650 0.25 0.20 600 Maximum 550 500 450 0.15 −50 −25 0 25 50 75 TJ − Junction Temperature − °C Figure 7. 100 125 400 −50 Minimum −25 0 25 50 75 TJ − Junction Temperature − °C Figure 8. 7 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 DETAILED DESCRIPTION The TPS40222 is a fixed frequency PWM controller incorporating an internal high-side MOSFET switch and is intended for non-synchronous converter applications requiring load current of up to 1.6 A. Feedback Control To maintain output voltage regulation, a fixed-frequency, current-mode-control architecture is employed. A transconductance error amplifier with internal compensation senses the output voltage through a resistive divider and compares the result with an internal 0.8-V precision reference voltage. The result of this comparison is fed to the inverting input of a PWM comparator. A composite sawtooth voltage waveform is fed in to the non-inverting input resulting at a PWM signal at the comparator output. To generate the sawtooth ramp signal, the load current is sensed through the high-side MOSFET during the ON portion of the switching cycle. The sensed current is then split and fed into two trimmed resistor banks that are used to generate the ramps for the PWM control and the pulse-by-pulse current limit. This method of sensing does not require a sense resistor in the high-current path. The portion of the load current for PWM control is then summed with a signal proportional to the oscillator sawtooth, plus a small portion of DC bias to create the composite ramp signal. UVLO An internal circuit will turn on the converter when the AVIN voltage rises above approximately 3.8 V. At voltages below this level, the internal oscillator is disabled and the internal MOSFET is biased off. Reference The precision bandgap reference of 0.8 V is trimmed to 1%. Voltage Error Amplifier The internal transconductance amplifier is used to control the output voltage. A series R-C circuit (2 MΩ, 16 pF) from the output of the amplifier to ground serves as the compensation circuit for the converter. Oscillator During normal operation, the internal oscillator runs at a nominal 1.25 MHz. During startup, the oscillator starts at a slower frequency, then as the output voltage rises, the frequency is increased to the nominal operating frequency. The switch-over point occurs when the FB pin voltage exceeds 0.6 V. Above 0.6 V, the oscillator remains at a nominal 1.25 MHz. A signal derived from the oscillator ramp is used to develop slope compensation for PWM control. 8 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 DETAILED DESCRIPTION (continued) Soft-Start During power-on, the TPS40222 slowly increases the voltage to the non-inverting input to the error amplifier. In this way, the TPS40222 slowly ramps up the output voltage until the voltage on the non-inverting input to the error amplifier reaches 0.8 V. At that time, the voltage at the non-inverting input to the error amplifier remains at 0.8 V. Upon startup, the time for the voltage on the non-inverting input of the error amplifier to reach 0.8 V is approximately 550 µs. The rate of rise of the voltage on the output of a TPS40222 is determined by the resistive divider network that sets the converter output voltage. For example, the rate of rise of the internal soft-start is: V REF 0.8 V t SS 550 s (1) where • tSS in the example is the typical soft-start time of 550 µs For a 1.2-V output converter, the rate of rise observed at the output is: V OUT 1.2 V t SS 550 s (2) Output Short-Circuit Protection Current fault (short-circuit) protection is provided by sensing the current through the switching MOSFET while it is in the ON state and comparing with a preset internal level. If the current exceeds this level, the switching pulse width is limited causing the output voltage to decay. As the output voltage decays, the operating frequency is also decreased, thereby reducing power dissipation. If the fault condition persists, and the output voltage continues to decay, then a watchdog circuit discharges the internal soft-start capacitor, effectively shutting off the converter. When this interval is completed, the converter then attempts to restart. Bootstrap To drive the internal N-channel MOSFET, a bootstrap, or boost circuit, is added to provide a voltage source higher than the input voltage of sufficient energy to fully enhance the MOSFET each switching cycle. During the freewheeling portion of the switching cycle (refer to Figure 9), the internal MOSFET is off, and the voltage at the SW node is clamped to just below ground by D1. At this time the input voltage (less the drop of the internal BOOST diode) is impressed upon C2, allowing it to charge. When the internal MOSFET is commanded to turn ON, the SW node rises towards VIN, and the voltage on the BOOST pin rises to approximately 2 × VIN. This voltage is used to further turn on the internal MOSFET for the remainder of the switching cycle. 9 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 APPLICATION INFORMATION Typical Application VIN C1 6 5 4 BOOST AVIN PVIN C2 TPS40222 FB GND SW 1 2 3 L1 VOUT D1 C3 R1 R2 UDG−04131 Figure 9. Typical Application Voltage Setting The output voltage may be set by knowing that the feedback voltage is 0.8 V and using Equation 3. To determine an output voltage, choose a convenient resistor value for R2 and calculate R1. V OUT VFB 1 R1 R2 (3) Output Filter (L1 and C3) Since the loop compensation is internally fixed and cannot be changed, loop stability can only be controlled by the proper choice of output inductance and capacitance. Table 2 provides a shortcut guide to this selection and recommended capacitance to maintain a safe 50 degrees of phase margin for various inductors and output voltages. The table also shows the minimum capacitance for 50 degress of phase margin at three temperatures, with the worst case for stability at -40°C. The granularity of the table is sufficient so the user can interpolate between values to find a specific operating condition. The table values assume a full load, which is also the worst case for phase compensation. As an example of using the table, consider a 2.5-V output converter with a 2.2-µH inductor. The table shows that a minimum of 15-µF of output capacitance is required to guarantee greater than 50 degress of phase margin at the worst case temperature of -40°C. With a lead capacitor (CLEAD) added to the feedback as shown in Figure 10, this minimum capacitance increases to 26-µF and the closed-loop frequency increases by about 20%. 10 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 APPLICATION INFORMATION (continued) Table 2. Capacitor Selection (1) INDUCTOR VALUE (µH) 5-VIN RIPPLE CURRENT (mA) CMIN (µF) (PM > 50° at -40°C) fC (kHz) TJ = -40°C fC(kHz) TJ = 25°C fC(kHz) TJ = 125°C CLEAD VALUE (pF) omitted OUTPUT VOLTAGE VOUT = 3.3 V Not Recommended (2) 1.8 2.2 3.3 340 230 4.7 160 5.6 140 9 125 101 68 21 285 247 92 270 12 98 77 52 omitted 28 144 112 67 330 15 80 62 41 omitted 38 111 85 52 470 16 74 58 38 omitted 40 103 79 47 470 13 116 93 63 omitted 23 169 133 81 330 15 102 81 54 omitted 26 147 114 65 330 omitted OUTPUT VOLTAGE VOUT = 2.5 V 1.8 550 2.2 370 3.3 300 4.7 5.6 210 180 17 91 71 48 28 134 102 56 270 20 78 61 41 omitted 38 106 81 47 470 23 68 53 35 omitted 34 106 79 43 330 20 105 84 56 omitted 30 137 109 68 470 21 100 80 54 omitted 32 129 101 62 470 25 86 67 45 omitted 35 115 88 53 470 30 72 56 37 omitted 39 99 75 44 470 33 65 51 34 omitted 40 94 71 41 470 OUTPUT VOLTAGE VOUT = 1.8 V 1.8 2.2 580 470 3.3 320 4.7 220 5.6 190 OUTPUT VOLTAGE VOUT = 0.8 V (1) (2) 1.8 470 50 94 75 50 2.2 390 52 91 72 48 3.3 260 60 79 62 42 4.7 180 70 68 53 36 5.6 150 75 63 49 33 n/a See Figure 10. For VOUT > 3.3 V use an inductor with a value greater than or equal to 2.2 µH. 11 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Output Stage Component Selection In most applications, the user starts with a known output voltage and current load requirement as shown in Figure 10. PVIN SW TPS40222 4 3 5 2 AVIN VOUT 3.3 V 1.5 A L1 2.2 µH GND BOOST FB 6 R1 31.25 kΩ CLEAD C0 1 + Internal VREF 800 mV R2 10 kΩ UDG−05095 Figure 10. Output Stage As shown in Figure 10, the trimmed reference voltage is internally connected to the error amplifier. Since the input bias current to this error amplifier is negligible. The feedback resistors R1 and R2 can be selected over a broad range limited by the low bias current into the error amplifier. With this restriction in mind, R2 was selected at 10 kΩ, so its current is 80 µA and large relative to the bias current of the error amplifier. The output voltage is then given by Equation 4. V OUT 0.8 1 R1 3.3 V R2 (4) where • • R1 = 31.25 kΩ R2 = 10 kΩ Inductor Selection This device's high-frequency internal clock enables the use of smaller, less expensive inductors. Ferrite, with its good high frequency properties, is the material of choice. Several manufacturers provide catalogs with inductor saturation currents, inductance values, and LSRs (internal resistance) for their various sized ferrites. For a 3.3-V, 1.5 A application, the inductor's saturation current must be higher than the maximum output current plus ½ the ripple current. The inductor value sets the ripple current. A small inductor provides better transient response and is a smaller, less expensive part. Too low an inductor value, however, causes high ripple currents that cause high ripple voltage across the ESR of the output capacitance. A rule of thumb is to set high ripple current to be less than 30% of the output current. A first order calculation then gives: V t ON L I (5) where • • • ∆V is the input voltage -( IR drops in the inductor and FET) - VOUT ∆I is 30% of 1.5 A tON is the on time given by (VOUT /(VIN× f)) where f = 1.25 MHz Under these conditions, L = 1.55 µH Selecting a standard value 2.2-µH inductor, with an internal resistance of 32 mΩ, the peak current developed during the on time is 1.66 A. This value is safely below the device's built in overcurrent limit of 2.1 A. 12 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Capacitor Selection One constraint on the capacitance is the overshoot allowed by a sudden load change. The worst case for a transient load release occurs at the time when the inductor has just finished a tON pulse. At this point, the inductor is operating at maximum current. When the output load is suddenly removed, all of the inductor current must be absorbed by the output capacitance. With a typical output voltage overshoot requirement of 2% at 3.3-V, the minimum capacitance required to remain in specification is calculated using Equation 6. 1 L I 2 1 C V 2 V 2 O O O 2 O OS 2 (6) where • • • • VOS is the maximum overshoot voltage LO = 2.2 µH IO = 1.5 A VO = 3.3 V Solving this relationship, the minimum required output capacitance CO is 11-µF. The other load transition extreme is from no load to full load that occurs just after a minimum on-time cycle has started. At this point, the controller has to support this load for the remainder of the cycle with a minimum of current available from the inductor. In this example, the minimum on-time with a 3.3-V output is 528 ns and the off-time is 800 ns minus 528 ns = 272 ns. Using the relationship shown in Equation 7; I t C MIN O 6.1 F V OUT (7) where • • • ∆VOUT is a 2% specified output voltage droop IO = 1.5 A ∆t = 272 ns Ceramic capacitors with a low ESR are used to achieve the lowest voltage ripple. For example, current 1206, 6.3-V capacitors that provide 22 µF and an ESR of 2 mΩ are available. 13 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 These component selection decisions influence the phase margin and hence the stability of the system. For example, raising the output capacitance reduces the system crossover frequency and raises phase margin. Figure 11 illustrates this in a curve that shows phase margin as a function of output capacitance for two widely different inductors. The curves show that beyond a certain point, added capacitance has limited benefit. This point can be exploited to avoid the expense of excessive output capacitance. The curves also show the advantage of a lower inductance, where only 20-µF of output capacitance is required to obtain 60 degrees of phase margin. The output voltage affects the phase margin by changing the equivalent output resistance to deliver full load. With a higher output voltage for example, there is a higher full-load resistance and a lower output capacitance is required for the same phase margin. An idea of this effect is illustrated in Figure 12 which plots the required minimum capacitance to achieve 50 degrees of phase margin at different output voltages. The curves also show the reduction in output capacitance that may be achieved with a lower inductor value. PHASE MARGIN vs OUTPUT CAPACITANCE OUTPUT VOLTAGE vs OUTPUT CAPACITANCE 6 100 L = 1.8 µH PHASE = 50° 90 5 VOUT − Output Voltage − V Phase Margin − ° 70 60 L = 5.6 µH 50 40 30 4 L = 5.6 µH 3 2 20 1 L = 2.2 µH 10 VOUT = 1.8 V 0 0 0 20 40 60 80 100 COUT − Output Capacitance − µF Figure 11. 120 0 10 20 30 40 50 60 70 COUT − Output Capacitance − µF 80 Figure 12. A further improvement in reducing output capacitance is made by adding a lead capacitor across R1 of the feedback network. This lead capacitor can be determined by making its impedance equal to the resistance of R1 at the resonant frequency of the output L-C network. The lead capacitance is calculated using Equation 8. 1 C LEAD 2 fR R (8) The resonant frequency formed by the inductor and the output load capacitance is calculated in Equation 9. 1 fR 1 2 L CO 1 2 (9) Catch Diode (D1) The selection of the catch diode depends on the application current. Select a diode that has a low forward voltage drop, and a low junction capacitance. A diode with too high of a forward voltage drop or a diode with high junction capacitance result in a converter that has poor efficiency, as well as excessive ringing on the SW node and excessive output voltage noise. 14 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Input Filter Capacitor (C1) Select a good quality, low ESR ceramic capacitor to bypass the input. For a conservative design, the capacitor should have a ripple current rating equal to the load current of the converter. Boost Capacitor (C2) The boost capacitor is sized to ensure there is enough energy available to turn on the internal MOSFET. For most applications, use a ceramic capacitor with a value between 33 nF and 100 nF. D2 VIN C1 6 5 4 BOOST AVIN PVIN C2 TPS40222 FB GND SW 1 2 3 L1 VOUT D1 C3 R1 R2 UDG−04132 Figure 13. Using a Boost Diode Boost Diode (D2) For some applications, the internal bootstrap diode’s voltage drop may be too high to sufficiently charge the boost capacitor each switching cycle. For these applications, a Schottky diode, D2 shown in Figure 13, may be added. Output Preload Requirement One of the requirements for proper startup of the DC-to-DC converter is that the boost capacitor, C2, has sufficient voltage across it before switching occurs. In some applications, notably those with output voltages of 3.3 V, and those with slowly rising or low input voltages, there is the need to add a small 10 mA, pre-load to the converter to hold the SW node to GND before switching begins. Without a pre-load, the output voltage may not reach regulation. In addition, the pre-load prevents the output from overshooting too much when the load is stepped from a high value to zero. AVIN Filtering Some applications may require the addition of an R-C filter on the input of AVIN to filter unwanted noise and improve load regulation. (See Figure 14) Use R4=10 Ω and C5=1 µF. Connect the ground side of C5 as close as possible to the GND pin of the device. SW Node Snubber To attenuate excessive ringing at the SW node, an R-C network may be added across D1. (See Figure 14) Use R3=10 Ω and C4=680 pF as a starting point. Decrease C4 until the minimum capacitance is found for the desired ringing attenuation. 15 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 VIN R4 C1 C5 6 5 4 BOOST AVIN PVIN C2 TPS40222 FB GND SW 1 2 3 L1 VOUT R3 C4 D1 C3 R1 R2 UDG−04130 Figure 14. AVIN Filter and SW Node Snubber 16 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Application Circuit Schematic Figure 15 shows an example of an application incorporating a TPS40222 in a 1.2-V output DC-to-DC converter. Notice the use of parallel capacitors at the input and the output to reduce the effective ESR of the capacitance. +VIN 4.5 V to 5.5 V TP1 1 C1A 22 µF J1 C1B 22 µF C1C 0.1 µF R4 2 GND TP2 C5 1 µF 6 5 4 BOOST AVIN PVIN TPS40222 FB GND SW 1 2 3 C2 33 nF TP3 L1 3.3 µH 1 2 R3 D1 C3A 22 µF C4 C3B 22 µF R1 5.6 kΩ +VOUT 1 1.2 V R5 J2 2 GND R2 10 kΩ TP4 UDG−05099 Figure 15. 5-VIN, 1.2 VOUT DC-to-DC Converter 17 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 Table 3. List of Materials REFERENCE DESIGNATOR QTY VENDOR PART NUMBER DESCRIPTION VENDOR NOTES C1A, C1B 2 Capacitor, 22 µF ceramic, 1206 Input bypass C1D 1 Capacitor, 0.1 µF ceramic, 0805 High-frequency bypass, mount near VCC C2 1 Capacitor, 33 nF ceramic, 0805 Bootstrap C3A, C3B 2 Capacitor, 22 µF ceramic, 1206 Output capacitors C4 1 Capacitor, 680 pF ceramic, 0805 Snubber (optional - open if not used) C5 1 Capacitor, 1 µF ceramic, 0805 Device input voltage filter capacitor D1 1 Diode, Schottky, 1 A RSX501L-20 ROHM L1 1 Inductor, 3.3 µH ELL6PV3R3N Panasonic R1 1 Resistor, 5620 Ω, 1%, SMD, 0603 Voltage setting resistor R2 1 Resistor, 10 kΩ, 1%, SMD, 0603 Voltage setting resistor R3 1 Resistor, 10 Ω, 10%, SMD, 0805 Snubber (optional - open if not used) R4 1 Resistor, 10 Ω, 10%, SMD, 0603 Device input voltage filter (optional - short if not used) R5 1 Resistor, 120 Ω, 10%, SMD, 0805 Output pre-load (optional - open if not used) U1 1 PWM converter device Catch diode Filter inductor Texas Instruments TPS40222 APPLICATION CURVES OUTPUT VOLTAGE vs INPUT VOLTAGE AT LOAD CURRENT EFFICIENCY vs LOAD CURRENT 100 1.410 VIN = 5 V IOUT = 1.0 A 95 1.408 90 η − Efficiency − % VOUT − Output Voltage − V IOUT = 1.5 A 1.406 IOUT = 0.5 A 1.404 85 VOUT = 3.3 V 80 75 70 VOUT = 1.25 V 1.402 65 No Load 1.400 4.0 60 4.5 5.0 5.5 6.0 VIN − Input Voltage − V Figure 16. 18 6.5 7.0 0 0.2 0.4 0.6 0.8 1.0 1.2 ILOAD − Load Current − A Figure 17. 1.4 1.6 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 TYPICAL CHARACTERISTICS SW 2 V/ div VOUT (0.5 V/ div) VIN (1 V/ div) t − Time − 200 µs/div t − Time − 100 ns/div Figure 18. Startup Waveform Figure 19. SW Node Waveform GAIN AND PHASE vs FREQUENCY 180 50 135 40 30 90 20 45 0 10 GAIN 0 −45 −10 −90 −20 −135 −30 100 1k 10 k 100 k Phase − ° Gain − dB PHASE −180 1M f − Frequency − Hz Figure 20. 19 TPS40222 www.ti.com SLUS642A – OCTOBER 2005 – REVISED JANUARY 2006 PC BOARD LAYOUT RECOMMENDATIONS Device Pad Design The 6-pin package has an exposed thermal pad intended to help conduct heat out of the package, allowing a higher than otherwise available operating ambient temperature. Place three vias within the pad area, tying them to an analog ground plane. PCB Layout When designing a DC-to-DC converter layout, care must be taken to ensure a noise-free design. VIN C1 6 5 BOOST AVIN 4 PVIN C2 TPS40222 FB GND SW 1 2 3 L1 VOUT B D1 A C3 R1 R2 UDG−04134 Figure 21. Ensuring a Noise-Free Layout • • • • • • • 20 AC current loops must be kept as short as possible. The input loop B (C1-U1-D1) in the figure must be kept short to ensure proper filtering by C1 for the device. Excessive high frequency noise on AVIN during switching could degrade overall regulation as the load increases. In order to reduce noise spikes seen by the device, an R-C filter is recommended (see AVIN Filtering in the APPLICATION INFORMATION section) and a snubber may be added (see SW Node Snubber in the APPLICATION INFORMATION section). The output loop A (D1-L1-C3) should also be kept as small as possible. Noise performance at the output of the converter suffers if the loop area is too large. It is recommended that traces carrying large AC currents NOT be connected through a ground plane. Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise shield. Split the ground plane as necessary to keep noise away from the TPS40222 and noise sensitive areas (R1, R2). Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated emissions For good output voltage regulation, R1 should be connected close to the load. The R2-TPS40222 (GND) connection should be tied close to the load as well. The trace from the R1-R2 junction to the TPS40222 should be kept away from any noise source, such as the SW node, or the boost circuitry. The GND pin and the thermal pad of the TPS40222 should be connected together under the device as indicated in the pad design section. For good thermal conductivity, VIAs directly under the device should connect the thermal pad to a ground plane on the other side of the board. PACKAGE OPTION ADDENDUM www.ti.com 27-Feb-2006 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TPS40222DRPR ACTIVE SON DRP 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40222DRPRG4 ACTIVE SON DRP 6 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40222DRPT ACTIVE SON DRP 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS40222DRPTG4 ACTIVE SON DRP 6 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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