TI TPS62060DSGR

TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
3-MHz 1.6A Step Down Converter in 2x2 SON Package
Check for Samples: TPS62061, TPS62063, TPS62060
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
2
3 MHz Switching Frequency
VIN Range from 2.7V to 6V
1.6A Output Current
Up to 97% Efficiency
Power Save Mode / 3 MHz Fixed-PWM Mode
Output Voltage Accuracy in PWM Mode ±1.5%
Output Discharge Function
Typical 18 µA Quiescent Current
100% Duty Cycle for Lowest Dropout
Voltage Positioning
Clock Dithering
Supports Maximum 1mm Height Solutions
Available in a 2x2x0.75mm SON
DESCRIPTION
The TPS62060 is a highly efficient synchronous
step-down DC-DC converter and provides up to 1.6A
output current.
With an input voltage range of 2.7V to 6V the device
is a perfect fit for power conversion from a single
Li-Ion battery as well from 5V or 3.3V system supply
rails. The TPS62060 operates at 3-MHz fixed
frequency and enters Power Save Mode operation at
light load currents to maintain high efficiency over the
entire load current range. The Power Save Mode is
optimized for low output voltage ripple. For low noise
applications, the device can be forced into fixed
frequency PWM mode by pulling the MODE pin high.
APPLICATIONS
In the shutdown mode, the current consumption is
reduced to less than 1µA and an internal circuit
discharges the output capacitor.
•
•
•
•
TPS62060 is optimized for operation with a tiny
1.0µH inductor and a small 10µF output capacitor to
achieve smallest solution size and high regulation
performance.
POL
Notebooks, Pocket PCs
Portable Media Players
DSP Supply
The TPS62060 is available in a small 2x2x0.75mm
8-pin SON package.
vertical spacer
vertical spacer
100
TYPICAL APPLICATION CIRCUIT
VIN = 3.7 V
95
90
VIN = 2.7 V to 6 V
PVIN
L
1.0 mH
SW
AVIN
CIN
10 mF
R1
360 kW
EN
MODE
AGND
PGND
VOUT = 1.8 V
up to 1.6 A
FB
R2
180 kW
Cff
22 pF
COUT
10 mF
VIN = 4.2 V
VIN = 5 V
85
Efficiency - %
TPS62060
80
75
70
65
L = 1.2 mH (NRG4026T 1R2),
COUT = 22 mF (0603 size),
VOUT = 3.3 V,
Mode: Auto PFM/PWM
60
55
50
0
0.2
0.4
0.8
0.6
1
1.2
IL - Load Current - A
1.4
1.6
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
TA
–40°C to
85°C
OUTPUT
VOLTAGE (2)
MODE
Power Good
PG
MAXIMUM
OUTPUT
CURRENT
TPS62060
Adjustable
Selectable
No
1.6 A
TPS62061
1.8V fix
Selectable
No
1.6 A
TPS62063
3.3V fix
Selectable
No
1.6 A
Adjustable
no
yes
1.6A
TPS6206x
(1)
(2)
FUNCTION
PART
NUMBER
(2)
PACKAGE
DESIGNATOR
PACKAGE
MARKING
CGY
CGX
DSG
QXD
-
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Contact TI for fixed output voltage options / Power Good output options
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
MIN
Voltage Range
(2)
Current (source)
AVIN, PVIN
–0.3
7
EN, MODE, FB
–0.3
VIN +0.3 < 7
SW
–0.3
7
Peak output
Internally limited
Electrostatic Discharge (HBM) QSS 009-105 (JESD22-A114A)
(3)
(1)
(2)
(3)
kV
1
Electrostatic Discharge (Machine model)
V
A
2
Electrostatic Discharge (CDM) QSS 009-147 (JESD22-C101B.01)
Temperature
MAX
200
V
TJ
–40
125
°C
Tstg
–65
150
°C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
The human body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin. The machine model is a 200-pF
capacitor discharged directly into each pin.
DISSIPATION RATINGS (1) (2)
(1)
(2)
2
PACKAGE
RθJA
POWER RATING
TA = ≤ 25°C
DERATING FACTOR
ABOVE TA = 25°C
DSG
75°C/W
1300 mW
13 mW/°C
Maximum power dissipation is a function of TJ(max), θJA and TA. The maximum allowable power dissipation at any allowable ambient
temperature is PD = (TJ(max) – TA)/ θJA.
This thermal data measured with high-K board (4 layers according to JESD51-7 JEDEC Standard.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
RECOMMENDED OPERATING CONDITIONS
MIN
AVIN ,
PVIN
Supply voltage
NOM
MAX
2.7
6
Output current capability
1600
UNIT
V
mA
Output voltage range for adjustable voltage
0.8
VIN
V
L
Effective Inductance Range
0.7
1.0
1.6
µH
COUT
Effective Output Capacitance Range
4.5
10
22
µF
–40
85
°C
–40
125
°C
TA
Operating ambient temperature
TJ
Operating junction temperature
(1)
(1)
In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the
part/package in the application (θJA), as given by the following equation: TA(max)= TJ(max)–(θJA X PD(max))
ELECTRICAL CHARACTERISTICS
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6V. External components CIN = 10μF 0603, COUT = 10μF 0603, L = 1.0μH, see the parameter
measurement information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY
VIN
Input voltage range
2.7
IQ
Operating quiescent current
IOUT = 0 mA, device operating in PFM mode
and not device not switching
ISD
Shutdown current
EN = GND, current into AVIN and PVIN
VUVLO
Undervoltage lockout threshold
6
V
18
25
μA
0.1
1
μA
Falling
1.73
1.78
1.83
Rising
1.9
1.95
1.99
V
ENABLE, MODE
VIH
High level input voltage
2.7 V ≤ VIN ≤ 6 V
1.0
6
VIL
Low level input voltage
2.7 V ≤ VIN ≤ 6 V
0
0.4
V
IIN
Input bias current
Pin tied to GND or VIN
0.01
1
μA
V
POWER SWITCH
VIN = 3.6 V
(1)
120
180
(1)
95
150
VIN = 3.6 V (1)
90
130
(1)
75
100
2250
2700
RDS(on)
High-side MOSFET on-resistance
RDS(on)
Low-side MOSFET on-resistance
ILIMF
Forward current limit MOSFET
high-side and low-side
2.7V ≤ VIN ≤ 6 V
Thermal shutdown
Increasing junction temperature
150
Thermal shutdown hysteresis
Decreasing junction temperature
10
TSD
VIN = 5.0 V
VIN = 5.0 V
1800
mΩ
mΩ
mA
°C
OSCILLATOR
fSW
(1)
Oscillator frequency
2.7 V ≤ VIN ≤ 6 V
2.6
3
3.4
MHz
Maximum value applies for TJ = 85°C
Copyright © 2010–2011, Texas Instruments Incorporated
3
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over full operating ambient temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply
for condition VIN = EN = 3.6V. External components CIN = 10μF 0603, COUT = 10μF 0603, L = 1.0μH, see the parameter
measurement information.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
Vref
Reference voltage
VFB(PWM)
Feedback voltage PWM Mode
VFB(PFM)
600
Feedback voltage PFM mode,
Voltage Positioning
PWM operation, MODE = VIN ,
2.7 V ≤ VIN ≤ 6 V, 0 mA load
–1.5%
device in PFM mode, voltage positioning active
1%
-0.5
Line regulation
%/A
0
R(Discharge)
Internal discharge resistor
Activated with EN = GND, 2.0V ≤ VIN≤ 6V, 0.8 ≤
VOUT≤ 3.6V
tSTART
Start-up time
Time from active EN to reach 95% of VOUT
(2)
1.5%
(2)
Load regulation
VFB
0%
mV
75
200
%/V
1450
500
Ω
μs
In PFM mode, the internal reference voltage is set to typ. 1.01×Vref. See the parameter measurement information.
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL
NO.
SON 2x2-8
I/O
PGND
1
PWR
GND supply pin for the output stage.
SW
2
OUT
This is the switch pin and is connected to the internal MOSFET switches. Connect the
external inductor between this terminal and the output capacitor.
AGND
3
IN
Analog GND supply pin for the control circuit.
FB
4
IN
Feedback pin for the internal regulation loop. Connect the external resistor divider to this pin.
In case of fixed output voltage option, connect this pin directly to the output capacitor
EN
5
IN
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown
mode. Pulling this pin to high enables the device. This pin must be terminated
MODE
6
IN
MODE: MODE pin = high forces the device to operate in fixed frequency PWM mode. MODE
pin = low enables the Power Save Mode with automatic transition from PFM mode to fixed
frequency PWM mode.
AVIN
7
IN
Analog VIN power supply for the control circuit. Need to be connected to PVIN and input
capacitor.
PVIN
8
PWR
NAME
Power PAD
4
DESCRIPTION
VIN power supply pin for the output stage.
For good thermal performance, this PAD must be soldered to the land pattern on the pcb.
This PAD should be used as device GND.
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
AVIN
PVIN
Current
Limit Comparator
Undervoltage
Lockout 1.8V
Thermal
Shutdown
Limit
High Side
PFM Comparator
Reference
0.6V VREF
FB
VREF
Softstart
VOUT RAMP
CONTROL
Gate Driver
Anti
Shoot-Through
Control
Stage
Error Amp.
VREF
SW
Integrator
FB
Internal
FB
Network*
MODE *
MODE/
PG
PWM
Comp.
Zero-Pole
AMP.
Limit
Low Side
Sawtooth
Generator
3MHz
Clock
PG
Current
Limit Comparator
FB
VREF
RDischarge
PG Comparator*
EN
AGND
PGND
* Function depends on device option
Vertical spacer
Vertical spacer
PARAMETER MEASUREMENT INFORMATION
VIN = 2.7 V to 6 V
TPS62060
PVIN
CIN
10 µF
L
1.0 µH/1.2 µH
SW
AVIN
EN
MODE/PG FB
AGND
PGND
R1
VOUT
up to 1.6 A
COUT
Cff
22 pF 10 µF
R2
L: LQH44PN1R0NP0, L = 1.0 mH,Murata,
NRG4026T1R2, L = 1.2 mH, Taiyo Yuden
CIN / COUT: GRM188R60J106U, Murata 0603 size
Copyright © 2010–2011, Texas Instruments Incorporated
5
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
TYPICAL CHARACTERISTICS
Table 1. Table of Graphs
FIGURE
η
Efficiency
Output Voltage Accuracy
Load Current, VOUT = 1.2 V, Auto PF//PWM Mode, Linear Scale
Figure 1
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode, Linear Scale
Figure 2
Load Current, VOUT = 3.3 V, PFM/PWM Mode, Linear Scale
Figure 3
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode vs. Forced PWM
Mode, Logarithmic Scale
Figure 4
Load Current, VOUT = 1.8 V, Auto PFM/PWM Mode
Figure 5
Load Current, VOUT = 1.8 V, Forced PWM Mode
Figure 6
Shutdown Current
Input Voltage and Ambient Temperature
Figure 7
Quiescent Current
Input Voltage
Figure 8
Oscillator Frequency
Input Voltage
Figure 9
Static Drain-Source On-State
Resistance
Input Voltage, Low-Side Switch
Figure 10
Input Voltage, High-Side Switch
Figure 11
RDISCHARGE
Input Voltage vs. VOUT
Figure 12
PWM Mode, VIN = 3.6 V, VOUT = 1.8 V, 500 mA, L = 1.2 μH, COUT = 10μF
Figure 13
PFM Mode, VIN = 3.6 V, VOUT = 1.8 V, 20 mA, L = 1.2 μH, COUT = 10μF
Figure 14
PWM Mode, VIN = 3.6 V, VOUT = 1.2 V, 0.2 mA to 1 A
Figure 15
PFM Mode, VIN = 3.6 V, VOUT = 1.2 V, 20 mA to 250 mA
Figure 16
VIN = 3.6 V, VOUT = 1.8 V, 200 mA to 1500 mA
Figure 17
PWM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
Figure 18
Typical Operation
Load Transient
Line Transient
PFM Mode, VIN = 3.6 V to 4.2 V, VOUT = 1.8 V, 500 mA
Figure 19
Startup into Load
VIN = 3.6 V, VOUT = 1.8 V, Load = 2.2-Ω
Figure 20
Output Discharge
VIN = 3.6 V, VOUT = 1.8 V, No Load
Figure 21
EFFICIENCY
vs
LOAD CURRENT
EFFICIENCY
vs
LOAD CURRENT
100
100
95
95
VIN = 5 V
90
VIN = 4.2 V
80
85
Efficiency - %
85
Efficiency - %
90
VIN = 5 V
VIN = 3 V
VIN = 3.3 V
VIN = 3.6 V
75
70
65
L = 1.2 mH (NRG4026T 1R2),
COUT = 10 mF (0603 size),
VOUT = 1.2 V,
Mode: Auto PFM/PWM
55
0.2
0.4
0.6
0.8
1
1.2
IL - Load Current - A
1.4
Figure 1. VOUT = 1.2V, Auto PFM/PWM Mode,
Linear Scale
6
VIN = 3.3 V
VIN = 3.6 V
75
70
65
60
50
0
VIN = 3 V
80
VIN = 4.2 V
L = 1.2 mH (NRG4026T 1R2),
COUT = 10 mF (0603 size),
VOUT = 1.8 V,
Mode: Auto PFM/PWM
60
55
1.6
50
0
0.2
0.4
0.6
0.8
1
1.2
IL - Load Current - A
1.4
1.6
Figure 2. VOUT = 1.8V, Auto PFM/PWM Mode,
Linear Scale
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
EFFICIENCY
vs
LOAD CURRENT
100
EFFICIENCY
vs
LOAD CURRENT
100
VIN = 3.7 V
Auto PFM/PWM Mode
95
90
90
VIN = 4.2 V
80
VIN = 5 V
70
Efficiency - %
Efficiency - %
85
80
75
70
L = 1.2 mH (NRG4026T 1R2),
COUT = 22 mF (0603 size),
VOUT = 3.3 V,
Mode: Auto PFM/PWM
60
55
50
40
0
0.2
0.4
0.6
0.8
1
1.2
IL - Load Current - A
1.4
20
0
0.001
1.6
0.01
0.1
IL - Load Current - A
1
10
Figure 3. VOUT = 3.3V, Auto PFM/PWM Mode,
Linear Scale
Figure 4. Auto PFM/PWM Mode vs. Forced PWM Mode,
Logarithmic Scale
OUTPUT VOLTAGE ACCURACY
vs
LOAD CURRENT
OUTPUT VOLTAGE ACCURACY
vs
LOAD CURRENT
1.890
1.890
1.872
1.872
1.854 Voltage Positioning PFM Mode
1.854
1.836
1.818
VIN = 3.3 V
1.800
PWM Mode
VIN = 3.6 V
VIN = 4.2 V
1.782
1.764
L = 1.2 mH (NRG4026T 1R2),
COUT = 10 mF (0603 size),
VOUT = 1.8 V
10
VO - Output Voltage DC - V
VO - Output Voltage DC - V
Forced PWM Mode
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
60
30
65
50
VIN = 3.3 V
VIN = 3.6 V
VIN = 4.2 V
VIN = 5 V
VIN = 5 V
L = 1 mH,
COUT = 10 mF,
VOUT = 1.8 V,
Mode: Auto PFM/PWM
1.746
1.728
1.710
0.001
0.01
0.1
IL - Load Current - A
1
Figure 5. Auto PFM/PWM Mode
Copyright © 2010–2011, Texas Instruments Incorporated
L = 1 mH,
COUT = 10 mF,
VOUT = 1.8 V,
Mode: Forced PWM
1.836
1.818
1.800
VIN = 3.3 V
1.782
VIN = 3.6 V
VIN = 4.2 V
1.764
VIN = 5 V
1.746
1.728
10
1.710
0.001
0.01
0.1
IL - Load Current - A
1
10
Figure 6. Forced PWM Mode
7
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
SHUTDOWN CURRENT
vs
INPUT VOLTAGE AND AMBIENT TEMPERATURE
QUIESCENT CURRENT
vs
INPUT VOLTAGE
25
TA = 85°C
TA = 85°C
20
0.75
Iq - Quiesent Current - mA
ISHDN - Shutdown Current - mA
1
0.50
TA = 25°C
0.25
3
3.5
4
4.5
5
VI - Input Voltage - V
5.5
10
3
3.5
4
4.5
5
VI - Input Voltage - V
6
Figure 8.
OSCILLATOR FREQUENCY
vs
INPUT VOLTAGE
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
0.12
TA = 85°C
3.05
0.1
TJ = 85°C
TA = 25°C
TJ = 25°C
3
0.08
2.95
TA = -40°C
0.04
2.85
0.02
3
3.5
4
4.5
5
VI - Input Voltage - V
Figure 9.
5.5
6
TJ = -40°C
0.06
2.9
2.8
2.5
5.5
Figure 7.
RDSON - W
fOSC - Oscillator Frequency - MHz
TA = -40°C
0
2.5
6
3.1
8
15
5
TA = -40°C
0
2.5
TA = 25°C
0
2.5
3
3.5
4
4.5
5
VI - Input Voltage - V
5.5
6
Figure 10. Low-Side Switch
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
INPUT VOLTAGE
RDISCHARGE
vs
INPUT VOLTAGE
0.2
600
0.18
500
0.16
400
TJ = 25°C
0.12
RDischarge - W
RDSON - W
VO = 3.3 V
TJ = 85°C
0.14
TJ = -40°C
0.1
0.08
VO = 1.8 V
300
200
0.06
VO = 1.2 V
0.04
100
0.02
0
2.5
3
3.5
4
4.5
5
VI - Input Voltage - V
5.5
6
0
2.5
3
Figure 11. High-Side Switch
3.5
4
4.5
5
VI - Input Voltage - V
5.5
6
Figure 12.
VOUT 50mV/Div
VOUT 50mV/Div
VIN = 3.6 V
VOUT = 1.8 V
IOUT = 20 mA
MODE = GND
L = 1.2 mH
COUT = 10 mF
SW 2V/Div
SW 2V/Div
ICOIL 500mA/Div
MODE = GND
VIN = 3.6 V
L = 1.2 mH
VOUT = 1.8 V
IOUT = 500 mA COUT = 10 mF
Time Base - 100ns/Div
Figure 13. Typical Operation (PWM Mode)
Copyright © 2010–2011, Texas Instruments Incorporated
ICOIL 200mA/Div
Time Base - 4ms/Div
Figure 14. Typical Operation (PFM Mode)
9
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
VOUT100 mV/Div
VOUT100 mV/Div
SW 2V/Div
SW 2V/Div
ICOIL1A/Div
ICOIL1A/Div
VIN = 3.6 V,
VOUT = 1.2 V,
IOUT = 0.2 A to 1 A
MODE = VIN
ILOAD500 mA/Div
VIN = 3.6 V,
VOUT = 1.2 V,
IOUT = 20 mA to 250 mA
ILOAD500 mA/Div
Time Base - 10 µs/Div
Time Base - 10 µs/Div
Figure 15. Load Transient Response
PWM Mode 0.2A To 1A
Figure 16. Load Transient
PFM Mode 20 mA to 250mA
VIN = 3.6 V to 4.2 V,
VOUT = 1.8 V,
IOUT = 500 mA
L = 1.2 mH,
200 mV/Div
500 mV/Div
2A/Div
VIN = 3.6 V,
VOUT = 1.8 V,
1A/Div
L = 1.2 mH
COUT = 10 mF
IOUT 200 mA to 1500 mA
Time Base - 100ms/Div
Figure 17. Load Transient Response
200 mA To 1500 mA
10
50 mV/Div
Time Base - 100 ms/Div
Figure 18. Line Transient Response PWM Mode
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
2 V/Div
500 mV/Div
1 V/Div
2 A/Div
500 mA/Div
50 mV/Div
VIN = 3.6 V to 4.2 V,
VOUT = 1.8 V,
IOUT = 50 mA,
L = 1.2 mH,
COUT = 10 mF
500 mA/Div
Time Base - 100 ms/Div
Figure 19. Line Transient PFM Mode
EN
1 V/Div
VIN = 3.6 V, L = 1.2 mH,
VOUT = 1.8 V, COUT = 10 mF
Load = 2R2
Time Base - 100 ms/Div
Figure 20. Startup Into Load – VOUT 1.8 V
VIN = 3.6 V,
VOUT = 1.8 V,
COUT = 10 mF,
No Load
SW
2 V/Div
VOUT
1 V/Div
Time Base - 2ms/Div
Figure 21. Output Discharge
Copyright © 2010–2011, Texas Instruments Incorporated
11
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
DETAILED DESCRIPTION
OPERATION
The TPS62060 step down converter operates with typically 3MHz fixed frequency pulse width modulation (PWM)
at moderate to heavy load currents. At light load currents the converter can automatically enter Power Save
Mode and operates then in PFM (Pulse Frequency Mode) mode.
During PWM operation the converter use a unique fast response voltage mode controller scheme with input
voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output
capacitors. At the beginning of each clock cycle initiated by the clock signal, the High Side MOSFET switch is
turned on. The current flows now from the input capacitor via the High Side MOSFET switch through the inductor
to the output capacitor and load. During this phase, the current ramps up until the PWM comparator trips and the
control logic will turn off the switch. The current limit comparator will also turn off the switch in case the current
limit of the High Side MOSFET switch is exceeded. After a dead time preventing shoot through current, the Low
Side MOSFET rectifier is turned on and the inductor current ramps down. The current flows now from the
inductor to the output capacitor and to the load. It returns back to the inductor through the Low Side MOSFET
rectifier..
The next cycle will be initiated by the clock signal again turning off the Low Side MOSFET rectifier and turning on
the High Side MOSFET switch.
POWER SAVE MODE
In TPS62060 pulling the Mode pin low enables Power Save Mode. If the load current decreases, the converter
enters Power Save Mode operation automatically. During Power Save Mode the converter skips switching and
operates with reduced frequency in PFM mode with a minimum quiescent current to maintain high efficiency. The
converter positions the output voltage typically +1% above the nominal output voltage. This voltage positioning
feature minimizes voltage drops caused by a sudden load step.
The transition from PWM mode to PFM mode occurs once the inductor current in the Low Side MOSFET switch
becomes zero, which indicates discontinuous conduction mode.
During the Power Save Mode the output voltage is monitored with a PFM comparator. As the output voltage falls
below the PFM comparator threshold of VOUTnominal +1%, the device starts a PFM current pulse. For this the High
Side MOSFET switch will turn on and the inductor current ramps up. After the on-time expires the switch will be
turned off and the Low Side MOSFET switch will be turned on until the inductor current becomes zero.
The converter effectively delivers a current to the output capacitor and the load. If the load is below the delivered
current the output voltage will rise. If the output voltage is equal or higher than the PFM comparator threshold,
the device stops switching and enters a sleep mode with typ. 18µA current consumption.
In case the output voltage is still below the PFM comparator threshold, further PFM current pulses will be
generated until the PFM comparator threshold is reached. The converter starts switching again once the output
voltage drops below the PFM comparator threshold due to the load current.
The PFM mode is exited and PWM mode entered in case the output current can no longer be supported in PFM
mode.
Dynamic Voltage Positioning
This feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. It is
active in Power Save Mode and regulates the output voltage 1% higher than the nominal value. This provides
more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off.
12
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
Output voltage
Voltage Positioning
Vout +1%
PFM Comparator
threshold
Light load
PFM Mode
Vout (PWM)
moderate to heavy load
PWM Mode
Figure 22. Power Save Mode Operation with automatic Mode transition
100% Duty Cycle Low Dropout Operation
The device starts to enter 100% duty cycle mode as the input voltage comes close to the nominal output voltage.
In order to maintain the output voltage, the High-Side MOSFET switch is turned on 100% for one or more cycles.
With further decreasing VIN the High-Side MOSFET switch is turned on completely. In this case the converter
offers a low input-to-output voltage difference. This is particularly useful in battery-powered applications to
achieve longest operation time by taking full advantage of the whole battery voltage range.
The minimum input voltage to maintain regulation depends on the load current and output voltage, and can be
calculated as:
VINmin = VOmax + IOmax × (RDS(on)max + RL)
With:
IOmax = maximum output current
RDS(on)max = maximum P-channel switch RDS(on).
RL = DC resistance of the inductor
VOmax = nominal output voltage plus maximum output voltage tolerance
Undervoltage Lockout
The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from
excessive discharge of the battery. It disables the output stage of the converter once the falling VIN trips the
under-voltage lockout threshold VUVLO. The under-voltage lockout threshold VUVLO for falling VIN is typically
1.78V. The device starts operation once the rising VIN trips under-voltage lockout threshold VUVLO again at
typically 1.95V.
Output Capacitor Discharge.
With EN = GND, the devices enter shutdown mode and all internal circuits are disabled. The SW pin is
connected to PGND via an internal resistor to discharge the output capacitor.
MODE SELECTION
The MODE pin allows mode selection between forced PWM mode and Power Save Mode.
Connecting this pin to GND enables the Power Save Mode with automatic transition between PWM and PFM
mode. Pulling the MODE pin high forces the converter to operate in fixed frequency PWM mode even at light
load currents. This allows simple filtering of the switching frequency for noise sensitive applications. In this mode,
the efficiency is lower compared to the power save mode during light loads.
Copyright © 2010–2011, Texas Instruments Incorporated
13
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
The condition of the MODE pin can be changed during operation and allows efficient power management by
adjusting the operation mode of the converter to the specific system requirements.
ENABLE
The device is enabled by setting EN pin to high. At first, the internal reference is activated and the internal
analog circuits are settled. Afterwards, the soft start is activated and the output voltage is ramped up. The output
voltages reaches 95% of its nominal value within tSTARTof typically 500 µs after the device has been enabled. The
EN input can be used to control power sequencing in a system with various DC/DC converters. The EN pin can
be connected to the output of another converter, to drive the EN pin high and getting a sequencing of supply
rails. With EN = GND, the device enters shutdown mode. In this mode, all circuits are disabled and the SW pin is
connected to PGND via an internal resistor to discharge the output.
SOFT START
The TPS62060 has an internal soft start circuit that controls the ramp up of the output voltage. Once the
converter is enabled and the input voltage is above the undervoltage lockout threshold VUVLOthe output voltage
ramps up from 5% to 95% of its nominal value within tRamp of typ. 250µs.
This limits the inrush current in the converter during start up and prevents possible input voltage drops when a
battery or high impedance power source is used.
During soft start, the switch current limit is reduced to 1/3 of its nominal value ILIMF until the output voltage
reaches 1/3 of its nominal value. Once the output voltage trips this threshold, the device operates with its
nominal current limit ILIMF.
INTERNAL CURRENT LIMIT / FOLD-BACK CURRENT LIMIT FOR SHORT-CIRCUIT PROTECTION
During normal operation the High-Side and Low-Side MOSFET switches are protected by its current limits ILIMF.
Once the High-Side MOSFET switch reaches its current limit, it is turned off and the Low-Side MOSFET switch is
turned on. The High-Side MOSFET switch can only turn on again, once the current in the Low -Side MOSFET
switch decreases below its current limit ILIMF. The device is capable to provide peak inductor currents up to its
internal current limit ILIMF..
As soon as the switch current limits are hit and the output voltage falls below 1/3 of the nominal output voltage
due to overload or short circuit condition, the foldback current limit is enabled. In this case the switch current limit
is reduced to 1/3 of the nominal value ILIMF.
Due to the short-circuit protection is enabled during start-up, the device does not deliver more than 1/3 of its
nominal current limit ILIMF until the output voltage exceeds 1/3 of the nominal output voltage. This needs to be
considered when a load is connected to the output of the converter, which acts as a current sink.
CLOCK DITHERING
In order to reduce the noise level of switch frequency harmonics in the higher RF bands, the TPS62060 family
has a built-in clock-dithering circuit. The oscillator frequency is slightly modulated with a sub clock causing a
clock dither of typ. 6ns.
THERMAL SHUTDOWN
As soon as the junction temperature, TJ, exceeds 150°C (typical) the device goes into thermal shutdown. In this
mode, the High-Side and Low-Side MOSFETs are turned off. The device continues its operation when the
junction temperature falls below the thermal shutdown hysteresis.
14
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
APPLICATION INFORMATION
VIN = 2.7 V to 6 V
TPS62060
PVIN
SW
R1
360 kΩ
AVIN
EN
MODE
AGND
PGND
CIN
10 µF
VOUT = 1.8 V
up to 1.6 A
L
1.0 µH
FB
Cff
22 pF
COUT
10 µF
R2
180 kΩ
Figure 23. TPS62060 1.8V Adjustable Output Voltage Configuration
OUTPUT VOLTAGE SETTING
The output voltage can be calculated to:
R
V OUT + VREF
1) 1
R2
ǒ
Ǔ
with an internal reference voltage VREF typically 0.6V.
To minimize the current through the feedback divider network, R2 should be within the range of 120 kΩ to 360
kΩ. The sum of R1 and R2 should not exceed ~1MΩ, to keep the network robust against noise. An external
feed-forward capacitor Cff is required for optimum regulation performance. Lower resistor values can be used.
R1 and Cff places a zero in the loop. The right value for Cff can be calculated as:
1
fz =
= 25 kHz
2 ´ p ´ R1 ´ C ff
Therefore, the feed forward capacitor can be calculated to:
1
C ff =
2 ´ p ´ R1 ´ 25 kHz
OUTPUT FILTER DESIGN (INDUCTOR AND OUTPUT CAPACITOR)
The internal compensation network of TPS62060 is optimized for a LC output filter with a corner frequency
of:
fc =
1
2 ´ p ´ (1μH ´ 10μF)
= 50kHz
The part operates with nominal inductors of 1.0µH to 1.2 µH and with 10µF to 22µF small X5R and X7R ceramic
capacitors. Please refer to the lists of inductors and capacitors. The part is optimized for a 1.0µH inductor and
10µF output capacitor.
Inductor Selection
The inductor value has a direct effect on the ripple current. The selected inductor has to be rated for its dc
resistance and saturation current. The inductor ripple current (ΔIL) decreases with higher inductance and
increases with higher VI or VO.
Equation 1 calculates the maximum inductor current in PWM mode under static load conditions. The saturation
current of the inductor should be rated higher than the maximum inductor current as calculated with Equation 2.
This is recommended because during heavy load transient the inductor current rises above the calculated value.
DI L + Vout
1 * Vout
Vin
L
ƒ
Copyright © 2010–2011, Texas Instruments Incorporated
(1)
15
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
I Lmax + I outmax )
www.ti.com
DI L
2
(2)
With:
f = Switching Frequency (3MHz typical)
L = Inductor Value
ΔIL = Peak-to-Peak inductor ripple current
ILmax = Maximum inductor current
Ioutmax = Maximum output current
A more conservative approach is to select the inductor current rating just for the switch current of the converter.
Accepting larger values of ripple current allows the use of lower inductance values, but results in higher output
voltage ripple, greater core losses, and lower output current capability.
The total losses of the coil have a strong impact on the efficiency of the DC/DC conversion and consist of both
the losses in the dc resistance R(DC) and the following frequency-dependent components:
• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)
• Additional losses in the conductor from the skin effect (current displacement at high frequencies)
• Magnetic field losses of the neighboring windings (proximity effect)
• Radiation losses
Table 2. List of Inductors
DIMENSIONS [mm3]
INDUCTANCE μH
3.2 x 2.5 x 1.2 max
1.0
MIPSAZ3225D
FDK
3.2 x 2.5 x 1.0 max
1.0
LQM32PN (MLCC)
Murata
3.7 x 4 x 1.8 max
1.0
LQH44 (wire wound)
Murata
4.0 x 4.0 x 2.6 max
1.2
NRG4026T (wire wound)
Taiyo Yuden
3.5 x 3.7 x 1.8 max
1.2
DE3518 (wire wound)
TOKO
INDUCTOR TYPE
SUPPLIER
Output Capacitor Selection
The advanced fast-response voltage mode control scheme of the TPS62060 allows the use of tiny ceramic
capacitors. Ceramic capacitors with low ESR values have the lowest output voltage ripple and are
recommended. The output capacitor requires either an X7R or X5R dielectric. Y5V and Z5U dielectric capacitors,
aside from their wide variation in capacitance over temperature, become resistive at high frequencies and may
not be used. For most applications a nominal 10µF or 22µF capacitor is suitable. At small ceramic capacitors, the
DC-bias effect decreases the effective capacitance. Therefore a 22µF capacitor can be used for output voltages
higher than 2V, see list of capacitors.
In case additional ceramic capacitors in the supplied system are connected to the output of the DC/DC converter,
the output capacitor COUT need to be decreased in order not to exceed the recommended effective capacitance
range. In this case a loop stability analysis must be performed as described later.
At nominal load current, the device operates in PWM mode and the RMS ripple current is calculated as:
I RMSCout + Vout
1 * Vout
1
Vin
L
ƒ
2
Ǹ3
(3)
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. For most applications a 10µF ceramic capacitor is recommended. The input capacitor can be
increased without any limit for better input voltage filtering.
16
Copyright © 2010–2011, Texas Instruments Incorporated
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
Take care when using only small ceramic input capacitors. When a ceramic capacitor is used at the input and the
power is being supplied through long wires, such as from a wall adapter, a load step at the output or VIN step on
the input can induce ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop
instability or could even damage the part by exceeding the maximum ratings.
Table 3. List of Capacitors
CAPACITANCE
TYPE
SIZE [mm3]
SUPPLIER
10μF
GRM188R60J106M
0603: 1.6 x 0.8 x 0.8
Murata
22μF
GRM188R60G226M
0603: 1.6 x 0.8 x 0.8
Murata
22µF
CL10A226MQ8NRNC
0603: 1.6 x 0.8 x 0.8
Samsung
10µF
CL10A106MQ8NRNC
0603: 1.6 x 0.8 x 0.8
Samsung
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals
• Switching node, SW
• Inductor current, IL
• Output ripple voltage, VOUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or wrong L-C output filter
combinations. As a next step in the evaluation of the regulation loop, the load transient response is tested. The
time between the application of the load transient and the turn on of the P-channel MOSFET, the output
capacitor must supply all of the current required by the load. VOUT immediately shifts by an amount equal to
ΔI(LOAD) x ESR, where ESR is the effective series resistance of COUT. ΔI(LOAD) begins to charge or discharge CO
generating a feedback error signal used by the regulator to return VOUT to its steady-state value. The results are
most easily interpreted when the device operates in PWM mode at medium to high load currents.
During this recovery time, VOUT can be monitored for settling time, overshoot, or ringing; that helps evaluate
stability of the converter. Without any ringing, the loop has usually more than 45° of phase margin.
Copyright © 2010–2011, Texas Instruments Incorporated
17
TPS62061, TPS62063
TPS62060
SLVSA95A – MARCH 2010 – REVISED JANUARY 2011
www.ti.com
LAYOUT CONSIDERATIONS
vertical spacer
vertical spacer
Mode
Enable
5.08 mm
VIN
GND
CIN
COUT
VOUT
7.19 mm
2.54 mm
R2
R1
CFF
GND
L
3.81 mm
Figure 24. PCB Layout
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well
as EMI and thermal problems. It is critical to provide a low inductance, impedance ground path. Therefore, use
wide and short traces for the main current paths. The input capacitor should be placed as close as possible to
the IC pins as well as the inductor and output capacitor.
Connect the AGND and PGND Pins of the device to the PowerPAD™ land of the PCB and use this pad as a star
point. Use a common Power PGND node and a different node for the Signal AGND to minimize the effects of
ground noise. The FB divider network should be connected right to the output capacitor and the FB line must be
routed away from noisy components and traces (e.g., SW line).
Due to the small package of this converter and the overall small solution size the thermal performance of the
PCB layout is important. To get a good thermal performance a four or more Layer PCB design is recommended.
The PowerPAD of the IC must be soldered on the power pad area on the PCB to get a proper thermal
connection. For good thermal performance the PowerPAD on the PCB needs to be connected to an inner GND
plane with sufficient via connections. Please refer to the documentation of the evaluation kit.
18
Copyright © 2010–2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2011
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package
Drawing
Pins
Package Qty
Eco Plan
(2)
Lead/
Ball Finish
MSL Peak Temp
(3)
TPS62060DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS62060DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS62061DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS62061DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS62063DSGR
ACTIVE
WSON
DSG
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
TPS62063DSGT
ACTIVE
WSON
DSG
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR
Samples
(Requires Login)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2011
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Apr-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
TPS62060DSGR
WSON
DSG
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS62060DSGT
WSON
DSG
8
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS62061DSGR
WSON
DSG
8
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS62061DSGT
WSON
DSG
8
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS62063DSGR
WSON
DSG
8
3000
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
TPS62063DSGT
WSON
DSG
8
250
179.0
8.4
2.2
2.2
1.2
4.0
8.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Apr-2011
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TPS62060DSGR
WSON
DSG
8
3000
195.0
200.0
45.0
TPS62060DSGT
WSON
DSG
8
250
195.0
200.0
45.0
TPS62061DSGR
WSON
DSG
8
3000
195.0
200.0
45.0
TPS62061DSGT
WSON
DSG
8
250
195.0
200.0
45.0
TPS62063DSGR
WSON
DSG
8
3000
195.0
200.0
45.0
TPS62063DSGT
WSON
DSG
8
250
195.0
200.0
45.0
Pack Materials-Page 2
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