TI TPS65110RGE

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SLVS495 − SEPTEMBER 2003
FEATURES
DESCRIPTION
D Complete LTPS-LCD Bias Solution
D Triple Output Charge Pump Providing
D
D
D
D
D
D
D
D
D
VCC at 16 mA, VDD at 2 mA, VSS at 1 mA
2.4 V to 5.5 V Input Voltage Range
Fixed Output Voltages of 3.3 V, 7.5 V, −2.7 V
or 5.0 V, 9.0 V, −3.0 V
50 µA Typical Quiescent Current
Less Than 1 µA Shutdown Current
Ultra-Low Ripple (VCC = 5 mV,
Typical at 5 mA)
Autonomous Boost for VCC Supply
1.5% Accuracy on Fixed VCC Output Voltage
Sequential Power Control
24-Pin QFN Package (4 x 4)
APPLICATIONS
D Small Form LTPS−LCD Displays
D PDAs, Pocket PCs
D Smart Phones
The TPS65110/11 is a very compact power supply
solution providing the three voltages required by many
LTPS LCD displays.
All three regulated outputs are generated using a charge
pump topology.
The VCC charge pump provides precise, high efficiency,
and very low ripple dc/dc conversion for the LCD analog
power. The VCC boost ratio (x1.0, x1.33, x1.5, and x2.0)
is automatically set based on input and output voltage
conditions. The VCC output assures 16 mA of current by
using three 0.22-µF flying capacitors. If the required output
current is smaller, smaller capacitors can be applied.
The VDD charge pump provides a higher positive voltage,
and the VSS charge pump provides the negative output
voltage. Power up/down sequences are internally set and
are secured even in cases of sudden and abnormal VIN
drop.
One of the most significant features of the TPS65110/11
is the ultra-low output voltage ripple, as the VCC charge
pump achieves 5-mV output ripple voltage.
APPLICATION CIRCUIT FOR TPS65111
AVAILABLE OUTPUT VOLTAGE OPTIONS
PART NUMBER
0.1 µF
TPS65110RGE
VIN
2.4 V to 5.5 V
VIN
4.7 µF
VSS
0.22 µF
0.22 µF
CCP1
CDP1
CCN1
CCP2
CDN1
CDP2
CCN2
CCP3
CDN2
CDP3
CCN3
CDN3
VCC
2.2 µF
VDD
7.5 V
VSS
−2.7 V
TPS65111RGE
5.0 V
9.0 V
−3.0 V
(1) VDD BOOST
X3
X2
2.2 µF
TPS65111
0.22 µF
VCC
5 V, 16 mA
VSS
−3 V, 1 mA
CSP CSN
VCC
3.3 V
0.1 µF
0.1 µF
0.1 µF
VDD
1 µF
VDD
9 V, 2 mA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!" # $%&" !# '%()$!" *!"&+ *%$"#
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Copyright  2003, Texas Instruments Incorporated
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage at VIN (2)
−0.3 V to 7.0 V
Input voltage at EN, CLK, DATA (2)
Power dissipation (3)
−0.3 V to VIN + 0.3 V
46°C/W
Virtual operation junction temperature, TJ
−40°C to 125°C
Storage temperature range
−65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260°C
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
(3) The package thermal impedance is calculated in accordance with JESD 51−5.
CHANNEL PERFORMANCE OVERVIEW
CHANNEL
VCC
VDD
VSS
Output Voltage Control
Regulated
Regulated
Regulated
Boost Ratio
x1; x1.333; x1.5; x2
x2 or x3
x−1
Boost setting
Autonomous Boost
Fixed
Fixed
Power Supply
VIN
VCC
VCC
Output Current
16 mA
2 mA
1 mA
Accuracy
±1.5%
±3%
±3%
Num of Ext CAP
4
4
2
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
UNIT
Input voltage range, VIN
2.4
5.5
V
Main output voltage, VCC
3.0
5.2
V
V
Positive output voltage range, VDD
6.5
10
Negative output voltage range, VSS
−4.5
−2.4
V
VIN input capacitor(Ci)
4.7
µ!
VCC output capacitor(CCO)
VDD output capacitor(CDO)
2.2
µ!
1.0
µ!
VSS output capacitor(CSO)
VCC flying capacitors(CC1, CC2, CC3)
2.2
µ!
0.22
µ!
0.1
µ!
VDD and VSS flying capacitors(CD1, CD2, CD3, CS)
Operating ambient temperature, TA
−40
85
°C
Operating junction temperature, TJ
−40
125
°C
2
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ELECTRICAL CHARACTERISTICS
"" # "$ % " " &'°($ (()*((&*((*&& µ!$ (+)*(+&*(+*(,*) µ!$ ((-*(,-*&& µ!$
(+-*) µ!$ ./*0 .$ 1 PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE
VI
Input voltage range
IQ
Operating quiescent current
VI = 2.8 V, EN = VI,
SCLK = DATA = VROM = GND, No load
ISD
Shutdown supply current
VI = 2.8 V, EN = GND,
SCLK = DATA = VROM = GND
fmax
Maximum operating frequency
VUVLO
Under−voltage lockout threshold
2.4
VI = 0 V to 3.6 V
VI = 3.6 V to 0 V
Hysteresis
50
5.5
V
120
µA
1
µA
kHz
320
400
520
2.1
2.3
2.5
2.0
2.2
2.4
30
100
V
mV
LOGIC SECTION
VIH
EN/CLK/DATA high level input voltage
VIL
IIH / IIL
EN/CLK/DATA low level input voltage
Logic input current
VI = 2.4 V to 3.5 V
VI = 3.5 V to 5.5 V
1.3
V
1.5
EN = GND or VI
0.4
V
0.01
0.1
µA
3.3
3.35
TPS65110 OUTPUT (VCC, VDD, VSS)
VCC
IVCC
VCC Output DC voltage range
VCC Output current
VRIPPLEC VCC Output voltage ripple
VREGC
VCC Line regulation
LREGC
VCC Load regulation
trC
tfC
VDD
IVDD
VCC Rise time
VCC Fall time
VCC = 3.3 V, IVDD = 1.0 mA, VDD boost = x3
VCC = 3.3 V
V
mA
5
90% to 10%, no load
VDD Output DC voltage range
VDD Output current
mV
0.1
0.5
0.3
1
%/V
%
100
µ,
6
mS
84%
86%
7.27
7.5
7.73
2
V
mA
IVDD = 1 mA
10% to 90%, no load
7
mV
1.4
mS
90% to 10%, no load
2.4
mS
VDD Efficiency
VCC to VDD, VCC = 3.3 V, VDD = 7.5 V,
IVDD = 0.2 mA
VCC to VDD, VCC = 3.3 V, VDD = 7.5 V, IVDD = 2 mA
VSS Output DC voltage range
VSS Output current
VCC = 3.3 V, IVSS = 0.2 mA
VCC = 3.3 V
VSS Efficiency
16
VI = 2.8 V, IVCC = no load to 10 mA
10% to 90%, no load
VI to VCC, VCC = 3.3 V, IVCC = 1 mA
VI to VCC, VCC = 3.3 V, IVCC = 10 mA
VRIPPLES VSS Output voltage ripple
trS
VSS Rise time
tfS
VSS Fall time
3.25
IVCC = 5 mA
VI = 2.4 V to 5.5 V
VCC Efficiency
VRIPPLED VDD Output voltage ripple
trD
VDD Rise time
tfD
VDD Fall time
VSS
IVSS
VI = 2.8 V, IVCC = 5 mA
IVDD = 2 mA, IVSS = 1 mA
70%
70%
−2.78
−2.7
1
−2.62
V
mA
IVSS = 0.2 mA
10% to 90%, no load
220
µ,
90% to 10%, no load
2
mS
VCC to VSS, VCC = 3.3 V, VSS = −2.8 V,
IVSS = 0.2 mA
VCC to VSS, VCC = 3.3 V, VSS = −2.8 V,
IVSS = 1 mA
3
mV
82%
82%
3
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ELECTRICAL CHARACTERISTICS Continued
"" # "$ % " " &'°($ (()*((&*((*&& µ!$ (+)*(+&*(+*(,*) µ!$ ((-*(,-*&& µ!$
(+-*) µ!$ ./*0 .$ 1 TPS65111 OUTPUT (VCC, VDD, VSS)
VCC
IVCC
VCC Output dc voltage range
Maximum VCC output current
VRIPPLEC VCC Output voltage ripple
VREGC
VCC Line regulation
LREGC
VCC Load regulation
trC
tfC
VDD
IVDD
VCC Rise time
VCC Fall time
VSS Efficiency
4
V
mA
VI = 3.6 V, IVCC = no load to 10 mA
10% to 90%, no load
0.3
1
200
µS
5
9
mS
90% to 10%, no load
VCC = 5.0 V, IVDD = 1.0 mA, VDD boost = x2
VCC = 5.0 V
VRIPPLES VSS Output voltage ripple
trS
VSS Rise time
tfS
VSS Fall time
5.075
0.5
VDD Output dc voltage range
Maximum VDD output current
VSS Output dc voltage range
Maximum VSS output current
5.0
16
0.1
VI to VCC, VCC = 5.0 V, IVCC = 1 mA
VI to VCC, VCC = 5.0 V, IVCC = 10 mA
VDD Efficiency
4.925
IVCC = 5 mA
VI = 2.7 V to 5.5 V
VCC Efficiency
VRIPPLED VDD Output voltage ripple
trD
VDD Rise time
tfD
VDD Fall time
VSS
IVSS
VI = 3.6 V, IVCC = 5 mA
IVDD = 2 mA, IVSS = 1 mA
mV
%/V
%
88%
90%
8.73
9.0
9.27
2
V
mA
IVDD = 1 mA
10% to 90%, no load
8
mV
1.8
mS
90% to 10%, no load
3
mS
VCC to VDD, VCC = 5.0 V, VDD = 9.0 V,
IVDD = 0.2mA
VCC to VDD, VCC = 5.0 V, VDD = 9.0 V,
IVDD = 2mA
VCC = 5.0 V, IVSS = 0.2 mA
VCC = 5.0 V
87%
88%
−3.09
−3.0
1
−2.91
V
mA
IVSS = 0.2 mA
10% to 90%, no load
250
µ,
90% to 10%, no load
2.4
mS
VCC to VSS, VCC = 5.0 V, VSS = −3.0 V,
IVSS = 0.2 mA
VCC to VSS, VCC = 5.0 V, VSS = −3.0 V,
IVSS = 1 mA
3
58%
58%
mV
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PIN ASSIGNMENTS
CSN1
VSS
PGND
CDP1
CDN1
CDN3
RGE PACKAGE
(TOP VIEW)
24 23 22 21 20 19
1
18
2
17
3
Thermal
Pad
4
5
6
16
15
14
7
8
13
9 10 11 12
CDN2
CDP3
CDP2
VDD
VROM
AGND
CCN1
CCP1
VIN
DATA
CLK
EN
CSP1
VCC
CCN3
CCP3
CCN2
CCP2
Terminal Functions
TERMINAL
DESCRIPTION
NO.
NAME
1
CSP1
VSS Positive terminal for CS
2
VCC
VCC Charge pump output
3
CCN3
VCC Negative terminal for CC3
4
CCP3
VCC Positive terminal for CC3
5
CCN2
VCC Negative terminal for CC2
6
CCP2
VCC Positive terminal for CC2
7
CCN1
VCC Negative terminal for CC1
8
CCP1
VCC Positive terminal for CC1
9
VIN
10
DATA
Input supply voltage
I2C serial data input
11
CLK
I2C serial clock input
12
EN
Power on/off enable logic input (H : active / L : shutdown)
13
AGND
Analog GND
14
VROM
EEPROM power supply
15
VDD
VDD Charge pump output
16
CDP2
VDD Positive terminal for CD2
17
CDP3
VDD Positive terminal for CD3
18
CDN2
VDD Negative terminal for CD2
19
CDN3
VDD Negative terminal for CD3
20
CDN1
VDD Negative terminal for CD1
21
CDP1
VDD Positive terminal for CD1
22
PGND
Power GND
23
VSS
24
CSN1
VSS Charge pump output
VSS Negative terminal for CS
5
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FUNCTIONAL BLOCK DIAGRAM
VIN
PSEL
VIN
VCC
VPS
VIN_PG
PWR_ON
CLK
VBG
BG
OSC
IBIAS
VBG
VIN
BOOST
CTRL
VINDET
VBG
IB
VPS
SYS_EN
EN
EN
Sequential
Power
Control
CCP1
VIN_PG
CCN1
VCC_ON
CCP2
VCC
VSS_ON
CLK
CCN2
VDD_ON
VBG
CCP3
CCN3
CLK
VCC
VPS
VCC
CSP1
VROM
CLK
VBG
VSS
CSN1
VSS
CLK
EN
VPS
SCLK
DATA
Serial
I/F
VCC
CDP1
EEPROM
VROM
CDN1
VDD
CLK
VBG
CDP2
CDN2
CDP3
CDN3
GND
6
VDD
PGND
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TYPICAL APPLICATION CIRCUIT
VSS
CD1
CSO
0.1 µF
2.2 µF
CDN3
CDN1
CDP1
PGND
VSS
CSN1
PGND
CD2
CS
0.1 µF
VCC
VCC
CCN3
CCO
CC3
0.22 µF
PGND
CCP3
CCN2
23
22
21
20
19
1
18
2
17
3
16
4
15
5
14
CC2
6
13
10
CC1
0.22 µF
VIN
2.4 V to 5.5 V
11
CDN2
0.1 µF
CDP3
CD3
CDP2
VDD
VROM
0.1 µF
VDD
CDO
1 µF
AGND
PGND
12
EN
9
CLK
8
DATA
7
VIN
CCP2
CCP1
0.22 µF
CCN1
2.2 µF
CSP1
24
CIN
AGND
4.7 µF
Enable
Signal
7
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TYPICAL CHARACTERISTICS
VCC EFFICIENCY
VCC EFFICIENCY
100
100
TPS65110
VCC = 3.3 V
I(VCC) = 10 mA
90
Efficiency − %
90
Efficiency − %
TPS65110
VI = 2.8 V
VCC = 3.3 V
80
70
80
70
I(VCC) = 1 mA
60
60
50
50
2
2.5
3
3.5
4
VI − Input Voltage − V
4.5
0
5
5
10
25
30
35
40
Figure 2
VCC LOAD REGULATION
VCC LOAD REGULATION
3.35
3.35
TPS65110
I(VDD) = 2 mA,
I(VSS) = 1 mA,
VI = 2.8 V
VO− VCC Output Voltage − V
VO− VCC Outout Voltage − V
20
I(VCC) − Supply Current − mA
Figure 1
3.30
15
TA = −40°C
TA = 25°C
3.25
TPS65110
I(VDD) = 2 mA,
I(VSS) = 1 mA,
VI = 3.6 V
TA = −40°C
3.30
TA = 25°C
3.25
TA = 85°C
TA = 85°C
3.20
3.20
0
10
20
30
40
I(VCC) − Supply Current − mA
Figure 3
8
50
0
10
20
30
40
I(VCC) − Supply Current − mA
Figure 4
50
60
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VDD LOAD REGULATION
2.80
TPS65110
VCC = 3.3 V
I(VCC) = I(VSS) = no load
VO− VSS Output Voltage − V
VO− VDD Output Voltage − V
7.6
VSS LOAD REGULATION
TA = −40°C
7.5
7.4
TA = 25°C
TA = 85°C
TPS65110
VCC = 3.3 V
I(VCC) = I(VDD) = no load
2.75
TA = −40°C
2.70
2.65
TA = 25°C
2.60
TA = 85°C
7.3
2.55
7.2
2.50
0
1
2
3
4
5
I(VDD) − Supply Current − mA
6
7
0
1
Figure 5
6
7
5
5.5
Figure 6
MAXIMUM SWITCHING FREQUENCY
vs
INPUT VOLTAGE
QUIESCENT CURRENT
vs
INPUT VOLTAGE
490
100
460
I q − Quiescent Current − µ A
f − Maximum Switching Frequency − kHz
2
3
4
5
I(VSS) − Supply Current − mA
TA = 25°C
430
TA = −40°C
400
TA = 85°C
370
80
TA = 25°C
TA = 85°C
60
TA = −40°C
40
20
340
310
2
2.5
3
3.5
4
4.5
VI − Input Voltage − V
Figure 7
5
5.5
0
2
2.5
3
3.5
4
4.5
VI − Input Voltage − V
Figure 8
9
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POWERUP SEQUENCE
POWERDOWN SEQUENCE
VDD
VDD
VCC
VCC
EN
EN
VSS
VSS
(VI = 3.0 V, VCC = 3.3 V, VDD = 7.5 V, VSS = −2.7 V, VDDBOOST = x3,
No load, CC1/2/3 = 0.22 µF, CCO = 2.2 µF)
(VI = 3.0 V, VCC = 3.3 V, VDD = 7.5 V, VSS = −2.7 V, VDDBOOST = x3,
No load, CC1/2/3 = 0.22 µF, CCO = 2.2 µF)
Figure 10
Figure 9
VCC RIPPLE VOLTAGE
VCC RIPPLE VOLTAGE
IO = 10 mA
IO = 0.5 mA
VCC
VCC
CCP1
CCP1
(VI = 2.7 V, VCC = 3.3 V, TA = 25°C, CC1/2/3 = 0.1 µF,
CCO = 2.2 µF)
Figure 11
10
(VI = 2.7 V, VCC = 3.3 V, TA = 25°C, CC1/2/3 = 0.1 µF,
CCO = 2.2 µF)
Figure 12
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DETAILED DESCRIPTION
VCC Charge Pump
The VCC output provides a very high efficiency, regulated, dc/dc conversion through a wide input range by
supporting x1.0, x1.33, x1.5, and x2.0 boost charge pump operation. TPS65110 automatically sets the boost
ratio based on input and output voltage conditions. For example, when the input voltage from a battery becomes
lower, the device automatically increases the boost ratio from x1.33 to x1.5. In a fixed input voltage mode, the
device provides for higher conversion efficiency; for example, in the case of 2.8 V to 3.3 V conversion or 2.8
V to 5.0 V conversion. In this case, the VCC charge pump can enter into a SKIP mode operation in order to
maintain the efficiency of a low load condition. The highest frequency of the charge pump is 400 kHz (typ). The
charge pump operates by using higher frequencies in the heavier load current conditions, and decreases the
frequency in the lighter load conditions. Maximum output current and operating frequency characteristics are
dependent on external conditions such as the flying capacitor, output capacitor, and ambient temperature
range.
VIN [V]
VCC[V]
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
x1.5
x1.33
5.0
NA
x2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.1
4.2
4.4
4.6
4.8
5.0
5.2
5.4
5.5
x1
x1.5
x1.33
x1
NOTE: Gray portion is HYSTERESIS.
Of importance, the VCC charge pump is also used as the power source for the VDD and VSS charge pumps.
Therefore, consider a case where the VDD charge pump’s output current is required to be 2mA, and the boost
ratio is x3. With this condition, the required (additional) current for the VCC output is slightly more than 6 mA.
If the VSS charge pump output current requirement is 1 mA, then the (additional) required current from VCC
is another 1 mA. (Note: the VCC charge pump maintains a minimum of 16-mA output capability in addition to
the loads required to support the VDD and VSS charge pumps under the recommended conditions.)
VDD Charge Pump
The power source for the VDD charge pump is the VCC charge pump. The output voltage and boost ratio of
the VDD charge pump are fixed at either a 7.5 V and x3 boost (TPS65110), or a 9.0 V and x2 boost (TPS65111).
The topology of this charge pump is SKIP mode, and the maximum frequency is 400 kHz. Maximum output
current is dependent on the flying capacitors and ambient temperature range (refer to the typical
characteristics).
VSS Charge Pump
The VSS charge pump is powered from the VCC charge pump and has a fixed output voltage of either –2.7
V (TPS65110) or –3.0 V (TPS65111). The boost ratio for the VSS charge pump is fixed at x−1. The operation
topology is SKIP mode and has a maximum frequency of 400 kHz. Maximum output current is dependent on
the flying capacitor and ambient temperature range (refer to the typical characteristics).
UVLO − Under Voltage Lockout
The UVLO provides for the save operation of the device. It prevents the converter from turning on when the
voltage on the VIN pin is less than the threshold voltage of UVLO. Note that although the input voltage range
of the product is shown to be down to 2.4 V, the maximum threshold of the UVLO for a rising VIN is 2.5 V.
Therefore, to operate down to 2.4 V, the device must first be powered by a source of more than 2.5 V.
Enable
Low logic on the EN pin forces the TPS6511x into shutdown mode. In shutdown, the power switch, drivers,
voltage reference, oscillator, and all other functions are turned off. The supply current is reduced to less than
1 µA in shutdown mode.
Power-Up and Power-Down Sequencing
The TPS65110/11 controls power-up and power-down sequence through an enable pin. This signal should be
terminated and not be left floating to prevent miss-operation.
Power-Up Sequence
When the enable pin EN is pulled high, the device starts its power on sequencing. The VCC output starts up
first. When the output voltage VCC has reached 75% of its nominal value, the VSS output comes up next. When
VSS has reached 75% of the nominal value, the positive output VDD finally comes up.
11
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Power-Down Sequencing
When the enable pin EN is pulled low, the device starts its power-down sequencing. The VDD output goes down
first. When the output voltage VDD has reached 70% of its nominal value, the VSS output goes down next.
When VSS has reached 70% of the nominal value, the positive output VCC finally goes down. The TPS6511x
ensures this power-down sequence even in the case of a sudden VI drop.
2.3 V
VIN
EN
1
2
1
1
1
2
Vref
(Internal)
x0.75
VCC
2.2 V
3
x0.75
3
3
4
3
VSS
x0.7
x0.7
4
x0.7
2
x0.7
VDD
12
1
x0.7
5
x0.7
SYS_EN
(Internal)
2
4
1 2
Power Sequence
PACKAGE OPTION ADDENDUM
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30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
Lead/Ball Finish
MSL Peak Temp (3)
TPS65110RGE
ACTIVE
QFN
RGE
24
92
TBD
CU SN
Level-2-235C-1 YEAR
TPS65110RGER
ACTIVE
QFN
RGE
24
3000
TBD
CU SN
Level-2-235C-1 YEAR
TPS65110RGERG4
ACTIVE
QFN
RGE
24
3000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
TPS65111RGE
ACTIVE
QFN
RGE
24
150
TBD
CU SN
Level-2-235C-1 YEAR
TPS65111RGER
ACTIVE
QFN
RGE
24
3000
TBD
CU SN
Level-2-235C-1 YEAR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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