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SCDS188 – JANUARY 2005
Description
Features
The TS3A5017 is a dual single-pole quadruple-throw
(4:1) analog switch that is designed to operate from
2.3 V to 3.6 V. This device can handle both digital and
analog signals, and signals up to V+ can be transmitted
in either direction.
Applications
D Sample-and-Hold Circuit
D Battery-Powered Equipment
D Audio and Video Signal Routing
D Communication Circuits
1EN 1
Logic
Control
IN2 2
15 2EN
14 IN1
1S3 4
13 2S4
1S2 5
12 2S3
1S1 6
11 2S2
1D 7
10 2S1
L
IN2
L
IN1
L
Low Total Harmonic Distortion (THD)
2.3-V to 3.6-V Single-Supply Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
V+ = 3.3 V, TA = 25°C
Dual Analog
MUX/DEMUX
(4:1 MUX/DEMUX)
Configuration
Number of channels
2
ON-state resistance (ron)
11 Ω
ON-state resistance match (∆ron)
1Ω
ON-state resistance flatness (ron(flat))
Turn-on/turn-off time (tON/tOFF)
Charge injection (QC)
FUNCTION TABLE
EN
Excellent ON-State Resistance Matching
Summary of Characteristics
9 2D
GND 8
Low Charge Injection
− 2000-V Human-Body Model
(A114-B, Class II)
− 1000-V Charged-Device Model (C101)
16 V+
1S4 3
Isolation in the Powered-Down Mode, V+ = 0
Low ON-State Resistance (10 W)
D ESD Performance Tested Per JESD 22
SOIC, SSOP, TSSOP, OR TVSOP PACKAGE
(TOP VIEW)
Logic
Control
D
D
D
D
D
D
D
Bandwidth (BW)
D TO S
S TO D
D = S1
L
L
H
D = S2
L
H
L
D = S3
L
H
H
D = S4
H
X
X
OFF
7Ω
5 ns/1.5 ns
5 pC
165 MHz
OFF isolation (OISO)
−48 dB at 10 MHz
Crosstalk (XTALK)
−49 dB at 10 MHz
Total harmonic distortion (THD)
Leakage current (ID(OFF)/IS(OFF))
Power-supply current (I+)
Package option
0.21%
±0.1 µA
2.5 µA
16-pin SOIC, SSOP,
TSSOP, or TVSOP
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+ $#/*)'(
)#!"#$% '# (,+)")&'#!( ,+$ '0+ '+$%( #" +1&( !('$*%+!'( ('&!/&$/ 2&$$&!'3
$#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+ '+('!4 #" &.. ,&$&%+'+$(
Copyright 2005, Texas Instruments Incorporated
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SCDS188 – JANUARY 2005
ORDERING INFORMATION
PACKAGE(1)
TA
QFN − RGY
SOIC − D
−40°C
−40
C to 85
85°C
C
SSOP (QSOP) − DBQ
TSSOP − PW
TVSOP − DGV
ORDERABLE PART NUMBER
Tape and reel
TS3A5017RGYR
Tube
TS3A5017D
Tape and reel
TS3A5017DR
Tape and reel
TS3A5017DBQR
Tube
TS3A5017PW
Tape and reel
TS3A5017PWR
Tape and reel
TS3A5017DGVR
TOP-SIDE MARKING
YA017
TS3A5017
YA017
YA017
YA017
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
Absolute Minimum and Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted)
V+
VS, VD
Supply voltage range(3)
Analog voltage range(3)(4)
IK
IS, ID
Analog port diode current
VI
IIK
Digital input voltage range(3)(4)
I+
IGND
Continuous current through V+
θJA
On-state switch current
Digital input clamp current
VS, VD < 0
VS, VD = 0 to 7 V
VI < 0
MAX
−0.5
4.6
V
−0.5
4.6
V
−128
128
mA
−0.5
4.6
V
−50
UNIT
mA
−50
mA
100
Continuous current through GND
Package thermal impedance(5)
MIN
−100
mA
mA
D package
73
DB package
82
DGV package
120
DW package
108
°C/W
Tstg
Storage temperature range
−65
150
°C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade
device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified
is not implied.
(2) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(3) All voltages are with respect to ground, unless otherwise specified.
(4) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(5) The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCDS188 – JANUARY 2005
Electrical Characteristics for 3.3-V Supply(1)
V+ = 3 V to 3.6 V, TA = −40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SYMBOL
TA
V+
MIN
TYP
MAX
UNIT
Analog Switch
Analog signal
range
ON-state
resistance
ON-state
resistance match
between
channels
ON-state
resistance
flatness
S
OFF leakage
current
D
OFF leakage
current
VD, VS
0
25°C
ron
0 ≤ VS ≤ V+,
ID = −32 mA,
Switch ON,
See Figure 13
∆ron
VS = 2.1 V,
ID = −32 mA,
Switch ON,
See Figure 13
0 ≤ VS ≤ V+,
ID = −32 mA,
Switch ON,
See Figure 13
25°C
ron(flat)
VS = 1 V, VD = 3 V,
or
VS = 3 V, VD = 1 V,
Switch OFF,
See Figure 14
25°C
IS(OFF)
Switch OFF,
See Figure 14
25°C
VD = 1 V, VS = 3 V,
or
VD = 3 V, VS = 3 V,
Switch OFF,
See Figure 14
25°C
VD = 0 to 3.6 V,
VS = 3.6 V to 0,
Switch OFF,
See Figure 14
25°C
ISPWR(OFF)
ID(OFF)
IDPWR(OFF)
VS = 0 to 3.6 V,
VD = 3.6 V to 0,
Full
V+
11
3V
12
14
25°C
1
Ω
3
Full
7
9
3V
Full
Full
Full
Full
S
ON leakage
current
VS = 1 V, VD = Open,
or
VS = 3 V, VD = Open,
Switch ON,
See Figure 15
25°C
IS(ON)
D
ON leakage
current
VD = 1 V, VS = Open,
or
VD = 3 V, VS = Open,
Switch ON,
See Figure 15
25°C
ID(ON)
Ω
2
3V
Full
V
10
−0.1
3.6 V
−0.2
−1
0V
0V
0.2
1
0.05
0.1
0.2
0.5
−5
−0.1
5
0.05
−0.2
−0.1
µA
1
0.1
3.6 V
Full
µA
5
−0.2
−1
0.1
0.5
−5
−0.1
3.6 V
0.05
Ω
0.2
0.05
µA
A
0.1
3.6 V
µA
A
Full
−0.2
0.2
Full
2
5.5
V
Full
0
0.8
V
25°C
−1
Digital Control Inputs (IN1, IN2, EN)(2)
Input logic high
Input logic low
Input leakage
current
VIH
VIL
IIH, IIL
VI = 5.5 V or 0
Full
3.6 V
−1
0.05
1
1
µA
A
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
3
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SCDS188 – JANUARY 2005
Electrical Characteristics for 3.3-V Supply(1) (continued)
V+ = 3 V to 3.6 V, TA = −40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SYMBOL
TA
V+
MIN
TYP
5
MAX
UNIT
Dynamic
Turn-on time
VD = 2 V,
RL = 300 Ω,
CL = 35 pF,
See Figure 17
25°C
3.3 V
1
tON
Full
3 V to 3.6 V
1
9.5
Turn-off time
VD = 2 V,
RL = 300 Ω,
CL = 35 pF,
See Figure 17
25°C
3.3 V
0.5
tOFF
Full
3 V to 3.6 V
0.5
VGEN = 0, RGEN = 0
CL = 0.1 nF,
See Figure 22
25°C
3.3 V
5
pC
10.5
1.5
ns
3.5
4.5
ns
Charge injection
QC
S
OFF capacitance
CS(OFF)
VS = V+ or GND,
Switch OFF,
See Figure 16
25°C
3.3 V
19
pF
D
OFF capacitance
CD(OFF)
VD = V+ or GND,
Switch OFF,
See Figure 16
25°C
3.3 V
4.5
pF
S
ON capacitance
CS(ON)
VS = V+ or GND,
Switch ON,
See Figure 16
25°C
3.3 V
25
pF
D
ON capacitance
CD(ON)
VD = V+ or GND,
Switch ON,
See Figure 16
25°C
3.3 V
25
pF
CI
VI = V+ or GND,
See Figure 16
25°C
3.3 V
2
pF
BW
RL = 50 Ω,
Switch ON,
See Figure 18
25°C
3.3 V
165
MHz
OISO
RL = 50 Ω,
f = 10 MHz,
Switch OFF,
See Figure 19
25°C
3.3 V
−48
dB
Crosstalk
XTALK
RL = 50 Ω,
f = 10 MHz,
Switch ON,
See Figure 20
25°C
3.3 V
−49
dB
Crosstalk
Adjacent
XTALK(ADJ)
RL = 50 Ω,
f = 10 MHz,
Switch ON,
See Figure 21
25°C
3.3 V
−74
dB
THD
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 23
25°C
3.3 V
0.21
%
Digital input
capacitance
Bandwidth
OFF isolation
Total harmonic
distortion
Supply
25°C
Positive supply
I+
VI = V+ or GND,
Switch ON or OFF
3.6 V
current
Full
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
4
2.5
7
10
µA
A
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SCDS188 – JANUARY 2005
Electrical Characteristics for 2.5-V Supply(1)
V+ = 2.3 V to 2.7 V, TA = −40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SYMBOL
TA
V+
MIN
TYP
MAX
UNIT
Analog Switch
Analog signal
range
ON-state
resistance
ON-state
resistance match
between
channels
ON-state
resistance
flatness
S
OFF leakage
current
D
OFF leakage
current
VD, VS
0
25°C
ron
0 ≤ VS ≤ V+,
ID = −24 mA,
Switch ON,
See Figure 13
∆ron
VS = 1.6 V,
ID = −24 mA,
Switch ON,
See Figure 13
0 ≤ VS ≤ V+,
ID = −24 mA,
Switch ON,
See Figure 13
25°C
ron(flat)
VS = 0.5 V, VD = 2.2 V,
or
VS = 2.2 V, VD = 0.5 V,
Switch OFF,
See Figure 14
25°C
IS(OFF)
Switch OFF,
See Figure 14
25°C
VD = 0.5 V, VS = 2.2 V,
or
VD = 2.2 V, VS = 0.5 V,
Switch OFF,
See Figure 14
25°C
VD = 0 to 5.5 V,
VS = 5.5 V to 0,
Switch OFF,
See Figure 14
25°C
ISPWR(OFF)
ID(OFF)
IDPWR(OFF)
VS = 0 to 3.6 V,
VD = 3.6 V to 0,
Full
V+
20.5
2.3 V
22
24
25°C
1
Ω
3
Full
16
18
2.3 V
Full
Full
Full
Full
S
ON leakage
current
VS = 0.5 V, VD = Open,
or
VS = 2.2 V, VD = Open,
Switch ON,
See Figure 15
25°C
IS(ON)
D
ON leakage
current
VD = 0.5 V, VS = Open,
or
VD = 2.2 V, VS = Open,
Switch ON,
See Figure 15
25°C
ID(ON)
Ω
2
2.3 V
Full
V
20
−0.1
2.7 V
−0.2
−1
0V
0V
0.2
1
0.05
0.1
0.2
0.5
−5
−0.1
5
0.05
−0.2
−0.1
µA
1
0.1
2.7 V
Full
µA
5
−0.2
−1
0.1
0.5
−5
−0.1
2.7 V
0.05
Ω
0.2
0.05
µA
A
0.1
2.7 V
µA
A
Full
−0.2
0.2
Full
1.7
5.5
V
Full
0
0.7
V
25°C
−1
Digital Control Inputs (IN1, IN2)(2)
Input logic high
Input logic low
Input leakage
current
VIH
VIL
IIH, IIL
VI = 5.5 V or 0
Full
2.7 V
−1
0.05
1
1
µA
A
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
5
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SCDS188 – JANUARY 2005
Electrical Characteristics for 2.5-V Supply(1) (continued)
V+ = 2.3 V to 2.7 V, TA = −40°C to 85°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SYMBOL
TA
V+
MIN
TYP
1.5
5
MAX
UNIT
Dynamic
Turn-on time
VD = 1.5 V,
RL = 300 Ω,
CL = 35 pF,
See Figure 17
25°C
2.5 V
tON
Full
2.3 V to 2.7 V
Turn-off time
VD = 1.5 V,
RL = 300 Ω,
CL = 35 pF,
See Figure 17
25°C
2.5 V
0.3
tOFF
Full
2.3 V to 2.7 V
0.3
VGEN = 0, RGEN = 0
CL = 0.1 nF,
See Figure 22
25°C
2.5 V
1
8
10
2
ns
4.5
6
ns
Charge injection
QC
S
OFF capacitance
CS(OFF)
VS = V+ or GND,
Switch OFF,
See Figure 16
25°C
2.5 V
18.5
pF
D
OFF capacitance
CD(OFF)
VD = V+ or GND,
Switch OFF,
See Figure 16
25°C
2.5 V
45
pF
S
ON capacitance
CNC(ON)
VS = V+ or GND,
Switch ON,
See Figure 16
25°C
2.5 V
24
pF
D
ON capacitance
CD(ON)
VD = V+ or GND,
Switch ON,
See Figure 16
25°C
2.5 V
24
pF
CI
VI = V+ or GND,
See Figure 16
25°C
2.5 V
2
pF
BW
RL = 50 Ω,
Switch ON,
See Figure 18
25°C
2.5 V
165
MHz
OISO
RL = 50 Ω,
f = 10 MHz,
Switch OFF,
See Figure 19
25°C
2.5 V
−48
dB
Crosstalk
XTALK
RL = 50 Ω,
f = 10 MHz,
Switch ON,
See Figure 20
25°C
2.5 V
−49
dB
Crosstalk
Adjacent
XTALK(ADJ)
RL = 50 Ω,
f = 10 MHz,
Switch ON,
See Figure 21
25°C
3.3 V
−74
dB
THD
RL = 600 Ω,
CL = 50 pF,
f = 20 Hz to 20 kHz,
See Figure 23
25°C
2.5 V
0.29
%
Digital input
capacitance
Bandwidth
OFF isolation
Total harmonic
distortion
pC
Supply
25°C
Positive supply
I+
VI = V+ or GND,
Switch ON or OFF
2.7 V
current
Full
(1) The algebraic convention, whereby the most negative value is a minimum and the most positive value is a maximum
6
2.5
7
10
µA
A
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TYPICAL PERFORMANCE
12
18
TA = 25_C
16
10
14
855C
V+ = 2.5 V
8
ron (W)
ron (Ω)
12
10
8
6
255C
6
4
V+ = 3.3 V
4
–405C
2
2
0
0
1
2
VCOM (V)
3
0
0.0
4
Figure 1. ron vs VCOM
0.5
1.0
3.0
3.5
40
16
14
855C
10
8
255C
6
4
2
–405C
0
0.0
INC(ON)
ICOM(ON)
30
Leakage Current (nA)
12
ron (W)
2.5
Figure 2. ron vs VCOM (V+ = 3.3 V)
18
INO(ON)
20
ICOM(OFF)
INC(OFF)
10
INO(OFF)
0
0.5
1.0
1.5
2.0
2.5
3.0
−40
25
TA (°C)
VCOM (V)
85
Figure 4. Leakage Current vs Temperature
(V+ = 5.5 V)
Figure 3. ron vs VCOM (V+ = 5 V)
4.5
9
4.0
8
V+ = 3.3 V
3.5
7
3.0
6
2.5
tON/tOFF (ns)
Charge Injection (pC)
1.5
2.0
VCOM (V)
V+ = 2.5 V
2.0
1.5
1.0
0.5
tON
5
4
tOFF
3
2
1
0.0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VCOM (V)
Figure 5. Charge-Injection (QC) vs VCOM
0
2.0
2.5
3.0
3.5
4.0
V+ (V)
Figure 6. tON and tOFF vs Supply Voltage
7
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SCDS188 – JANUARY 2005
TYPICAL PERFORMANCE
5.0
2.0
4.5
tON
3.5
3.0
2.5
2.0
1.8
Logic Level Threshold (nA)
tON/tOFF (ns)
4.0
tOFF
1.5
1.0
0.5
1.6
1.2
25
VIL
1.0
0.8
0.6
0.4
0.2
0.0
−40
VIH
1.4
0.0
2.0 2.2
85
2.4 2.6
TA (5C)
2.8 3.0 3.2
V+ (V)
3.4 3.6
3.8 4.0
Figure 8. Logic-Level Threshold vs V+
Figure 7. tON and tOFF vs Temperature (V+ = 5 V)
0
0
−10
−20
−2
Gain (dB)
−30
Gain (dB)
−4
−6
−40
−50
−60
−8
−70
−80
−10
−12
0.1
−90
1
10
Frequency (MHz)
100
1000
−100
0.1
1
10
100
1000
Frequency (MHz)
Figure 10. OFF Isolation and Crosstalk vs
Frequency (V+ = 5 V)
Figure 9. Bandwidth (Gain vs Frequency)
(V+ = 5 V)
3.5
0.25
3.0
2.5
2.0
0.15
I+ (µA)
THD (%)
0.20
0.10
1.5
1.0
0.05
0.00
10
0.5
0.0
100
1000
Frequency (Hz)
10 K
100 K
Figure 11. Total Harmonic Distortion vs
Frequency
8
−40
25
TA (5C)
85
Figure 12. Power-Supply Current vs
Temperature (V+ = 3.6 V)
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PIN DESCRIPTION
PIN
NUMBER
NAME
1
1EN
Enable (active low)
2
IN2
Digital control pin to connect D to S
3
1S4
1S3
Analog I/O
1S2
1S1
Analog I/O
7
1D
Common
8
GND
4
5
6
DESCRIPTION
Analog I/O
Analog I/O
Ground
9
2D
Common
10
2S1
2S2
Analog I/O
2S3
2S4
Analog I/O
13
14
IN1
Digital control pin to connect D to S
15
2EN
Enable (active low)
16
V+
11
12
Analog /O
Analog I/O
Power supply
9
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SCDS188 – JANUARY 2005
PARAMETER DESCRIPTION
SYMBOL
DESCRIPTION
VD
Voltage at D
VS
Voltage at S
ron
Resistance between D and S ports when the channel is ON
∆ron
Difference of ron between channels in a specific device
ron(flat)
Difference between the maximum and minimum value of ron in a channel over the specified range of conditions
IS(OFF)
Leakage current measured at the S port, with the corresponding channel (S to D) in the OFF state
ISPWR(OFF)
Leakage current measured at the S port, under powered down mode, V+ = 0
IS(ON)
Leakage current measured at the S port, with the corresponding channel (S to D) in the ON state and the output (D) open
ID(OFF)
Leakage current measured at the D port, with the corresponding channel (D to S) in the OFF state
IDPWR(OFF)
Leakage current measured at the D port, under powered down mode, V+ = 0
ID(ON)
Leakage current measured at the D port, with the corresponding channel (D to S) in the ON state and the output (S) open
VIH
Minimum input voltage for logic high for the control input (IN, EN)
VIL
Maximum input voltage for logic low for the control input (IN, EN)
VI
Voltage at the control input (IN, EN)
IIH, IIL
Leakage current measured at the control input (IN, EN)
tON
Turn-on time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay
between the digital control (IN) signal and analog output (D or S) signal when the switch is turning ON.
tOFF
Turn-off time for the switch. This parameter is measured under the specified range of conditions and by the propagation delay
between the digital control (IN) signal and analog output (D or S) signal when the switch is turning OFF.
QC
Charge injection is a measurement of unwanted signal coupling from the control (IN) input to the analog (S or D) output. This is
measured in coulomb (C) and measured by the total charge induced due to switching of the control input.
Charge injection, QC = CL × ∆VD, CL is the load capacitance, and ∆VD is the change in analog output voltage.
CS(OFF)
CS(ON)
Capacitance at the S port when the corresponding channel (S to D) is OFF
CD(OFF)
CD(ON)
Capacitance at the D port when the corresponding channel (D to S) is OFF
CI
Capacitance of control input (IN)
OISO
OFF isolation of the switch is a measurement of OFF-state switch impedance. This is measured in dB in a specific frequency,
with the corresponding channel (S to D) in the OFF state.
XTALK
Crosstalk is a measurement of unwanted signal coupling from an ON channel to an adjacent ON channel (1S1 to 2S1). This is
measured in a specific frequency and in dB.
BW
Bandwidth of the switch. This is the frequency in which the gain of an ON channel is −3 dB below the DC gain.
THD
Total harmonic distortion describes the signal distortion caused by the analog switch. This is defined as the ratio of root mean
square (RMS) value of the second, third, and higher harmonic to the absolute magnitude of the fundamental harmonic.
I+
Static power-supply current with the control (IN) pin at V+ or GND
10
Capacitance at the S port when the corresponding channel (S to D) is ON
Capacitance at the D port when the corresponding channel (D to S) is ON
W www.ti.com
SCDS188 – JANUARY 2005
PARAMETER MEASUREMENT INFORMATION
V+
VS1 S1
D
+
VS2-S4
VD
Channel ON
S2-S4
r on +
VI
IN or EN
ID
VD * VS2*S4 or VS1
W
ID
VI = VIH or VIL
+
GND
Figure 13. ON-State Resistance (ron)
V+
VS1
+
S1
D
VS2-S4
S2-S4
VD
+
OFF-State Leakage Current
Channel OFF
VI = VIH or VIL
VS1 or VS2-S4 = 0 to V+
and
VD = V+ to 0
IN or EN
VI
+
GND
Figure 14. OFF-State Leakage Current (ID(OFF), IS(OFF), INO(OFF)
V+
VS1
+
S1
D
VS2-S4
S2-S4
VD
ON-State Leakage Current
Channel ON
VI = VIH or VIL
IN or EN
VI
+
GND
Figure 15. ON-State Leakage Current (ID(ON), IS(ON))
11
W www.ti.com
SCDS188 – JANUARY 2005
V+
VS1
Capacitance
Meter
S1
VS2-S4
VD
VBIAS
VBIAS = V+ or GND
S2-S4
VI = VIH or VIL
D
Capacitance is measured at S1,
S2-S4, D, and IN inputs during
ON and OFF conditions.
VI
IN or EN
GND
Figure 16. Capacitance (CI, CD(OFF), CD(ON), CS(OFF), CS(ON))
V+
VS1
S1
VD(3)
RL
CL
tON
300 Ω
35 pF
tOFF
300 Ω
35 pF
D
CL(2)
S2-S4
RL
VI
Logic
Input(1)
TEST
IN or EN
GND
V+
Logic
Input
(VI)
CL(2)
50%
50%
0
tON
tOFF
Switch
Output
(VS1)
90%
90%
(1) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
(2) CL includes probe and jig capacitance.
(3) See Electrical Characteristics for VD.
Figure 17. Turn-On (tON) and Turn-Off Time (tOFF)
V+
Network Analyzer
50 W
VS1
S1
D
S2-S4
Source
Signal
VD
Channel ON: S1 to D
VI = V+ or GND
Network Analyzer Setup
IN or EN
50 W
VI
+
Source Power = 0 dBm
(632-mV P-P at 50-W load)
GND
Figure 18. Bandwidth (BW)
12
DC Bias = 350 mV
W www.ti.com
SCDS188 – JANUARY 2005
V+
Network Analyzer
50 W
VS1
Channel OFF: S to D
S1
Source
Signal
50 W
VI = V+ or GND
VD
D
S2-S4
Network Analyzer Setup
IN or EN
Source Power = 0 dBm
(632-mV P-P at 50-W load)
VI
50 W
+
GND
DC Bias = 350 mV
Figure 19. OFF Isolation (OISO)
V+
Network Analyzer
50 W
Channel ON: S1 to D
VS1
Channel OFF: S2-S4 to D
S1
VD
Source
Signal
VS2-S4
50 W
VI
VI = V+ or GND
S2-S4
+
Network Analyzer Setup
50 W
IN or EN
Source Power = 0 dBm
(632-mV P-P at 50-W load)
GND
DC Bias = 350 mV
Figure 20. Crosstalk (XTALK)
V+
Network Analyzer
50 W
V1S
Source
Signal
1S1
V2S
2S1
2D
IN or EN
50 W
Channel ON: S1 to D
1D
50 W
Network Analyzer Setup
Source Power = 0 dBm
(632 mV P-P at 50 W load)
VI
+
GND
DC Bias = 350 mV
Figure 21. Adjacent Crosstalk
13
W www.ti.com
SCDS188 – JANUARY 2005
V+
RGEN
VGEN
Logic
Input
(VI)
S1
D
+
VD
VIH
OFF
ON
OFF V
IL
∆VD
VD
S2-S4
CL(1)
VI
IN or EN
Logic
Input(2)
VGEN = 0 to V+
RGEN = 0
CL = 0.1 nF
QC = CL × ∆VD
VI = VIH or VIL
GND
(1) CL includes probe and jig capacitance.
(2) All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr < 5 ns, tf < 5 ns.
Figure 22. Charge Injection (QC)
VI = VIH or VIL
fSOURCE = 20 Hz to 20 kHz
Channel ON: D to S
VSOURCE = V+ P-P
V+/2
V+
Audio Analyzer
RL
S1
10 mF
Source
Signal
D
600 W
600 W
S2-S4
IN or EN
VI
+
600 W
GND
(1) CL includes probe and jig capacitance.
Figure 23. Total Harmonic Distortion (THD)
14
10 mF
CL(1)
PACKAGE OPTION ADDENDUM
www.ti.com
30-Aug-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
TS3A5017D
ACTIVE
SOIC
D
16
TS3A5017DBQR
ACTIVE
SSOP/
QSOP
DBQ
TS3A5017DBQRE4
ACTIVE
SSOP/
QSOP
TS3A5017DE4
ACTIVE
TS3A5017DGVR
40
Lead/Ball Finish
MSL Peak Temp (3)
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
DBQ
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-2-260C-1YEAR
SOIC
D
16
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS3A5017DGVRE4
ACTIVE
TVSOP
DGV
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS3A5017DR
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS3A5017DRE4
ACTIVE
SOIC
D
16
2500 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS3A5017PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS3A5017PWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS3A5017PWR
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
TS3A5017PWRE4
ACTIVE
TSSOP
PW
16
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
40
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
0,65
14
0,10 M
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
8
14
16
20
24
28
A MAX
3,10
5,10
5,10
6,60
7,90
9,80
A MIN
2,90
4,90
4,90
6,40
7,70
9,60
DIM
4040064/F 01/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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