INTEGRATED CIRCUITS DATA SHEET TZA3015HW 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver Preliminary specification Supersedes data of 2003 Oct 06 2003 Dec 16 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW FEATURES General • A-rabitte(1): supports any bit rate from 30 Mbit/s to 3.2 Gbit/s with one single reference frequency • 4-bit parallel interface • Selectable Double Data Rate (DDR, half clock rate) or Single Data Rate (SDR) clocking scheme on parallel interface, enabling easy interfacing with FPGA devices Multiplexer • 4 : 1 multiplexing ratio • I2C-bus and pin programmable • Supports co-directional and contra-directional clocking • Six selectable reference frequency ranges • 4-stage FIFO for wide tolerance to clock skew • Transmitter, receiver and transceiver modes • Rail-to-rail parallel inputs compliant with LVPECL, Current-Mode Logic (CML) and LVDS • Clean-up loop back mode • Programmable parity checking • Line loop back mode • CML data and clock outputs. • Diagnostic loop back mode • Serial loop timing mode Demultiplexer • Single 3.3 V power supply. • 1 : 4 demultiplexing ratio Limiter • Adjustable LVDS output swing • Frame detection for SDH/SONET and Gigabit Ethernet • Limiting amplifier with typical 5 mV input sensitivity (GE) frames. • Received Signal Strength Indicator (RSSI) • Loss Of Signal (LOS) indicator with adjustable threshold I2C-bus configurable options • Differential overvoltage protection. • Programmable frequency resolution of 10 Hz • Independent receive and transmit bit rate Data and clock recovery and synthesizer • Supports any bit rate from 30 Mbit/s to 3.2 Gbit/s when using I2C-bus interface • Slice level adjustment to improve Bit Error Rate (BER) • Supports eight pre-programmed (pin selectable) bit rates: • Adjustable swing for CML serial data and clock outputs • Six reference frequency ranges • Programmable polarity of RF I/Os • Clock versus data swap for optimum connectivity – SDH/SONET rates at 155.52 Mbit/s, 622.08 Mbit/s, 2488.32 Mbit/s and 2666.06 Mbit/s (STM16/OC48 + FEC) • Swap of parallel bus for optimum connectivity • Mute function for a forced logic 0 output state – Gigabit Ethernet at 1250 Mbit/s and 3125 Mbit/s • Programmable parity – Fibre Channel at 1062.5 Mbit/s and 2125 Mbit/s. • Programmable 32-bit frame detection. • Provides stable clock signal at LOS • Frequency lock indicator for DCR • Loss Of Lock (LOL) indicator for synthesizer • ITU-T compliant jitter tolerance for Data and Clock Recovery (DCR) • ITU-T compliant jitter transfer for DCR in clean-up loop back mode • ITU-T compliant jitter generation for synthesizer. (1) A-rate is a trademark of Koninklijke Philips Electronics N.V. 2003 Dec 16 2 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW APPLICATIONS GENERAL DESCRIPTION • Any optical transmission system with line rates between 30 Mbit/s and 3.2 Gbit/s The TZA3015HW is a fully integrated optical network transceiver containing a limiter, data and clock recovery circuit, clock synthesizer, 1 : 4 demultiplexer and 4 : 1 multiplexer. • Physical interface IC in receive and transmit channels • Transponder applications The A-rate feature allows the IC to operate at any bit rate between 30 Mbit/s and 3.2 Gbit/s with one single reference frequency. • Dense wavelength division multiplexing systems • Due to DDR clocking option, the ultimate physical interface for FPGA based designs. All clock signals are generated using a fractional N synthesizer with 10 Hz resolution offering a true continuous rate operating. For full configuration flexibility the transceiver can be programmed by pin and via the I2C-bus. ORDERING INFORMATION TYPE NUMBER TZA3015HW 2003 Dec 16 PACKAGE NAME DESCRIPTION VERSION HTQFP100 plastic thermal enhanced thin quad flat package; 100 leads; body 14 × 14 × 1 mm; exposed die pad SOT638-1 3 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW BLOCK DIAGRAM CREF FIFORESET PAREVEN OVERFLOW 81 FREF0 FREF1 ENRX ENTX 93 94 42 89, 90 91 79, 80 31 LM1 LM2 TXSD TXSDQ TXSC TXSCQ ENTXSC RXSD RXSDQ 45 86, 87 64 65 CLK MUX ÷4 32 LM MUX 27 LM0 TXPARERR/ TXPARERRQ PHASE SHIFT CLOCK SYNTHESIZER ÷R 95 TXPCO/ TXPCOQ ENDDR LOL CREFQ 83 82 TXPRSCL/ TXPRSCLQ LOOP MODE SELECT 28 29 c LOOP d 5 BUF 6 PARITY CHECK AND BUS SWAP MUX 4:1 d BUF MUX c 3 DLB MUX 16 PARITY GENERATOR AND BUS SWAP PHASE DETECTOR LIM 17 DMX 1:4 RSSI RSSI LOSTH RREF LOS SCL(DR2) SDA(DR1) CS(DR0) UI VCO LPF 20 ENDDR 19 TZA3015HW LOS 14 FREQUENCY WINDOW DETECTOR 21 76 77 TXPAR/ TXPARQ 73 74 TXPD3/ TXPD3Q 71 72 TXPD2/ TXPD2Q 69 70 TXPD1/ TXPD1Q 67 68 48 49 TXPD0/ TXPD0Q 61 62 RXPD3/ RXPD3Q 59 60 RXPD2/ RXPD2Q 57 58 RXPD1/ RXPD1Q 55 56 RXPD0/ RXPD0Q 52 53 RXPC/ RXPCQ 46 47 43 RXFP/ RXFPQ RXPAR/ RXPARQ ENBA 24 23 CLEAN-UP PLL I2C-BUS 22 INTERRUPT CONTROLLER 13 25 VDD (1) VEE (2) VCCD 96 98, 99 38 37 IPUMP INWINDOW WINSIZE RXPRSCL/ RXPRSCLQ (1) Connected to pins 2, 12, 26, 33, 35, 40, 50, 84 and 100. (2) Connected to pins 4, 7, 8, 11, 36, 39, 44, 51, 54, 63, 66, 75, 78, 85 and 97. Fig.1 Block diagram. 2003 Dec 16 CLKDIR FIFO 9 10 88 TXPC/ TXPCQ 4 1, 34 VCCO 15, 18, 92 VCCA 30 INT 41 LOWSWING mgu679 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW PINNING SYMBOL VEE SYMBOL PIN die pad DESCRIPTION PIN DESCRIPTION VCCD 36 supply voltage (digital part) common ground plane WINSIZE 37 wide and narrow frequency detect window select input VCCO 1 supply voltage (clock generator) INWINDOW 38 frequency window detector output VEE 2 ground VCCD 39 supply voltage (digital part) ENTXSC 3 enable serial clock VEE 40 ground VCCD 4 digital supply voltage LOWSWING 41 enable low LVDS swing TXSD 5 serial data output FREF0 42 reference frequency select input 0 TXSDQ 6 serial data output inverted VCCD 7 supply voltage (digital part) ENBA 43 enable byte alignment 44 supply voltage (digital part) VCCD 8 supply voltage (digital part) VCCD TXSC 9 serial clock output ENDDR 45 enable DDR TXSCQ 10 serial clock output inverted RXFP 46 frame pulse output VCCD 11 supply voltage (digital part) RXFPQ 47 frame pulse output inverted 48 parity output VEE 12 ground RXPAR UI 13 user interface select input RXPARQ 49 parity output inverted RREF 14 reference resistor input VEE 50 ground 51 supply voltage (digital part) 52 parallel clock output VCCA 15 supply voltage (analog part) VCCD RXSD 16 serial data input RXPC RXSDQ 17 serial data input inverted RXPCQ 53 parallel clock output inverted 54 digital supply voltage VCCA 18 supply voltage (analog part) VCCD LOSTH 19 loss of signal threshold input RXPD0 55 parallel data output 0 RSSI 20 received signal strength indicator output RXPD0Q 56 parallel data output 0 inverted RXPD1 57 parallel data output 1 58 parallel data output 1 inverted LOS 21 loss of signal output RXPD1Q CS(DR0) 22 chip select output (data rate select input 0) RXPD2 59 parallel data output 2 RXPD2Q 60 parallel data output 2 inverted SDA(DR1) 23 I2C-bus serial data input and output (data rate select input 1) RXPD3 61 parallel data output 3 SCL(DR2) 24 I2C-bus serial clock input (data rate select input 2) RXPD3Q 62 parallel data output 3 inverted VCCD 63 supply voltage (digital part) TXPC 64 parallel clock input TXPCQ 65 parallel clock input inverted VCCD 66 supply voltage (digital part) TXPD0 67 parallel data input 0 TXPD0Q 68 parallel data input 0 inverted VDD 25 supply voltage (digital) VEE 26 ground LM0 27 loop mode select input 0 LM1 28 loop mode select input 1 LM2 29 loop mode select input 2 INT 30 interrupt output ENRX 31 enable receiver ENTX 32 enable transmitter VEE 33 ground VCCO 34 supply voltage (clock generator) VEE 35 ground 2003 Dec 16 5 TXPD1 69 parallel data input 1 TXPD1Q 70 parallel data input 1 inverted TXPD2 71 parallel data input 2 TXPD2Q 72 parallel data input 2 inverted TXPD3 73 parallel data input 3 TXPD3Q 74 parallel data input 3 inverted Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver SYMBOL PIN TZA3015HW DESCRIPTION SYMBOL PIN DESCRIPTION VCCD 75 supply voltage (digital part) TXPRSCL 89 prescaler synthesizer output TXPAR 76 parity input TXPRSCLQ 90 TXPARQ 77 parity input inverted prescaler synthesizer output inverted VCCD 78 supply voltage (digital part) LOL 91 loss of lock output TXPCO 79 transmitter parallel clock output VCCA 92 supply voltage (analog part) TXPCOQ 80 transmitter parallel clock output inverted CREF 93 reference clock input CREFQ 94 reference clock input inverted FREF1 95 reference frequency select input 1 IPUMP 96 clean-up PLL charge pump output VCCD 97 supply voltage (digital part) RXPRSCL 98 prescaler DCR output RXPRSCLQ 99 prescaler DCR output inverted VEE 100 ground PAREVEN 81 parity select input (odd or even) OVERFLOW 82 FIFO overflow alarm output FIFORESET 83 FIFO reset input VEE 84 ground VCCD 85 supply voltage (digital part) TXPARERR 86 parity error output TXPARERRQ 87 parity error output inverted CLKDIR 2003 Dec 16 88 selection input between co- and contra-directional clocking 6 Philips Semiconductors Preliminary specification 76 TXPAR 78 VCCD 77 TXPARQ 79 TXPCO 81 PAREVEN 80 TXPCOQ 82 OVERFLOW 83 FIFORESET 85 VCCD 84 VEE 86 TXPARERR 87 TXPARERRQ 88 CLKDIR 89 TXPRSCL TZA3015HW 90 TXPRSCLQ 92 VCCA 91 LOL 93 CREF 94 CREFQ 95 FREF1 96 IPUMP 97 VCCD 98 RXPRSCL 100 VEE handbook, full pagewidth 99 RXPRSCLQ 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver VCCO 1 75 VCCD VEE 2 74 TXPD3Q ENTXSC 3 73 TXPD3 VCCD 4 72 TXPD2Q TXSD 5 71 TXPD2 TXSDQ 6 70 TXPD1Q VCCD 7 69 TXPD1 VCCD 8 68 TXPD0Q TXSC 9 67 TXPD0 TXSCQ 10 66 VCCD 65 TXPCQ VCCD 11 VEE 12 64 TXPC TZA3015HW UI 13 63 VCCD RREF 14 62 RXPD3Q VCCA 15 61 RXPD3 RXSD 16 60 RXPD2Q RXSDQ 17 59 RXPD2 VCCA 18 58 RXPD1Q LOSTH 19 57 RXPD1 RSSI 20 56 RXPD0Q Fig.2 Pin configuration. 2003 Dec 16 7 VEE 50 RXPAR 48 RXPARQ 49 RXFPQ 47 RXFP 46 ENDDR 45 ENBA 43 VCCD 44 FREF0 42 LOWSWING 41 VCCD 39 VEE 40 INWINDOW 38 VCCD 36 WINSIZE 37 VCCO 34 VEE 35 VEE 33 ENTX 32 51 VCCD ENRX 31 52 RXPC VDD 25 INT 30 SCL(DR2) 24 LM2 29 54 VCCD 53 RXPCQ LM1 28 SDA(DR1) 23 LM0 27 55 RXPD0 CS(DR0) 22 VEE 26 LOS 21 MGU680 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Some functions of the TZA3015HW can be controlled both using pre-program mode and via the I2C-bus. In these cases, an extra I2C-bus bit called I2C<pinname> is available to set the programming precedence to pre-programmed or I2C-bus bit (default is selection by pre-programmed). FUNCTIONAL DESCRIPTION The TZA3015HW contains the following main blocks: • General part: configuration via I2C-bus mode or pre-programmed mode • Receiver part: limiting amplifier, data and clock recovery and demultiplexer PRE-PROGRAMMED MODE • Transmitter part: clock synthesizer and multiplexer. The TZA3015HW is primarily intended to be programmed via the I2C-bus. If no I2C-bus control is present in the application, the TZA3015HW can be used in the pre-programmed mode (pin UI = LOW), with reduced functionality. The TZA3015HW functions that are accessible in the pre-programmed mode and their associated pins are: • All pre-programmed modes are supported by one single reference frequency General CONFIGURATION The IC features two types of user interface: I2C-bus or direct pin programming of eight predefined modes. The mode selection is set by pin UI. The I2C-bus mode is operational and A-rate functionality is enabled if pin UI is left open-circuit or connected to VCC (see Table 1). If pin UI is connected to VEE, the eight pre-programmed modes can be selected with pins CS(DR0), SDA(DR1) and SCL(DR2). Table 1 • The redefined pins DR0 to DR2 act as standard CMOS inputs that select any of the desired data rates; see Table 3 • Transceiver mode (transceiver, transmitter, receiver, off) (ENRX and ENTX) Truth table for pin UI UI MODE LOW pre-programmed HIGH I2C-bus • Enable serial clock output (ENTXSC) PIN 22 PIN 23 PIN 24 DR0 DR1 DR2 • Loss of signal threshold setting (LOSTH) CS SDA SCL • Select loop mode (LM0 to LM2) • Automatic byte alignment for SDH/SONET or Gigabit Ethernet (ENBA) I2C-BUS MODE • Frame detection for SDH/SONET or Gigabit Ethernet In I2C-bus mode the IC can be configured by using pins SDA and SCL. Pin CS has to be HIGH during the I2C-bus read or write actions. When pin CS is made LOW, the programmed configuration remains active, but signals SDA and SCL are ignored. In this way, all ICs in the application with the same I2C-bus address (e.g. other TZA3015HWs) are individually accessible. The I2C-bus • Even parity generation (PAREVEN) • In window detection (INWINDOW) • Sizeable frequency window: 1000 or 0 ppm (WINSIZE) • Temperature alarm (INT, open drain) • Co-directional or contra-directional clocking scheme (CLKDIR) address is given in Table 2. • Enable DDR for both receiver and transmitter (ENDDR) Table 2 Device address of the TZA3015HW • CML serial RF outputs with typical 300 mV (p-p) single-ended signal (DC-coupled load) DEVICE ADDRESS BITS R/W A6 A5 A4 A3 A2 A1 A0 1 0 1 0 1 0 0 • Loss of lock detection (LOL) • FIFO overflow indication (OVERFLOW) X • FIFO reset (FIFORESET) • Supported reference frequencies: 19.44, 38.88, 155.52 and 622.08 MHz. After power-up, the TZA3015HW initiates a Power-On Reset (POR) sequence to restore the default settings of the I2C-bus registers, regardless of the user interface. See Table 21 for the defaults and a detailed list of all I2C-bus registers and the meaning of their contents. 2003 Dec 16 8 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver Table 3 TZA3015HW Truth table for pins DR2 to DR0 (pin UI = VEE) PROTOCOL BIT RATE (Mbit/s) DR2 DR1 DR0 LOW LOW LOW STM1/OC3 155.52 LOW LOW HIGH STM4/OC12 622.08 LOW HIGH LOW STM16/OC48 2488.32 handbook, halfpage VCCA IN 50 Ω LOW HIGH HIGH STM16 + FEC 2666.06 HIGH LOW LOW GE 50 Ω 1250.00 HIGH LOW HIGH 10GE HIGH HIGH LOW Fibre Channel 1062.50 HIGH HIGH HIGH Fibre Channel 2125.00 INQ 3125.00 VEE MDB385 Fig.3 Limiter input termination configuration. Receiver LIMITING AMPLIFIER The TZA3015HW contains a limiting amplifier (see Fig.3). Received Signal Strength Indicator (RSSI) To achieve optimum receiver sensitivity for any bit rate, the bandwidth of the amplifier is automatically scaled with the bit rate. Wideband noise of the optical front-end (photo detector and transimpedance amplifier) is thus reduced for lower bit rates. When using the I2C-bus, the bandwidth of the amplifier can be set independently of the bit rate with bits AMP[2:0] in register LIMCON (D3h). The signal strength at the input is measured with a logarithmic detector. The logarithmic detector converts the input signal amplitude into a voltage which can be measured at pin RSSI. The RSSI reading has a dynamic range of 40 dB with a sensitivity (SRSSI) of 17 mV/dB (typical) for a Vi(p-p) range of 5 to 500 mV (see Fig.4). VRSSI can be calculated using the following formula: The highest bandwidth is selected as default at power-up. V i(p-p) V RSSI = V RSSI(32mV) + S RSSI × 20log ----------------32 mV where: VRSSI(32mV) = 680 mV (typical). MCE412 handbook, full pagewidth 1.2 VRSSI (V) SRSSI 0.9 0.68 0.6 0.3 0 5 10 32 102 300 500 Vi(p-p) (mV) Fig.4 VRSSI as a function of Vi(p-p). 2003 Dec 16 9 103 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Loss Of Signal (LOS) indicator Besides the analog RSSI output, a digital LOS indication is present on the TZA3015HW. The RSSI level is internally compared with a LOS threshold, which can be set by connecting an external resistor to pin LOSTH or by means of an internal DAC which is accessible via the I2C-bus. VCCA RSSI RSSI Bit I2CLOSTH of register LIMLOSCON (D1h) enables the 8-bit DAC, of which the value needs to be programmed into register LIMLOSTH (D0h). The threshold level is adjustable in 256 steps from 0 to 1.2 V. LOS LOS compare 1.2 V Vref If the received signal strength is below the threshold value, pin LOS will be HIGH. A default hysteresis of 3 dB is applied in the comparator. The hysteresis can be set with bits HTLC[2:0] in register LIMLOSCON (D1h). The programmable range is 0 to 7 dB. VEE RREF I R2 ground The polarity of the LOS output can be inverted by bit LOSPOL of register LIMLOSCON (D1h) to provide more flexibility in the application. MGU681 Fig.5 LOSTH reference setting by external resistor If the built-in DAC is not used, the reference voltage level to pin LOSTH can be set by connecting an external resistor (R2) between pin LOSTH and ground. VLOSTH is determined by the resistor ratio between R2 and R1 (see Fig.5). For resistor R1 a value of 10 to 20 kΩ is recommended, yielding a current of 120 to 60 µA through R1. Setting the LOSTH reference level by external resistors. Slice level adjustment Due to asymmetrical noise in some optical transmission systems, a pre-detection signal-to-noise ratio improvement can be achieved by adding a DC offset to the input signal. This is done by the slice level circuit in the TZA3015HW. The required offset depends on the photo detector characteristics in the optical front-end and the amplitude of the received signal. The slice level is adjustable between −50 and +50 mV in 512 steps of 0.2 mV. R2 VLOSTH = ------- × V ref R1 Vref represents a temperature stabilized and accurate reference voltage of 1.2 V. The minimum threshold level corresponds to 0 V and the maximum to 1.2 V. Hence, the value of R2 may not be higher than R1. The accuracy of VLOSTH depends mainly on the matching of the two external resistors. Bit SLEN of register LIMLOSCON (D1h) enables the slice function. The slice level is set by sign and magnitude convention. The polarity sign is set by bit SLSGN in register LIMLOSCON (D1h). The magnitude is set by an 8-bit DAC, accessible via register LIMSL (D2h), from 0 to 50 mV in 256 steps. Apart from using resistors (R1 and R2) to set the LOS threshold, an accurate external voltage source may also be used. The introduced offset is not present on input pins RXSD(Q), in order not to affect the logarithmic RSSI detector, which would detect the offset as a valid input signal. If no resistor is connected or an external voltage higher than 2/3 × VCC is applied to pin LOSTH, the LOS detection circuit (including the RSSI reading) is automatically switched off to reduce power dissipation. This ‘auto power off’ function only works in the pre-programmed mode. I2C-bus mode allows flexible configuration. 2003 Dec 16 R1 10 kΩ LOSTH 10 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW and takes over control if the VCO frequency drifts outside the predefined frequency window. This might occur during a ‘loss of signal’ situation. Due to the FWD, the VCO frequency is always close to the required bit rate, enabling rapid phase acquisition when the lost input signal returns. DATA AND CLOCK RECOVERY (DCR) The TZA3015HW recovers the clock and data contents from the incoming bit stream; see Fig.6. The DCR uses a combined frequency and phase locking scheme, providing reliable and quick data acquisition on any bit rate between 30 Mbit/s and 3.2 Gbit/s. Due to the loose coupling of 1000 ppm, the reference frequency does not need to be highly accurate or stable. Any crystal-based oscillator that generates a reasonably accurate frequency (e.g. 100 ppm) will do. This only holds if the TZA3015HW is used as a receiver since the synthesizer of the transmitter uses the same reference clock. The transmitter does need a very accurate reference frequency. At power-up, coarse adjustment of the free running Voltage Controlled Oscillator (VCO) frequency is required. This is achieved by the Frequency Window Detector (FWD) circuit. The FWD is a conventional frequency locked PLL. The FWD checks the VCO frequency, which has to be within a 1000 ppm window around the required frequency. The FWD then compares the divided VCO frequency, also available on pins RXPRSCL(Q), with the reference frequency on pins CREF(Q), usually 19.44 MHz. If the VCO frequency is outside this window, the FWD disables the Data Phase Detector (DPD) and forces the VCO to a frequency within the window. As soon as the ‘in window’ condition occurs, which is visible on pin INWINDOW, the DPD is enabled and will lock on the incoming bit stream. Since the VCO frequency is very close to the expected bit rate, the phase acquisition will be almost instantaneous, resulting in quick phase lock to the incoming data stream. Fractional N synthesizer in the DCR The DCR section contains a fractional N synthesizer as frequency acquisition aid for the A-rate functionality. This allows the DCR to synchronize on incoming data, regardless of the received bit rate. Any combination of bit rate and reference frequency is possible, due to the 22 bits fractional N synthesizer, allowing approximately 10 Hz frequency resolution. The LSB (bit K0) should be set to logic 1 to avoid limit cycles (cycles of less than maximum length). This leaves 21 bits (bits K[21:1]), available for free programming. Although the VCO is now locked to the incoming bit stream, the FWD is still supervising the VCO frequency handbook, full pagewidth recovered data from limiting amplifier and DLB MUX to demultiplexer recovered clock DATA PHASE DETECTOR up down OCTAVE DIVIDER CHARGE PUMP ÷M VOLTAGE CONTROLLED OSCILLATOR LOOP FILTER + MAIN Frac DIVIDER N, K ÷N REFERENCE DIVIDER divided CREF(Q) up FREQUENCY WINDOW DETECTOR down CHARGE PUMP RXPRSCL(Q) PRESCALER BUFFER MGU683 INWINDOW WINSIZE Fig.6 Functional diagram of data and clock recovery. 2003 Dec 16 11 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW DCR programming Table 5 Programming the DCR involves four dividers: Most-common optical transmission protocols PROTOCOL • Reference divider R BIT RATE (Mbit/s) OCTAVE • Main divider N 10GE 3125.00 0 • Fractional divider K 2xHDTV 2970.00 0 • Octave divider M. STM16/OC48 + FEC 2666.06 0 STM16/OC48 2488.32 0 DV-6000 2380.00 0 The first step is to determine in which octave the desired bit rate fits, see Fig.7 and Tables 4 and 5. Figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the TZA3015HW. Table 5 lists the most commonly used standards together with the associated line rates. Table 4 clarifies the octave definitions. This yields the value for the octave divider M. The value for R is determined by the reference frequency and the received bit rate (see Section “Reference clock programming”). handbook, 6halfpage 5 28.125 56.25 4 112.5 3 225 2 450 1 900 0 1800 3200 Mbits/s MGU316 Fig.7 Table 4 Commonly used line rates and allocation of octaves along a logarithmic bit rate scale. Fibre Channel 2125.00 0 HDTV 1485.00 1 D-1 video 1380.00 1 DV-6010 1300.00 1 Gigabit Ethernet 1250.00 1 Fibre Channel 1062.50 1 OptiConnect 1062.50 1 ISC 1062.50 1 STM4/OC12 622.08 2 DV-6400 595.00 2 Fibre Channel 425.00 3 OptiConnect 265.63 3 Fibre Channel 212.50 4 ESCON/SBCON 200.00 4 STM1/OC3 155.52 4 FDDI 125.00 4 Fast Ethernet 125.00 4 Fibre Channel 106.25 5 OC1 51.84 6 The values for N and K are derived from the division ratio (n.k). The division ratio (n.k) can be calculated with the following formula: Octave definition bit rate × M × R n.k = ---------------------------------------f ref OCTAVE M LOWEST BIT RATE (Mbit/s) HIGHEST BIT RATE (Mbit/s) 0 1 1800 3200 1 2 900 1800 2 4 450 900 k = fractional part of the division ratio where: n = integer part of the division ratio 3 8 225 450 bit rate = bit rate at serial input in Mbit/s 4 16 112.5 225 M = octave divider M 5 32 56.25 112.5 R = reference divider R 6 64 28.125 56.25 fref = reference frequency in MHz. 2003 Dec 16 12 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver handbook, full pagewidth TZA3015HW CALCULATE N and K n.k = bit rate × M × R fref n is integer part k is fractional part yes k=0? no RXNILFRAC = 1 RXNILFRAC = 0 0.25 < k < 0.75 no yes no k ≤ 0.25 ? yes k ≥ 0.75 ? no yes k = k + 0.5 N=2×n N=2×n N=2×n−1 k = k − 0.5 N=2×n+1 j = 21 k=k×2 k≥1? no yes Kj = 1 Kj = 0 decimal to binary conversion of fractional part k=k−1 j=j−1 j=0? no yes K0 = 1 Write Kj into registers C3h, C4h, C5h or E3h, E4h, E5h Convert N to binary and write into registers C1h, C2h or E1h, E2h END MCE413 Fig.8 Flowchart for calculating N and K. 2003 Dec 16 13 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Having calculated the division factor (n.k), the values for N and K can be calculated according to the flow depicted in the flowchart of Fig.8. The value of the octave divider M is programmed by bits RXDIV_M[2:0] in register RXOCTDIV (C0h). The value for the main divider N is programmed by bits RXN[8:0] in registers RXMAINDIV1 (C1h) and RXMAINDIV0 (C2h). The value for the fractional divider K is programmed by bits RXK[21:0] in registers RXFRACN2 to RXFRACN0 (C3h to C5h). Bit RXNILFRAC in register RXFRACN2 (C3h) must be set depending on whether there is a fractional part or not. Example 1: An SDH or SONET link has a bit rate of 2488.32 Mbit/s (STM16/OC48) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 77.76 MHz. This means that the reference division R needs to be 4. The values of n and k can be calculated from the flowchart: bit rate × M × R 2488.32 Mbits × 1 × 4 n.k = ---------------------------------------- = --------------------------------------------------------- = 128 f ref 77.76 MHz Since k = 0 in this example, no fractional functionality is required, bit RXNILFRAC (register C3h), should be logic 1. N = 2 × n and no correction is required. Consequently the appropriate values are: R = 4 (register A1h), M = 1 (register C0h) and N = 256 (registers C1h and C2h). Example 2: An SDH STM16 or SONET OC48 link with FEC has a bit rate of 2666.057143 Mbit/s (15/14 × 2488.32 Mbit/s) and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 38.88 MHz. This means that the reference division R needs to be 2. The values of n and k can be bit rate × M × R 2666.05714283 Mbits × 1 × 2 calculated from the flowchart: n.k = ---------------------------------------- = ----------------------------------------------------------------------------- = 137.1428571 f ref 38.88 MHz This means that n = 137, k = 0.1428571 and bit RXNILFRAC (register C3h) should be logic 0. Since k < 0.25, k is corrected to 0.6428571, while the corrected N becomes N = 273. Consequently the appropriate values are: R = 2 (register A1h), M = 1 (register C0h), N = 273 (registers C1h and C2h) and K = 10 1001 0010 0100 1001 0011 (registers C3h to C5h). The FEC bit rate is usually quoted to be 2666.06 Mbit/s. Due to round off errors, this leads to a slightly different value for k than in the example. Example 3: A Fibre Channel link has a bit rate of 1062.50 Mbit/s and consequently fits in octave number 1, so M = 2. Suppose the reference frequency provided at pins CREF(Q) is 19.44 MHz. This means that the reference division R needs to be 1. The values of n and k can be calculated from the flowchart: bit rate × M × R 1062.50 Mbits × 2 × 1 n.k = ---------------------------------------- = --------------------------------------------------------- = 109.3106996 f ref 19.44 MHz This means that n = 109, k = 0.3107 and bit RXNILFRAC should be logic 0 (register C3h). Since k is between 0.25 and 0.75, k does not need to be corrected and N = 2 × n = 218. Consequently the appropriate values are: R = 1 (register A1h), M = 2 (register C0h) and N = 218 (registers C1h and C2h). K = 01 0011 1110 0010 1000 0001 (registers C3h to C5h). Example 4: A non standard transmission link has a bit rate of 3012 Mbit/s and consequently fits in octave number 0, so M = 1. Suppose the reference frequency provided at pins CREF(Q) is 20.50 MHz. This means that the reference division R needs to be 1. The values of n and k can be calculated from the flowchart: 3012 Mbits × 1 × 1 bit rate × M × R n.k = ---------------------------------------- = ------------------------------------------------ = 146.9268293 20.50 MHz f ref This means that n = 146, k = 0.9268293 and bit RXNILFRAC should be logic 0 (register C3h). Since k is larger than 0.75, k needs to be corrected to 0.4268293 and N = 2 × n + 1 = 293. Consequently the appropriate values are: R = 1 (register A1h), M = 1 (register C0h) and N = 293 (registers C1h and C2h). K = 01 1011 0101 0001 0010 1011 (registers C3h to C5h). If the I2C-bus is not used, the DCR can be set up for the eight pre-programmed bit rates by pins DR0 to DR2 with an applied reference frequency of 19.44 MHz (see Table 3). 2003 Dec 16 14 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Reference clock programming Reference input The reference clock, connected to pins CREF(Q), is used for both the DCR frequency window detector and the transmitter synthesizer. The reference clock is divided by divider R. Pre-programmed operating in an SDH/SONET application assumes the use of a reference clock with a frequency that is a multiple (R) of 19.44 MHz. For other applications, any reference frequency between 18 and 21 MHz may be used. If a reference frequency is selected, any bit rate between 30 Mbit/s and 3.2 Gbit/s is supported. For optimum jitter performance and Power Supply Rejection Ratio (PSRR), the sensitive reference input should be driven differentially (see Fig.9). If the reference frequency source (fref) is single-ended, the unused CREF or CREFQ input should be terminated with an impedance which matches the source impedance Rsource. The PSRR can be improved by AC coupling the reference frequency source to inputs CREF and CREFQ. Any low frequency noise injected from the fref power supply will be attenuated by the resulting high-pass filter. The low cut-off frequency of the AC coupling must be lower than the reference frequency, otherwise the reference signal will be attenuated and the signal to noise ratio will be reduced. The value of coupling capacitor C is calculated using the 1 formula: C > ----------------------------------2πR source f ref The division ratio and reference frequency can be programmed by the bits FREFI2C[2:0] of register REFDIV (A1h) or by pins FREF0 and FREF1. Internally, the reference frequency is always divided to the lowest frequency range between 18 and 21 MHz and for SDH/SONET applications to 19.44 MHz. This is done by divider R which is set by the described pins and bits. In the pre-programmed mode (Table 6) four ranges of clock frequencies can be used by programming R through pins FREF0 and FREF1. In I2C-bus mode (Table 7) two additional ranges of clock frequencies can be used by programming R through bits FREFI2C[2:0]. Table 6 VCCD handbook, halfpage Truth table for reference divider R in pre-programmed mode 50 Ω 50 Ω 43 CREF REFERENCE FREQUENCY PIN DIVISION FACTOR SDH/SONET R FREF1 FREF0 (MHz) HIGH 1 HIGH LOW 2 38.88 36 to 42 LOW HIGH 8 155.52 144 to 168 LOW LOW 32 622.08 576 to 672 Table 7 FREF I2C1 FREF I2C0 REFERENCE FREQUENCY RANGE (MHz) 0 0 0 1 18 to 21 0 0 1 2 36 to 42 0 1 0 4 72 to 84 0 1 1 8 144 to 168 1 0 0 16 288 to 336 1 0 1 32 576 to 672 2003 Dec 16 C Rsource fref 18 to 21 DIVISION FACTOR R C Rsource on-chip Truth table for reference divider R in I2C-bus mode BIT FREF I2C2 19.44 42 CREFQ RANGE (MHz) HIGH VCC Fig.9 off-chip MDB060 Reference input with single-ended clock source. Prescaler outputs The prescaler output RXPRSCL(Q) is the VCO frequency of the DCR divided by the main division factor N. It can be used as an accurate reference for another PLL, since it corresponds to the recovered data rate. If needed, the polarity of the prescaler outputs can be inverted by bit RXPRSCLINV of register DDR&RXPRSCL (D5h). If no prescaler information is desired, the output can be disabled by bit RXPRSCLEN of the same register. Apart 15 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW INWINDOW output from these settings, the signal amplitude can be set. This parameter follows the settings of the LVDS outputs. For programming details, see Section “LVDS outputs”. The status of the FWD circuit is reflected in the state of pin INWINDOW; HIGH for an ‘in window’ situation and LOW whenever the VCO is outside the defined frequency window. Due to the fact that the device enters the frequency acquisition mode when out of window is detected, the INWINDOW pin will have an intermittent value when the input signal is not within the defined window boundary. FWD programming The default width of the window for frequency acquisition is 1000 ppm around the required bit rate. This window size can be changed between 4000 and 250 ppm by bits WINSIZE[2:0] of register DCRCON (C6h). This allows for loose or tight coupling of the VCO to the applied reference clock. Another feature is to define a window width of 0 ppm, by means of pin WINSIZE, see Table 8. This effectively removes the dead zone from the FWD, rendering the FWD into a classical PLL. DEMULTIPLEXER The demultiplexer converts the serial input bit stream to a parallel format. The output data is available on a 4-bit LVDS-bus, thus reducing the data frequency by a factor four. Apart from the de-serializing function, the demultiplexer comprises a parity calculator and a frame header detection circuit. The VCO will be directly locked to the reference signal instead of the incoming bit stream. Apart from pin WINSIZE, this mode can be invoked by bits I2CWINSIZE and WINSIZE of register DCRCON(C6h). Table 8 The calculated parity (even) is available at output pins RXPAR(Q), whereas occurrence of the frame header pattern in the data stream results in a one clock cycle (parallel clock output) wide pulse on output pins RXFP(Q). Truth table for pin WINSIZE WINSIZE FREQUENCY WINDOW (ppm) LOW 0 HIGH 1000 Accurate clock generation during loss of signal If pin ENBA is HIGH, automatic byte (word) alignment takes place, formatting the parallel output to logical nibbles. Apart from pin ENBA, this mode can be invoked by bits I2CENBA and ENBA of register DMXCON (B8h). A zero window size is especially interesting in the absence of input data, since the frequency of the ‘recovered clock’ will be equal to the programmed line clock rate. To support most commonly used transmission protocols, the frame header pattern can be programmed to any 32-bit pattern (see Section “Frame detection”). Bit AUTOWIN of register DCRCON (C6h) (see Table 9) makes the window size dependent on the LOS status of the limiter. If the optical input signal is lost, the FWD automatically selects the 0 ppm window size; i.e. a direct lock to the reference frequency. This results in a stable and defined output clock during LOS situations, while automatically reverting back to normal DCR operating when the input signal returns. If required, the demultiplexer output can be forced into a fixed logic state by bit DMXMUTE of register DMXCON (B8h). The highest supported parallel bus speed is 800 Mbit/s. Frame detection Byte alignment is enabled if the enable byte alignment input (pin ENBA) is forced HIGH. Whenever a 32-bit sequence matches the programmed header pattern, the incoming data is formatted into logical bytes (being output as nibbles) and a frame pulse is generated on differential output pins RXFP(Q). Any header pattern can be programmed through registers HEADER3 to HEADER0 (B0h to B3h). It is possible to enter a ‘don’t care’ for any bit position, e.g. to program a header pattern that is much shorter than 32 bits or to program a pattern with a gap in it. The accuracy of the reference frequency needs to be better than 20 ppm if the application has to comply with ITU-T recommendations. Table 9 Truth table for bit AUTOWIN AUTOWIN FREQUENCY WINDOW 0 FWD user defined 1 FWD dependent on LOS 2003 Dec 16 16 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW MSB HEADER handbook, full pagewidth LSB HEADER bit 0 bit 31 HEADER3 0 0 0 1 0 1 1 1 0 1 1 0 0 0 1 0 HEADER0 HEADERX3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 HEADERX0 X 0 0 1 0 X 1 1 0 1 1 0 0 0 X X received data data stream MGU548 Fig.10 Example of programming the frame pattern (the symbol ‘X’ represents a don’t care). For this, it is necessary to program registers HEADERX3 to HEADERX0 (B4h to B7h). Programming a logic 1 into the HEADERX register will turn the corresponding bit in the HEADER register into a don’t care bit, in this way the HEADER register is masked. An example of programming the framing pattern is shown in Fig.10. boundary detection is enabled on the rising edge of ENBA and remains enabled while ENBA is HIGH. Boundaries are recognized on receipt of the second A2 byte and RXFP goes HIGH for one RXPC clock cycle. The four most significant bits of the first A2 byte in the frame header are the first bits that appear on the outgoing data bus (RXPD0 to RXPD3) with the correct alignment. The default frame header pattern is F6F62828h, corresponding to the middle section of the standard SDH/SONET frame header (the last two A1 bytes plus the first two A2 bytes). When interfacing with a section terminating device, ENBA must remain HIGH for a full frame after the initial frame pulse. This is to allow the section terminating device to verify internally that frame and byte alignment are correct (see Fig.12). Byte boundary detection is disabled on the first RXFP pulse after ENBA has gone LOW. If signal ENBA is LOW, no active alignment takes place. However, if the framing pattern happens to occur in the formatted data, a frame pulse will continue to be output on pins RXFP(Q). Figure 13 shows frame and byte boundary detection activated on the rising edge of ENBA and deactivated by the first RXFP pulse after ENBA has gone LOW. Receiver framing in SDH/SONET applications Figure 11 shows a typical SDH/SONET re-frame sequence involving byte alignment. Frame and byte 2003 Dec 16 17 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth serial clock ENBA serial data A1 A1 A1 A2 RXPD0 to RXPD3 A2 A2, bits 0-3 valid data invalid data RXPC RXFP MGU342 Fig.11 Frame and byte detection in SDH/SONET application. handbook, halfpage boundary detection enabled boundary detection enabled handbook, halfpage ENBA ENBA RXFP RXFP MCE414 MCE415 Fig.12 ENBA operating time with section terminating device. Fig.13 Alternate ENBA timing. Receiver framing in other applications Parity generation In other applications frame headers may be used that are shorter than 32 bits, e.g. 10 bits for Gigabit Ethernet. The position of the frame header in the header register can be chosen freely, but determines the boundary of the parallel data on pins RXPD0(Q) to RXPD3(Q). After alignment, the header bits that are programmed by bits H12 to H15 of register HEADER1 (B2h), appear at the RXPD(Q) outputs. A frame pulse appears at output RXFP(Q) at the same time. Outputs RXPAR(Q) provide the even parity of the nibble that is currently available on the parallel bus. With bit RXPARINV of register RXMFOUTC0 (D4h), the parity can be made odd. If no parity check is required, bit RXPAREN of register RXMFOUTC0 (D4h) can be programmed to disable this output, to reduce power dissipation. 2003 Dec 16 18 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Transmitter Because of the 22 bits fractional N capability, any combination of bit rate (30 Mbit/s to 3.2 Gbit/s) and reference frequency between 18 and 672 MHz is possible. The LSB (bit k0) of the fractional divider, should be set to logic 1 to avoid limit cycles. These are cycles of less than maximum length, which generate spurs in the frequency spectrum. This leaves bits k[21:1] available for programming the fraction, allowing approximately 10 Hz of frequency resolution without altering the reference frequency. CLOCK SYNTHESIZER The transmitter frequency can be set independently of the receiver frequency. For this a clock synthesizer is provided that drives the multiplexer. Just like the DCR the clock synthesizer is built around a fractional N synthesizer offering A-rate functionality for the transmit path. The clock synthesizer consists of a VCO, several dividers, a phase frequency detector, an integrated loop filter, a lock detection circuit and a prescaler output buffer (see Fig.14). To meet most transmission standards, the reference frequency should be very accurate. In order to be able to synthesize a clean RF clock that is compliant with the most stringent jitter generation requirements, it should also be very clean in terms of phase noise. The internal VCO is phase-locked to the reference clock signal provided at pins CREF(Q). This frequency is internally scaled down (if necessary) to a frequency in the range of 18 to 21 MHz by divider R. handbook, full pagewidth LOL OCTAVE DIVIDER up divided CREF(Q) PHASE FREQUENCY DETECTOR down CHARGE PUMP AND LOOP FILTER VCO ÷M to LM MUX and multiplexer MAIN DIVIDER N, K ÷N TXPRSCL(Q) MGU682 Fig.14 Schematic diagram of the clock synthesizer. 2003 Dec 16 19 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Parallel bus clocking schemes All parts of the PLL are internal; no external components are required. This allows for easy application. The TZA3015HW supports both co-directional and contra-directional clocking schemes for the parallel data bus. The clocking application can be selected by pin CLKDIR or by the bit CLKDIR of register MUXCON0 (F1h). Co-directional clocking is default. Programming the clock synthesizer involves four dividers: • Reference divider R • Main divider N • Fractional divider K • Octave divider M. Table 10 Truth table for clocking scheme PIN CLKDIR BIT CLKDIR This is essentially the same as for the DCR. The first step is to determine in which octave the desired bit rate fits, see Tables 4 and 5 and Fig.7. Figure 7 shows the position of the most commonly used line rates in relation to the defined octaves of the TZA3015HW. Table 5 clarifies the octave definitions; this yields the value for the octave divider M. The value for R is determined by the reference frequency and the received bit rate (see Section “Reference clock programming”). LOW 0 contra-directional clocking HIGH 1 co-directional clocking In the co-directional clocking mode, the parallel clock signal is applied to pins TXPC(Q). The parallel clock signal is generated in the data processing device (e.g. a framer). The co-directional application is depicted in Fig.15. The data processing device may be clocked by an external crystal or by the parallel clock output TXPCO(Q) of the TZA3015HW. This clock output is internally derived from the synthesizer. If the parallel clock output TXPCO(Q) is not required, it can be disabled in order to save dissipation. This is done by programming bit TXPCOEN of register TXMFOUTC (F2h). Prescaler output The prescaler output TXPRSCL(Q) is the VCO frequency of the synthesizer divided by the main division factor N. If the synthesizer is in-lock, the frequency is equal to the reference frequency at CREF(Q) divided by R. It can be used as an accurate reference for another PLL. If needed, the polarity of the prescaler outputs can be inverted by bit TXPRSCLINV of register TXMFOUTC (F2h). In a contra-directional clock application, no clock is provided on pin TXPC (see Fig.16). The clock that samples the input data on the parallel bus, is an internal clock derived from signal TXPCO. In this application, the part providing the parallel data has to be clocked with the clock signal TXPCO(Q). In order to alleviate timing problems, the phase of clock TXPCO(Q), with respect to the internal clock, can be shifted in 90° steps. Bit TXPCOINV (180°) of register TXMFOUTC (F2h) together with bit TXPOPHASE (90°) of register MUXCON0 (F1h) sets the phase shift (see Table 11). If no prescaler information is desired, the output can be disabled by bit TXPRSCLEN of the same register. Apart from these settings, the signal amplitude can be set. This parameter follows the settings of the LVDS outputs. For programming details, see Section “LVDS outputs”. Loss of lock During operating, the loss of lock output pin LOL should be LOW which means that the clock synthesizer is in-lock and the output frequency corresponds to the programmed value. If pin LOL goes HIGH, phase and/or frequency lock is lost and the output frequency may deviate from the programmed value. The LOL condition is also available in the registers INTERRUPT (00h) and STATUS (01h). Table 11 Truth table for bits TXPCINV and TXPOPHASE On demand (interrupt is default masked), it generates an interrupt signal at pin INT. MULTIPLEXER The multiplexer comprises a high-speed input register, a 4-stage First In First Out (FIFO) elastic buffer, a parity check circuit and the actual multiplexing tree. 2003 Dec 16 APPLICATION 20 TXPCOINV TXPOPHASE PHASE SHIFT 0 0 0° 0 1 90° 1 0 180° 1 1 270° Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW FRAMER handbook, full pagewidth TZA3015HW TXPAR TX_PARITY TXPARQ 4 TX_DATA 4 TXPD0 to TXPD3 TXPD0Q to TXPD3Q TXPC TX_CLK TXPCQ TXPCO TX_CLK_SRC TXPCOQ FIFORESET CREF MGU684 system clock Fig.15 Co-directional clocking diagram. FRAMER handbook, full pagewidth TZA3015HW TXPAR TX_PARITY TXPARQ 4 TX_DATA 4 TXPD0 to TXPD3 TXPD0Q to TXPD3Q TXPCO TX_CLK_SRC TXPCOQ FIFORESET CREF MGU685 system clock Fig.16 Contra-directional clocking diagram. 2003 Dec 16 21 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Double data rate mode Table 15 Truth table for bit TXPCODDREN Usually the parallel clock frequency (TXPC, RXPC and TXPCO) equals the parallel data rate (for example when the serial bit rate is 2.488 Gbit/s, the parallel bit rate is 622 Mbit/s and the data is clocked with a 622 MHz clock). This is the default operating mode. TXPCODDREN In I2C-bus mode the three parallel clocks can be set separately in the DDR mode by bits RXPCDDREN, TXPCDDREN and TXPCODDREN of registers DDR&RXPRSCL (D5h), MUXCON0 (F1h) and TXMFOUTC (F2h) respectively (see Tables 13, 14 and 15). Table 12 Truth table for pin ENDDR TXPC, RXPC and TXPCO in normal mode HIGH TXPC, RXPC and TXPCO in DDR mode TXPCO in normal mode The asynchronous signal FIFORESET is re-timed by the internal clock from the clock generator. Two clock cycles after signal FIFORESET has been made HIGH, the FIFO initializes. Two clock cycles after signal FIFORESET has been made LOW, the FIFO will be operational again. To initialize automatically, when an overflow has occurred, it is possible to connect pin OVERFLOW to pin FIFORESET directly or via a resistor. Table 13 Truth table for bit RXPCDDREN RXPCDDREN 0 The overflow alarm persists until the FIFO is reset by a HIGH-level on pin FIFORESET or by setting bit FIFORESET of register MUXCON0 (F1h) to logic 1. A FIFORESET also initializes the FIFO. I2C-bus control of the FIFORESET function is obtained by programming bit I2CFIFORES of register MUXCON0 (F1h). To fully benefit from the FIFO, it should be reset whenever there has been a LOL condition, or when bit rates have changed. The DDR mode is functional for the whole bit-rate range, so it is true A-rate. LOW TXPCO in DDR mode In the co-directional clocking scheme, the input register samples the parallel bus data on the rising edge of the clock signal TXPC(Q). The same clock writes this data into the FIFO register. Data is retrieved from the FIFO by an internal clock, derived from the clock generator of the actual multiplexing tree. This provides for large jitter tolerance on the parallel interface; the FIFO absorbs momentary phase disturbances. Excessively large phase disturbances may stretch the elastic buffer to its limits, causing a FIFO overflow or underflow. Pin OVERFLOW and the registers STATUS (01h) and INTERRUPT (00h) indicate this situation. On demand (i.e to programmed in the register INTMASK [A0h]) it generates an interrupt signal at pin INT. The DDR functionality can be enabled by pin ENDDR (see Table 12) or via the I2C-bus. I2C-bus control is enabled by setting bit I2CDDR of register DDR&RXPRSCL (D5h). MODE 1 FIFO register However, in some applications it is required to use a parallel clock operating at a frequency that is half of the parallel data rate. This is the DDR mode (for example when the serial bit rate is 2.488 Gbit/s, the parallel bit rate is 622 Mbit/s and the data is clocked at both the rising as well as the falling edge of the 311 MHz clock). The timing for the parallel input interface is in accordance with the SFI4 specification. ENDDR MODE MODE 1 RXPC in DDR mode Multiplexing bus swap 0 RXPC in normal mode Bit TXBUSSWAP of register MUXCON1 (F0h) swaps the bus order of the parallel data input bus TXPD0(Q) to TXPD3(Q). Bit TXBUSSWAP reverses the order of bits from MSB to LSB, or vice versa, to allow for optimum connectivity on the PCB. Table 14 Truth table for bit TXPCDDREN TXPCDDREN MODE 1 TXPC in DDR mode 0 TXPC in normal mode 2003 Dec 16 22 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Parity checking independently. This saves power when only one half of the functionality is needed. The TZA3015HW can also be configured as a clean-up PLL. This is described in the Section “Loop modes”. The operating modes can be selected with pins ENRX and ENTX, these pins enable the receiver and the transmitter. This also offers the possibility to power-down the complete IC. Operating (or enable) modes are listed in Table 17. In order to check the integrity of the data provided on the parallel input bus, a parity checking function has been implemented in the TZA3015HW. The calculated parity, based on the data currently on the bus, is compared to the expected parity provided at pins TXPAR(Q). If these do not match, i.e. a parity error has occurred, the output pins TXPARERR(Q) are HIGH during the next parallel bus clock (TXPC) period. Table 17 Truth table for the operating modes Odd or even parity checking can be selected by pin PAREVEN or by bit TXPAREVEN of register MUXCON1 (F0h). I2C-bus control of the parity type is enabled by setting bit I2CTXPAREVEN of register MUXCON1 (F0h). A HIGH-level on pin PAREVEN corresponds with even parity (default for bit TXPAREVEN), see Table 16. ENRX ENTX LOW LOW OPERATING MODE power-down LOW HIGH transmitter HIGH LOW receiver HIGH HIGH transceiver (or transponder) Table 16 Truth table for parity setting LOOP MODES PIN PAREVEN BIT TXPAREVEN PARITY TYPE LOW 0 odd HIGH 1 even The TZA3015HW supports four loop modes: • Line loop back • Diagnostic loop back • Serial loop timing Jitter performance • Clean-up loop back. The clock synthesizer has been optimized for lowest jitter generation and the data and clock recovery has been optimized for the best jitter tolerance. For all SDH/SONET line rates, the jitter tolerance and the jitter generation is compliant with ITU-T standard G.958, provided the reference clock is clean enough. For optimum jitter generation, the single-sideband phase noise of the reference frequency should be less than −140 dBc/Hz, for frequencies greater than 12 kHz from the carrier. If the reference divider R is used, this requirement elevates with approximately 20 × log R. Selecting the loop modes The required loop mode can be selected either by pins LM0, LM1 and LM2 or by I2C-bus control. The pin settings for the loop mode selection can be seen in Table 18. Table 18 Loop mode selection; note 1 Configuring the main functionality OPERATING MODES The TZA3015HW can be configured in several operating modes. It can be configured as: • Transceiver • Transmitter LM2 LM1 LM0 MODE LOW LOW LOW normal LOW LOW HIGH line loop back LOW HIGH LOW diagnostic loop back HIGH LOW HIGH serial loop timing HIGH HIGH LOW clean-up loop back HIGH HIGH HIGH normal • Receiver Note • Transponder with clean-up PLL. 1. The loop mode can be also programmed by setting bits LM[2:0] in register LOOPMODE (A3h). The transceiver configuration is the default operating mode. The transmitter and receiver part can be enabled 2003 Dec 16 23 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Line loop back mode transmit clock is generated. The parallel output clock signal is recovered from the serial output data. This loop mode is used to test the connection between the transceiver and the data processing unit and the system itself. No external fibre optic connection is needed to test the system (see Fig.18). This mode feeds back the received serial data to the serial data output together with the recovered serial clock. This allows testing of the serial data path including the optic fibres. The received serial data that is fed back is also available in parallel format at the parallel output bus (see Fig.17). Serial loop timing mode Diagnostic loop back mode This mode feeds back the recovered clock to the clock synthesizer in order to run the receiver and transmitter at the same clock frequency (see Fig.19). This mode feeds back the parallel input data to the parallel outputs together with a parallel clock. The parallel data is serialized and available at the serial output. Also a serial handbook, full pagewidth data serial data clock serial clock 4 4 4 MULTIPLEXER parallel data parallel clock SYNTHESIZER DCR serial data data 4 parallel data DEMULTIPLEXER clock LIMITER 4 parallel clock MCE416 Fig.17 Line loop back mode. handbook, full pagewidth data serial data clock serial clock 4 4 4 MULTIPLEXER parallel data parallel clock SYNTHESIZER DCR serial data LIMITER data 4 4 parallel data DEMULTIPLEXER clock parallel clock MCE417 Fig.18 Diagnostic loop back mode. 2003 Dec 16 24 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW data handbook, full pagewidth serial data clock serial clock 4 4 4 MULTIPLEXER parallel data parallel clock SYNTHESIZER DCR serial data LIMITER data 4 4 parallel data DEMULTIPLEXER clock parallel clock MCE418 Fig.19 Serial loop timing mode. Clean-up loop back mode components. The PLL consists of a phase frequency detector, a charge pump, an external loop filter (R, C1 and C2), a VCXO and a reference divider. The combination of R and C1 is mandatory and will transform the current at the output of the charge pump into a control voltage for the VXCO. Capacitor C2 is optional. The TZA3015HW can be used in transponder applications. In this application, the transmitter is locked onto the recovered clock from the DCR (RXPRSCL). Without preparations, the jitter transfer of this application is determined by cascading the transfer functions of the DCR and the clock synthesizer. This transfer function is not well controlled and may not meet the required specification in terms of bandwidth and/or jitter peaking. A second drawback is that the jitter generation of the synthesizer is degraded because the frequency reference (i.e. the DCR) is not very clean in terms of phase-noise. The internal clock and data path in the TZA3015HW is clarified in Fig.21. As can be seen in the clean-up application, the received (and transmitted) data is also available in parallel format at the parallel output bus. Two bits are available to ease the design of the clean-up PLL. The loop is designed to work with a VCXO that has a positive gain. That is an increasing voltage on the VCXO control input will increase the output frequency. By means of bit CLUPPLLINV of register REFDIV (A1h) the loop is inverted and will work with VCXOs which have a negative gain. Bit CLUPPLLHG of register REFDIV (A1h) will change the gain of the charge pump. If bit CLUPPLLHG is logic 0, the charge pump current ICP is 100 µA. If bit CLUPPLLHG is logic 1, the charge pump current ICP is 1 mA. This eases choosing suitable component values for R and C1. To improve both the jitter transfer and jitter generation in transponder applications, an external low-noise reference oscillator is locked onto the DCR recovered clock by means of a small band PLL, i.e. the clean-up PLL. The low-noise oscillator, e.g. a Voltage Controlled Crystal Oscillator (VCXO), acts as the reference for the clock synthesizer. If appropriately designed, the jitter will be dominated by the clean-up PLL. This PLL can be optimized for bandwidth and jitter peaking, while the jitter generation is optimized by choosing the appropriate VCXO. Figure 20 shows a typical clean-up PLL application. For ease of use, all components are integrated in the TZA3015HW, except for the VCXO and the loop filter 2003 Dec 16 25 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW external components handbook, full pagewidth from DCR PHASE FREQUENCY DETECTOR I2C bit: CLUPPLLINV CHARGE PUMP CREF REFERENCE DIVIDER IPUMP VCXO e.g. Vectron VDSGLA type C1 C2 R I2C bit: CLUPPLLHG to synthesizer MCE419 Fig.20 Clean-up PLL application with the TZA3015HW. handbook, full pagewidth data serial data clock serial clock 4 4 4 MULTIPLEXER parallel data parallel clock SYNTHESIZER DCR serial data LIMITER data 4 4 parallel data DEMULTIPLEXER clock parallel clock MCE420 Fig.21 Clean-up loop back mode. I/O configuration • Transmitter parallel clock output; pins TXPCO(Q) LVDS OUTPUTS • Prescaler DCR output; pins RXPRSCL(Q) • Prescaler synthesizer output; pins TXPRSCL(Q). Several options exist that allow flexible configuration of the LVDS outputs: output amplitude, signal polarity, bus order, mute and selective enable/disable of various outputs. All these options can be set in the registers MFOBCON (A4h), DMXCON (B8h), RXMFOUTC0 (D4h), DDR&RXPRSCL (D5h) and TXMFOUTC (F2h). Affected by these registers are: The output swing of all LVDS outputs can be set by pin LOWSWING or by programming bit LOWSWING in register MFOBCON (A4h). I2C-bus control is enabled by programming bit I2CLOWSWING in register MFOBCON (A4h). The typical voltage levels are given in Table 19. See also Figs 34 and 35. • Parallel clock output; pins RXPC(Q) Table 19 Truth table for pin LOWSWING • Parallel data output; pins RXPD0(Q) to RXPD3(Q) • Frame pulse output; pins RXFP(Q) LOWSWING LVDS OUTPUT VOLTAGE SWING • Parity output; pins RXPAR(Q) LOW 500 mV • Parity error output; pins TXPARERR(Q) HIGH 300 mV 2003 Dec 16 26 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Parallel clock output Prescaler DCR output Bit RXPCINV of register RXMFOUTC0 (D4h) sets the polarity of the parallel clock output RXPC(Q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. This might resolve a parallel bus timing problem. The parallel clock output can be disabled by programming bit RXPCEN of register RXMFOUTC0 (D4h). The polarity of the receiver prescaler output RXPRSCL(Q) is set by bit RXPRSCLINV of register DDR&RXPRSCL (D5h). The receiver prescaler output can be disabled by programming bit RXPRSCLEN of register DDR&RXPRSCL (D5h). Prescaler synthesizer output The polarity of the transmitter prescaler output TXPRSCL(Q) is set by bit TXPRSCLINV of register TXMFOUTC (F2h). The transmitter prescaler output can be disabled by programming bit TXPRSCLEN of register TXMFOUTC (F2h). Parallel data output The parallel output bus data RXPD0(Q) to RXPD3(Q) can be swapped by bit RXBUSSWAP of register DMXCON (B8h). The mute option forces the parallel output bits to a logic 0 state. This is done by programming bit DMXMUTE of register DMXCON (B8h). The polarity of the data RXPD0(Q) to RXPD3(Q) can be set by bit RXPDINV of register RXMFOUTC0 (D4h). The data outputs can be disabled by programming bit RXPDEN of register RXMFOUTC0 (D4h). LVDS INPUTS The available LVDS inputs are: • Parallel clock input; pins TXPC(Q) • Parallel data input; pins TXPD0(Q) to TXPD3(Q) • Parity input; pins TXPAR(Q). Frame pulse output The differential LVDS inputs can handle any input swing with a minimum of 100 mV (p-p) single-ended. The inputs accept any value between VEE and VCC, i.e. the input buffers are true rail-to-rail. The limiting value of the LVDS input current is 25 mA. A differential hysteresis of 25 mV is implemented; see Fig.33. The polarity of the frame pulse output RXFP(Q) is set by bit RXFPINV of register RXMFOUTC0 (D4h). The frame pulse output can be disabled by programming bit RXFPEN of register RXMFOUTC0 (D4h). Parity output Parallel clock input The polarity of the parity output RXPAR(Q) is set by bit RXPARINV of register RXMFOUTC0 (D4h). The parity output can be disabled by programming bit RXPAREN of register RXMFOUTC0 (D4h). Bit TXPCINV of register MUXCON1 (F0h) sets the polarity of the parallel clock input TXPC(Q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. This could be used to resolve a parallel bus timing problem. Parity error output The polarity of the parity error output TXPARERR(Q) is set by bit TXPARERRINV of register TXMFOUTC (F2h). The parity error output can be disabled by programming bit TXPARERREN of register TXMFOUTC (F2h). Parallel data input The order of the parallel output bus data TXPD0(Q) to TXPD3(Q) can be programmed by bit TXBUSSWAP of register MUXCON1 (F0h). Transmitter parallel clock output Bit TXPDINV of register MUXCON1 (F0h) sets the polarity of the parallel data inputs TXPD0(Q) to TXPD3(Q). Bit TXPCOINV of register TXMFOUTC (F2h) sets the polarity of the parallel clock output TXPCO(Q), effectively shifting the clock edge by half a clock cycle and changing the rising edge to a falling edge. The phase of the clock can be shifted by 90° by programming bit TXPCOPHASE of register MUXCON0 (F1h). The combination of these two bits offers a phase shift range of 0 to 360°, adjustable in four steps (step size 90°). This might resolve a parallel bus timing problem. The parallel clock output can be disabled by programming bit TXPCOEN of register TXMFOUTC (F2h). 2003 Dec 16 RF OUTPUTS The serial RF outputs are CML type outputs (see Figs 31 and 32). Several options exist that allow flexible configuration of the RF outputs: output amplitude adjustment, signal polarity, data-clock swap, output termination and selective enable/disable of the clock output. Thus, the TZA3015HW can be configured so that 27 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW connectivity problems with other ICs are avoided. Unused outputs can be disabled. REFERENCE CLOCK INPUT The reference clock CREF(Q) input is shown in Fig.36 These options can be programmed in registers TXRFOUTC1 (F3h) and TXRFOUTC0 (F4h). The following RF outputs are available: RF INPUT The serial data inputs are pins RXSD(Q). These pins are differential CML type serial RF data inputs. There are no special settings for these inputs. • Serial data output; pins TXSD(Q) • Serial clock output; pins TXSC(Q). The RF CML data and clock outputs have an adjustable signal amplitude between 70 and 1100 mV (p-p) single-ended in 16 steps. The amplitude can be programmed by setting bits RFS[3:0] of register TXRFOUTC0 (F4h). The default amplitude is 300 mV (p-p) single-ended. CMOS OUTPUTS The CMOS outputs are all used as logic outputs to indicate the status of the TZA3015HW. • Loss of signal output; pin LOS • Frequency window detector output; pin INWINDOW The clock and data outputs can be swapped by programming bit TXSDSCSWAP of register TXRFOUTC1 (F3h). Allowing full flexibility in the PCB design. • Interrupt output; pin INT • Loss of lock output; pin LOL • FIFO overflow alarm output; pin OVERFLOW. The data and clock outputs can be DC- or AC-coupled to the laser driver. The TZA3015HW serial RF outputs can be adapted to this for optimal connectivity by appropriately setting bit RFOUTTERMAC of register TXRFOUTC0 (F4h). DC termination is default. A LOW state equals the ground potential and a HIGH state equals the supply voltage. The INT output can be configured as CMOS output or as open-drain output (see Sections “Open-drain output” and “Interrupt generation”). The output is configured as open-drain output by default. Serial clock output CMOS INPUTS The polarity of the serial clock output TXSC(Q) can be programmed by bit TXSCINV of register TXRFOUTC1 (F3h). The serial clock output can be disabled by setting pin ENTXSC or by programming bit TXSCEN of register TXRFOUTC1 (F3h) (see Table 20). This saves power dissipation in applications where the serial clock is not needed The CMOS inputs are all used as logic inputs to configure the TZA3015HW: • User interface selection input; pin UI • Data rate selection inputs; pins DR0 to DR2 • Loop mode selection inputs; pins LM0 to LM2 • Enable receiver input; pin ENRX Table 20 Truth table for serial clock enable • Enable transmitter input; pin ENTX PIN ENTXSC BIT ENTXSC LOW 0 disabled • Wide and narrow frequency detect window selection input; pin WINSIZE HIGH 1 enabled • Enable low LVDS swing output input; pin LOWSWING SERIAL CLOCK • Reference frequency selection inputs; pins FREF0 and FREF1 In order to control the enabling of the serial clock output by the I2C-bus, bit I2CTXSCEN of register TXRFOUTC1 (F3h) must be programmed. • Enable byte alignment input; pin ENBA • FIFO reset input; pin FIFORESET • Odd or even parity check input; pin PAREVEN Serial data output • Co-directional or contra-directional clocking selection input; pin CLKDIR The polarity of the serial data output TXSD(Q) can be programmed by bit TXSDINV of register TXRFOUTC1 (F3h). The data output can be disabled by programming bit TXSDEN of register TXRFOUTC1 (F3h). 2003 Dec 16 • Enable serial clock input; pin ENTXSC. 28 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW interrupt bits where the ‘alarm’ is no longer present. If the ‘alarm’ is still set, the interrupt bit is not cleared after the read action. If an interrupt bit remains set (and if it is not masked) the INT pin will keep its interrupt condition active; it will not generate a pulse nor a spike. The I2C-bus status register is not reset since it always shows the present status of the receiver. It is important to note that the three reserved bits of the STATUS and INTERRUPT registers can take any value and that they can change during operating. These bits can not be used to obtain information on the status of the IC. The CMOS inputs have an internal pull-up resistance; if the input is left open, a logic HIGH state will be forced internally. In the pre-programmed mode (UI = LOW), pins DR0 to 2 act as regular CMOS inputs. In the I2C-bus mode (UI = HIGH), pins SCL and SDA comply with the I2C-bus interface standard. OPEN-DRAIN OUTPUT The TZA3015HW contains one open-drain interrupt output pin INT. The output type of the interrupt controller can be configured by programming bit INTOUT of register INTCONF (A5h). The output can be configured as a push-pull CMOS output or as an open-drain output. For the open-drain configuration an external pull-up resistor of 3.3 kΩ is recommended. The polarity can be set by programming bit INTPOL of register INTCONF (A5h). Power supply connections Four separate supply domains (VDD, VCCD, VCCO and VCCA) provide isolation between the various functional blocks. Each supply domain should be connected to a common VCC via separate filters. All supply domains should be powered synchronously. INTERRUPT GENERATION The TZA3015HW features a fully configurable interrupt generator. An interrupt signal can be generated in the following events: All supply pins, including the exposed die pad, must be connected. The die pad should be connected with the lowest inductance possible. Since the die pad is also used as the main ground return of the chip, the connection should have a low DC impedance as well. The voltage supply levels should be in accordance with the values specified in Chapter “Characteristics”. • Loss Of Signal (LOS) • INWINDOW • Temperature alarm • Loss Of Lock (LOL) All external components should be surface mounted devices, preferably of size 0603 or smaller. The components must be mounted as closely to the IC as possible. • FIFO overflow or underflow. The aforementioned events generate flags which can be read in register STATUS (01h). Each of these flags will generate an interrupt in the INTERRUPT register (00h). If programmed so in the register INTMASK (A0h) the INTERRUPT register bit(s) will generate an interrupt on pin INT. In this mask register each interrupt bit can be masked by writing a logic 0 in the corresponding bit position. I2C-BUS I2C-bus characteristics The I2C-bus is a 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Data transfer may be initiated only when the line is not busy. The STATUS register shows the present status of the receiver. The INTERRUPT register shows the history of the interrupts and is not affected by the INTMASK register. START AND STOP CONDITIONS Bit INTOUT of register INTCONF (A5h) determines the output type of pin INT: standard CMOS output or open-drain output. The latter is the default which provides for multiple receivers sharing a common interrupt signal wire with a 3.3 kΩ pull-up resistor (INT is active LOW in this case). The polarity can be set by programming bit INTPOL of register INTCONF (A5h). Figure 22 shows the definition of the start and stop conditions. Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH is defined as the start condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the stop condition (P). The interrupt and status register can be polled by an I2C-bus read action. After the read action on the interrupt register the interrupt register is reset by clearing the 2003 Dec 16 29 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW ACKNOWLEDGE The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a stop condition. Figure 23 shows the definition of an acknowledgement on the I2C-bus. Only one data byte is transferred between the start and stop conditions during a write from the transmitter to the receiver. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition MBC622 Fig.22 Start and stop conditions. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.23 (Not) acknowledge condition on the I2C-bus. 2003 Dec 16 30 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW I2C-bus protocol READ PROTOCOL Figure 24 shows the definition of the bytes. If bit R/W = 1 the master reads from the read register, if bit R/W = 0 the master writes to the write register. It is not possible to write and read the same register. Figure 26 shows the protocol for reading from one or more registers. After the start command (S) the receiver sends the address of the slave device, waits for an acknowledge from the transmitter slave, receives data from the slave (slave, TZA3015HW, starts sending data after generating the acknowledge), after receiving the data, the receiver (master) sends an acknowledge, or if finished a not-acknowledge followed by a stop condition (P). WRITE PROTOCOL Figure 25 shows the protocol for writing to one single register. After the start command (S) the transmitter sends the address of the slave device, waits for an acknowledge from the slave, sends the register address, waits for an acknowledge, sends data, waits for an acknowledge from the master followed by a stop condition (P). handbook, full pagewidth MSB LSB MSB R/W 1 LSB Slave address Register address MCE425 Fig.24 Definition of slave- and register address (= instruction byte); slave and register addresses are 7 bits. acknowledge from slave handbook, full pagewidth acknowledge from slave R/W MSB S SLAVE ADDRESS 0 A 1 acknowledge from master MSB REGISTER ADDRESS A LSB DATA A P one byte transferred MDB071 Fig.25 Write protocol. handbook, halfpage R/W S acknowledge from master (1) acknowledge from slave SLAVE ADDRESS MSB 1 A LSB DATA A/A P n bytes MDB072 (1) The master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. Fig.26 Read protocol. 2003 Dec 16 31 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW I2C-BUS REGISTERS The TZA3015HW can be programmed via the I2C-bus if pin UI = HIGH or leaving the pin open-circuit. The I2C-bus registers can be accessed via the 2-wire I2C-bus interface using pins SCL and SDA if pin CS = HIGH during read or write actions. The I2C-bus address of the TZA3015HW can be found in Table 2. Table 21 I2C-bus registers ADDRESS (HEX) NAME FUNCTION DEFAULT RANGE R/W General part 00 INTERRUPT interrupt register (see Table 22) XXXX XXXX n.a. R 01 STATUS status register (see Table 23) XXXX XXXX n.a. R A0 INTMASK interrupt mask register (see Table 24) 0000 0100 n.a. W A1 REFDIV reference divider and clean-up PLL (see Table 25) 0000 0000 n.a. W A3 LOOPMODE loop mode and enable register (see Table 26) 0110 0111 n.a. W A4 MFOBCON LVDS output buffer configuration (see Table 27) 0101 0000 n.a. W A5 INTCONF interrupt output configuration (see Table 28) 0000 0001 n.a. W B0 HEADER3 programmable header; MSB (see Table 29) 1111 0110 n.a. W B1 HEADER2 programmable header (see Table 30) 1111 0110 n.a. W B2 HEADER1 programmable header (see Table 31) 0010 1000 n.a. W B3 HEADER0 programmable header; LSB (see Table 32) 0010 1000 n.a. W B4 HEADERX3 programmable header don’t care; MSB (see Table 33) 0000 0000 n.a. W B5 HEADERX2 programmable header don’t care (see Table 34) 0000 0000 n.a. W B6 HEADERX1 programmable header don’t care (see Table 35) 0000 0000 n.a. W B7 HEADERX0 programmable header don’t care; LSB (see Table 36) 0000 0000 n.a. W B8 DMXCON demultiplexer configuration register (see Table 37) 0000 0000 n.a. W C0 RXOCTDIV DCR octave M divider (see Table 38) 0000 0000 n.a. W C1 RXMAINDIV1 VCO frequency N divider (see Table 39) 0000 0001 128 to 511 W C2 RXMAINDIV0 VCO frequency N divider (see Table 40) 0000 0000 128 to 511 W C3 RXFRACN2 fractional division (see Table 41) 1000 0000 n.a. W C4 RXFRACN1 fractional division (see Table 42) 0000 0000 n.a. W C5 RXFRACN0 fractional division (see Table 43) 0000 0000 n.a. W C6 DCRCON DCR configuration register (see Table 44) 0000 1100 n.a. W D0 LIMLOSTH limiter loss threshold 0000 0000 0 to 255 W D1 LIMLOSCON limiter loss of signal configuration register (see Table 45) 0000 1101 n.a. W D2 LIMSL limiter slice level 0000 0000 0 to 255 W D3 LIMCON limiter amplifier configuration (see Table 46) 0000 0000 n.a. W D4 RXMFOUTC0 disable/invert parallel outputs (see Table 47) 1010 1010 n.a. W Transceiver 2003 Dec 16 32 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver ADDRESS (HEX) D5 NAME TZA3015HW FUNCTION DEFAULT DDR&RXPRSCL disable/invert parallel outputs (see Table 48) RANGE R/W 0010 0000 n.a. W Transmitter part E0 TXOCTDIV synthesizer octave divider (see Table 49) 0000 0000 n.a. W E1 TXMAINDIV1 VCO frequency (N divider) (see Table 50) 0000 0001 128 to 255 W E2 TXMAINDIV 0 VCO frequency (N divider) (see Table 51) 0000 0000 128 to 255 W E3 TXFRACN2 fractional division (see Table 52) 1000 0000 n.a. W E4 TXFRACN1 fractional division (see Table 53) 0000 0000 n.a. W E5 TXFRACN0 fractional division (see Table 54) 0000 0000 n.a. W F0 MUXCON1 multiplexer configuration byte 1 (see Table 55) 0110 0010 n.a. W F1 MUXCON0 multiplexer configuration byte 0 (see Table 56) 0000 0010 n.a. W F2 TXMFOUTC disable/invert LVDS outputs (see Table 57) 1010 1000 n.a. W F3 TXRFOUTC1 disable/invert RF outputs (see Table 58) 0100 1011 n.a. W F4 TXRFOUTC0 RF output configuration register (see Table 59) 0000 0011 n.a. W Table 22 Register INTERRUPT (address: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION loss of signal 1 no signal present 0 signal present INWINDOW 1 frequency out of window 0 frequency in window temperature alarm 1 junction temperature ≥130 °C 0 junction temperature <130 °C loss of lock x x LOS INWINDOW TALARM LOL 1 synthesizer out of lock 0 synthesizer out of lock x reserved FIFO overflow or underflow 1 FIFO overflow or underflow occurred 0 FIFO normal operating 2003 Dec 16 NAME 33 OVERFLOW Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 23 Register STATUS (address: 01h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION loss of signal LOS 1 no signal present 0 signal present INWINDOW INWINDOW 1 frequency out of window 0 frequency in window temperature alarm TALARM 1 junction temperature ≥130 °C 0 junction temperature <130 °C loss of lock x x NAME LOL 1 synthesizer out of lock 0 synthesizer out of lock x reserved FIFO over- or underflow OVERFLOW 1 FIFO under- or underflow occurred 0 FIFO normal operating Table 24 Register INTMASK (address: A0h, default value: 04h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION mask LOS signal 1 not masked 0 masked; note 1 mask INWINDOW signal 1 not masked 0 masked; note 1 mask temperature alarm 1 not masked 0 masked; note 1 mask LOL signal x x 1 not masked 0 masked; note 1 x 1 not masked 0 masked; note 1 0 2003 Dec 16 0 0 MLOS MINWINDOW MTALARM MLOL reserved mask FIFO overflow or underflow 0 NAME 0 1 0 0 MOVERFLOW default value 34 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Note to Table 24 1. Signal is not processed by the interrupt controller. Table 25 Register REFDIV (address: A1h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION reference frequency division ratio divider R; octave selection 0 0 0 R=1 0 0 1 R=2 0 1 0 R=4 0 1 1 R=8 1 0 0 R = 16 1 0 1 NAME FREFI2C[2:0] R = 32 reference frequency division programming by I2C-bus I2CFREF 1 enable I2C-bus programming 0 enable programming by pins x reserved high gain clean-up PLL 1 enable high gain 0 normal gain CLUPPLLHG invert charge pump currents of the clean-up PLL 1 clean-up PLL inverted 0 clean-up PLL normal operating enable clean-up PLL CLUPPLLEN 1 clean-up PLL enabled 0 clean-up PLL disabled (except in clean-up loop back mode) 0 0 0 0 0 0 0 CLUPPLLINV 0 default value Table 26 Register LOOPMODE (address: A3h, default value: 67h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION 0 0 0 normal mode 0 0 1 line loop back mode 0 1 0 diagnostic loop back mode 0 1 1 reserved 1 0 0 reserved 1 0 1 serial loop timing mode 1 1 0 clean-up loop back mode 1 1 1 normal mode loop mode selection 2003 Dec 16 35 NAME LM[2:0] Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION loop mode programming by I2C-bus 1 enable I2C-bus programming 0 enable programming by pins x I2CLM reserved enable receiver 1 ENRX receiver enabled 0 receiver disabled enable transmitter 1 ENTX transmitter enabled 0 transmitter disabled transmitter/receiver enable by I2C-bus 1 enable 0 0 NAME I2C-bus I2CENTRX programming enable programming by pins 1 1 0 0 1 1 1 default value Table 27 Register MFOBCON (address: A4h, default value: 50h) BIT 7 6 PARAMETER 5 4 3 2 1 0 x x x x x x DESCRIPTION NAME reserved parallel output voltage swing 1 low swing (300 mV) 0 high swing (500 mV) LOWSWING parallel output voltage swing programming by I2C-bus I2CLOWSWING 1 enable I2C-bus programming 0 enable programming by pins 0 1 0 1 0 0 0 0 default value Table 28 Register INTCONF (address: A5h, default value: 01h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION interrupt output polarity 1 inverted 0 normal operating interrupt output configuration x x x x x x 0 0 0 0 0 0 2003 Dec 16 1 push-pull output 0 open drain output NAME INTPOL INTOUT reserved 0 1 default value 36 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 29 Register HEADER3 (address: B0h, default value: F6h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x x x x x 1 1 1 1 0 1 1 0 DESCRIPTION programmable header; H31 = MSB NAME H[31:24] default value Table 30 Register HEADER2 (address: B1h, default value: F6h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 1 1 1 1 0 1 1 0 DESCRIPTION programmable header NAME H[23:16] default value Table 31 Register HEADER1 (address: B2h, default value: 28h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 1 0 1 0 0 0 DESCRIPTION programmable header NAME H[15:08] default value Table 32 Register HEADER0 (address: B3h, default value: 28h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 1 0 1 0 0 0 DESCRIPTION programmable header; H00 = LSB NAME H[07:00] default value Table 33 Register HEADERX3 (address: B4h, default value: 00h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION don’t care; HX31 = MSB NAME HX[31:24] default value Table 34 Register HEADERX2 (address: B5h, default value: 00h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 2003 Dec 16 DESCRIPTION don’t care NAME HX[23:16] default value 37 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 35 Register HEADERX1 (address: B6h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION don’t care NAME HX[15:08] default value Table 36 Register HEADERX0 (address: B7h, default value: 00h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION don’t care; HX00 = LSB NAME HX[07:00] default value Table 37 Register DMXCON (address: B8h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x DESCRIPTION reserved parallel bus swapping 1 RXPD0 = MSB; RXPD3 = LSB (swapped) 0 RXPD3 = MSB; RXPD0 = LSB (normal) mute parallel outputs 1 enable mute; parallel outputs forced to logic 0 0 disable mute enable byte alignment 1 byte alignment enabled 0 byte alignment disabled ENBA programming by I2C-bus I2C-bus 1 enable 0 enable programming by pins 0 0 2003 Dec 16 0 0 0 0 0 NAME 0 RXBUSSWAP DMXMUTE ENBA I2CENBA programming default value 38 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 38 Register RXOCTDIV (address: C0h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION 0 0 0 M = 1; octave number 0 0 0 1 M = 2; octave number 1 0 1 0 M = 4; octave number 2 0 1 1 M = 8; octave number 3 1 0 0 M = 16; octave number 4 1 0 1 M = 32; octave number 5 1 1 0 M = 64; octave number 6 division ratio octave divider M; octave selection x x x x x 0 0 0 0 0 NAME RXDIV_M[2:0] reserved 0 0 0 default value Table 39 Register RXMAINDIV1 (address: C1h, default value: 01h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 DESCRIPTION division ratio divider N; RXN8 = MSB NAME RXN8 reserved 1 default value Table 40 Register RXMAINDIV0 (address: C2h, default value: 00h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION division ratio divider N; RXN0 = LSB NAME RXN[7:0] default value Table 41 Register RXFRACN2 (address: C3h, default value: 80h) BIT 7 6 PARAMETER 5 4 3 2 1 0 x x x x x x DESCRIPTION fractional divider; RXK21 = MSB x RXNILFRAC control bit (NF) no fractional N functionality 0 fractional N functionality 0 2003 Dec 16 RXK[21:16] reserved 1 1 NAME 0 0 0 0 0 0 RXNILFRAC default value 39 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 42 Register RXFRACN1 (address: C4h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION fractional divider NAME RXK[15:8] default value Table 43 Register RXFRACN0 (address: C5h, default value: 00h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION fractional divider; RXK0 = LSB NAME RXK[7:0] default value Table 44 Register DCRCON (address: C6h, default value: 0Ch) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION frequency window size; relative to bit rate 0 1 1 2000 ppm 1 0 0 1000 ppm 1 0 1 500 ppm 1 1 0 1 window size according to bits WINSIZE[2:0] (default value 1000 ppm); PLL frequency loosely coupled to reference crystal 0 window size is 0 ppm; PLL frequency directly synthesized from reference crystal WINSIZE control bit through 0 I2C-bus x x 0 WINSIZE I2CWINSIZE interface through external pin WINSIZE automatic frequency window size selection 0 WINSIZE[2:0] 250 ppm manual frequency window size selection 1 NAME 1 enabled 0 disabled AUTOWIN reserved 0 0 1 1 0 0 default value Table 45 Register LIMLOSCON (address: D1h, default value: 0Dh) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION enable loss of signal detection 2003 Dec 16 1 LOS detection enabled 0 LOS detection disabled 40 NAME LOSEN Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION LOS threshold level programming by I2C-bus 1 enable I2C-bus programming; set level by register D0h 0 set level by applying analog reference voltage on pin LOSTH loss of signal detection hysteresis 0 0 0 0 dB 0 0 1 1 dB 0 1 0 2 dB 0 1 1 3 dB 1 0 0 4 dB 1 0 1 5 dB 1 1 0 6 dB 1 1 1 7 dB enable slice level slice level enabled 0 slice level disabled positive slice level 0 negative slice level LOS level polarity LOSPOL 1 inverted polarity 0 normal polarity 0 0 1 1 0 HTLCB[2:0] SLSGN 1 0 I2CLOSTH SLEN 1 slice level sign 0 NAME 1 default value Table 46 Register LIMCON (address: D3h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION 0 0 0 octave number 0; 1800 to 3200 Mbit/s 0 0 1 octave number 1; 900 to 1800 Mbit/s 0 1 0 octave number 2; 450 to 900 Mbit/s 0 1 1 octave number 3; 225 to 450 Mbit/s 1 X X octave number 4; 30 to 225 Mbit/s amplifier octave selection x x x x x 0 0 0 0 0 2003 Dec 16 NAME AMP[2:0] reserved 0 0 0 default value 41 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 47 Register RXMFOUTC0 (address: D4h, default value: AAh) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION parallel data output polarity 1 inverted 0 normal RXPDINV parallel data output enable 1 enabled 0 disabled RXPDEN parallel clock output polarity 1 inverted 0 normal RXPCINV parallel clock output enable 1 enabled 0 disabled RXPCEN parity output polarity 1 inverted 0 normal RXPARINV parity output enable 1 enabled 0 disabled RXPAREN frame pulse output polarity 1 RXFPINV inverted 0 normal frame pulse output enable 1 RXFPEN enabled 0 1 NAME disabled 0 1 0 1 0 1 0 default value Table 48 Register DDR&RXPRSCL (address: D5h, default value: 20h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x DESCRIPTION reserved invert RX prescaler output 1 0 RXPRSCLINV inverted normal enable RX prescaler output 2003 Dec 16 NAME 1 enabled 0 disabled 42 RXPRSCLEN Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION DDR clock frequency mode for RXPC 1 DDR mode enabled 0 normal operating mode DDR programming by I2C-bus 1 enable I2C-bus programming 0 enable programming by pin ENDDR 0 0 1 0 0 0 0 0 NAME RXPCDDREN I2CDDR default value Table 49 Register TXOCTDIV (address: E0h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION 0 0 0 M = 1; octave number 0 0 0 1 M = 2; octave number 1 0 1 0 M = 4; octave number 2 0 1 1 M = 8; octave number 3 1 0 0 M = 16; octave number 4 1 0 1 M = 32; octave number 5 1 1 0 M = 64; octave number 6 division ratio octave divider M; octave selection x x x x x 0 0 0 0 0 NAME TXDIV_M[2:0] reserved 0 0 0 default value Table 50 Register TXMAINDIV1 (address: E1h, default value: 01h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 DESCRIPTION division ratio divider N; TXN8 = MSB NAME TXN8 reserved 1 default value Table 51 Register TXMAINDIV0 (address: E2h, default value: 00h) BIT PARAMETER 7 6 5 4 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 2003 Dec 16 DESCRIPTION division ratio divider N; TXN0 = LSB NAME TXN[7:0] default value 43 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 52 Register TXFRACN2 (address: E3h, default value: 80h) BIT 7 6 PARAMETER 5 4 3 2 1 0 x x x x x x DESCRIPTION fractional divider: TXK21 = MSB x TXK[21:16] reserved TXNILFRAC control bit (NF) 1 TXNILFRAC no fractional N functionality 0 1 NAME fractional N functionality 0 0 0 0 0 0 0 default value Table 53 Register TXFRACN1 (address: E4h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION fractional divider NAME TXK[15:8] default value Table 54 Register TXFRACN0 (address: E5h, default value: 00h) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x x x x x x x 0 0 0 0 0 0 0 0 DESCRIPTION fractional divider; TXK0 = LSB NAME TXK[7:0] default value Table 55 Register MUXCON1 (address: F0h, default value: 62h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION parallel INPUT bus swapping 1 TXPD0 = MSB; TXPD3 = LSB (swapped) 0 TXPD3 = MSB; TXPD0 = LSB (normal) parity polarity 1 even parity 0 odd parity parity programming by I2C-bus I2C-bus 1 by 0 by external pin PAREVEN 2003 Dec 16 inverted 0 normal TXBUSSWAP TXPAREVEN I2CTXPAREVEN interface parallel clock input polarity 1 NAME 44 TXPCINV Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION parallel data input polarity x x x 0 1 1 1 inverted 0 normal NAME TXPDINV reserved 0 0 0 1 0 default value Table 56 Register MUXCON0 (address: F1h, default value: 02h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION parallel clock output phase 1 0 0° phase shift contra-directional clocking parallel clock direction programming I2C-bus 1 by 0 I2C-bus by external pin CLKDIR 1 FIFORESET reset FIFO 0 normal mode FIFO reset programming by I2C-bus 1 by 0 I2C-bus x 2003 Dec 16 I2CFIFORES interface by external pin FIFORESET DDR clock frequency mode for TXPC 0 I2CLKDIR interface FIFO reset x CLKDIR co-directional clocking 0 0 TXPCOPHASE 90° phase shift parallel clock direction 1 NAME 1 DDR mode enabled 0 normal mode TXPCDDREN reserved 0 0 0 0 1 0 default value 45 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Table 57 Register TXMFOUTC (address: F2h, default value: A8h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION x reserved DDR clock frequency mode for TXPCO 1 DDR mode enabled 0 normal mode parallel clock output polarity 1 inverted 0 normal 1 enabled 0 disabled TXPCOEN prescaler output polarity 1 inverted 0 normal TXPRSCLINV prescaler output enable 1 enabled 0 disabled TXPRSCLEN parity error output polarity 1 inverted 0 normal TXPARERRINV parity error output enable 1 enabled 0 disabled 0 1 0 1 0 0 TXPCODDREN TXPCOINV parallel clock output enable 1 NAME TXPARERREN 0 default value Table 58 Register TXRFOUTC1 (address: F3h, default value: 4Bh) BIT 7 6 5 4 PARAMETER 3 2 1 0 x x DESCRIPTION reserved serial output data polarity 1 inverted 0 normal enable serial data output 1 enabled 0 disabled clock and data output swap 2003 Dec 16 NAME 1 swapped clock and data output 0 normal clock and data output 46 TXSDINV TXSDEN TXSDSCSWAP Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION serial clock output polarity 1 inverted 0 normal TXSCINV enable serial clock output 1 enabled 0 disabled NAME TXSCEN serial clock output enable programming by I2C-bus I2CTXSCEN 1 by I2C-bus interface 0 by external pin TXSC 0 1 0 0 1 0 1 1 default value Table 59 Register TXRFOUTC0 (address: F4h, default value: 03h) BIT 7 6 5 4 PARAMETER 3 2 1 0 DESCRIPTION 0 0 0 0 minimum; 70 mV (p-p) 0 0 1 1 default; 300 mV (p-p) 1 1 1 1 maximum; 1100 mV (p-p) serial output signal amplitude x x RFS[3:0] reserved serial output termination 1 AC-coupled 0 DC-coupled x 0 NAME RFOUTTERMAC reserved 0 2003 Dec 16 0 0 0 0 1 1 default value 47 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER MIN. MAX. UNIT VCC analog supply voltage −0.5 +3.6 V VDD digital supply voltage −0.5 +3.6 V Vn DC voltage 0.7 VCC + 0.5 V on pins RXPC(Q), RXPD0(Q) to RXPD3(Q), RXFP(Q), RXPAR(Q), TXPARERR(Q), TXPCO(Q), RXPRSCL(Q) and TXPRSCL(Q) on pins RXSD(Q), CREF(Q), TXPC(Q), TXPD0(Q) to TXPD3(Q), −0.5 TXPAR(Q), UI, RREF, LOSTH, RSSI, LOS, CS, SDA, SCL, LM0 to LM2, INT, ENRX, ENTX, WINSIZE, INWINDOW, ENDDR, LOWSWING, ENBA, PAREVEN, OVERFLOW, FIFORESET, ENTXSC, TXSD(Q), TXSC(Q), LOL, FREF0, FREF1, CLKDIR and IPUMP VCC + 0.5 V input current In on pins RXPC(Q), RXPD0(Q) to RXPD3(Q), RXFP(Q), RXPAR(Q), TXPARERR(Q), TXPCO(Q), RXPRSCL(Q) and TXPRSCL(Q) −20 +20 mA on pins RXSD(Q) and CREF(Q) −30 +30 mA on pin INT −2 +2 mA on pins TXPC(Q), TXPD0(Q) to TXPD3(Q) and TXPAR(Q) −25 +25 mA Tamb ambient temperature −40 +85 °C Tj junction temperature − 125 °C Tstg storage temperature −65 +150 °C THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS thermal resistance from junction to ambient notes 1 and 2 VALUE UNIT 16 K/W Notes 1. In compliance with JEDEC standards JESD51-5 and JESD51-7. 2. Four-layer Printed-Circuit Board (PCB) in still air with 36 plated vias connected with the heatsink and the second and fourth layer in the PCB. 2003 Dec 16 48 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW CHARACTERISTICS VCCA = VCCD = VCCO = 3.14 to 3.46 V; Tamb = −40 to +85 °C; Rth(j-a) < 16 K/W; all characteristics are specified for the default test settings (see Table 60); all voltages are referenced to VEE; positive currents flow into the device; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies ICCA analog supply current 13 21 29 mA ICCD digital supply current 350 395 456 mA IDD digital supply current 0 0.3 1 mA ICCO supply current for clock generator 41 55 64 mA ICC(tot) total supply current notes 1 and 2 404 471 550 mA Ptot total power dissipation notes 1 and 2 1.3 1.6 1.8 W notes 1 and 2 CMOS inputs: pins UI, CS, DR0 to DR2, LM0 to LM2, ENRX, ENTX, PAREVEN, WINSIZE, LOWSWING, FREF0, FREF1, ENBA, FIFORESET, CLKDIR, ENTXSC and ENDDR VIL LOW-level input voltage − − 0.2VCC V VIH HIGH-level input voltage 0.8VCC − − V IIL LOW-level input current VIL = 0 V −200 − − µA IIH HIGH-level input current VIH = VCC − − 10 µA 0 − 0.2 V VCC − 0.2 − VCC V CMOS outputs: pins LOS, INT, INWINDOW, LOL and OVERFLOW VOL LOW-level output voltage IOL = 1 mA VOH HIGH-level output IOH = −0.5 mA voltage Open-drain output: pin INT VOL LOW-level output voltage IOL = 1 mA 0 − 0.2 V IOH HIGH-level output VOH = VCC current − − 10 µA 220 300 380 mV Serial outputs: pins TXSD(Q) and TXSC(Q) single-ended with 50 Ω external load; DC swing; note 3 Vo(p-p) default output voltage swing (peak-to-peak value) Zo output impedance single-ended to VCC 40 50 60 Ω tr rise time − 60 90 ps 2003 Dec 16 20% to 80% 49 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver SYMBOL PARAMETER TZA3015HW CONDITIONS MIN. TYP. MAX. UNIT tf fall time 80% to 20% − 60 90 ps tD-C data-to-clock delay between differential crossovers; see Fig.27 −50 − +50 ps δ duty cycle signal TXSC(Q) between differential crossovers 40 50 60 % fbit output bit rate 30 − 3200 Mbit/s Serial input: pins RXSD(Q) Vi(p-p) input voltage swing (peak-to-peak value) single-ended; note 4; PRBS (27 − 1) 12 − 500 mV Vi(sens)(p-p) input voltage sensitivity (peak-to-peak value) single-ended; PRBS (27 − 1) − 5 12 mV Vsl typical slice level range note 5 −50 − +50 mV Zi input impedance differential 80 100 120 Ω fbit input data rate 30 − 3200 Mbit/s LVDS outputs: pins RXPD0(Q) to RXPD3(Q), RXPC(Q), RXPAR(Q), TXPARERR(Q), RXPRSCL(Q),TXPRSCL(Q), RXFP(Q) and TXPCO(Q) Vo(dif) differential output voltage RL = 100 Ω; DC-coupled low swing mode, DC 250 300 360 mV high swing mode, DC 400 500 600 mV Vo(cm) common mode output voltage RL = 100 Ω, DC-coupled 1.10 1.22 1.33 V tr, tf rise and fall time CL = 1 pF 100 200 250 ps tD-C data to clock delay normal mode; see Fig.28 −200 +200 ps DDR mode; see Fig.28 1/ duty cycle RXPC(Q) normal mode 45 50 55 % DDR mode 47 50 53 % δTX duty cycle TXPCO(Q) normal mode 45 50 55 % DDR mode 47 50 53 % skew channel to channel skew RXPD0 to RXPD3, RXPAR and RXFP; note 6 − − 100 ps 0 − VCC mV −100 − +100 mV δRX 4Tclk − − 250 1/ 4Tclk − 50 1/ 4Tclk + 150 ps LVDS inputs: pins TXPD0(Q) to TXPD3(Q), TXPAR(Q) and TXPC(Q) Vi input voltage range Vi(th)(dif) differential input voltage threshold 2003 Dec 16 DC 50 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver SYMBOL PARAMETER TZA3015HW CONDITIONS MIN. TYP. − MAX. UNIT Vi(p-p) input voltage swing (peak-to-peak value) single-ended; note 6 − Vi(hys) differential hysteresis input voltage Tamb = 0 °C to 85 °C 25 − − mV Tamb = −40 °C to 0 °C 15 − − mV 80 100 120 Ω 1000 mV zi(dif) differential input impedance th(co) hold time co-directional clocking see Fig.29 − 150 300 ps tsu(co) set-up time co-directional clocking see Fig.29 − 20 300 ps th(contra) hold time contradirectional clocking see Fig.29 − −1100 −850 ps tsu(contra) set-up time contra-directional clocking see Fig.29 − 1300 1450 ps th(co)DDR hold time co-directional clocking in DDR mode fbit = 124 to 800 Mbit/s; see Fig.29 − 0.3Tclk + 40 0.3Tclk + 240 ps fbit = 30 to 124 Mbit/s; see Fig.29; note 6 − 4780 5000 ps fbit = 124 to 800 Mbit/s; see Fig.29 − −1/4Tclk − 130 −1/4Tclk + 200 ps fbit = 30 to 124 Mbit/s; see Fig.29; note 6 − −4560 −3700 ps hold time contra-directional clocking in DDR mode see Fig.29 − −1/4Tclk − 1200 −1/4Tclk − 1000 ps tsu(contra)DDR set-up time contra-directional clocking in DDR mode see Fig.29 − 1/ δ note 6 40 50 60 % tsu(co)DDR th(contra)DDR set-up time co-directional clocking in DDR mode duty cycle clock TXPC(Q) 4Tclk + 1400 1/ 4Tclk + 1600 ps Reference frequency input; pins CREF(Q) Vi(p-p) input swing (peak-to-peak value) single-ended 50 − 1000 mV Vi input voltage range note 6 VCC − 1 − VCC + 0.25 V Zi input impedance single-ended to VCC 40 50 60 Ω 2003 Dec 16 51 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver SYMBOL PARAMETER TZA3015HW CONDITIONS MIN. TYP. MAX. UNIT ∆fCREF reference clock frequency accuracy SDH/SONET requirement −20 − +20 ppm fCREF reference clock frequency see Section “Reference clock programming”; R = 1, 2, 4, 8, 16 or 32 18 × R 19.44 × R 21 × R MHz 10 kΩ resistor to VEE 1.17 1.21 1.26 V Reference voltage; pin RREF Vref reference voltage Received signal strength indicator; pin RSSI Vi(p-p) detectable input voltage swing on serial data input (peak-to-peak value) single-ended 5 − 500 mV SRSSI RSSI sensitivity see Fig.4 15 17 20 mV/dB VRSSI(32mV) output voltage serial data input voltage Vi = 32 mV; PRBS(231 − 1) 580 680 780 mV ∆Vo output voltage variation input 30 to 3200 Mbit/s; PRBS(231 − 1); VCC = 3.14 to 3.47 V; ∆T = 120 °C −50 − +50 mV Zo output impedance − 1 10 Ω Io(source) output source current − − 1 mA Io(sink) output sink current − − 0.4 mA LOS detector hys hysteresis note 7 − 3 − dB ta assert time ∆Vi(p-p) = 3 dB − − 5 µs td de-assert time ∆Vi(p-p) = 3 dB − − 5 µs CLUPPLLHG = 0 − −0.1 − mA CLUPPLLHG = 1 − −1 − mA charge pump sink CLUPPLLHG = 0 current CLUPPLLHG = 1 − 0.1 − mA − 1 − mA Clean-up PLL: pin IPUMP Icp(source) Icp(sink) 2003 Dec 16 charge pump source current 52 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver SYMBOL PARAMETER TZA3015HW CONDITIONS MIN. TYP. MAX. UNIT Jitter characteristics Jtol(p-p) jitter tolerance to serial data input signal (peak-to-peak value) STM1/OC3 mode; PRBS(223 − 1) f = 6.5 kHz 3 >10 − UI f = 65 kHz 0.3 >1 − UI f = 1 MHz 0.3 >0.5 − UI f = 25 kHz 3 >10 − UI f = 250 kHz 0.3 >1 − UI f = 5 MHz 0.3 >0.5 − UI f = 100 kHz 3 10 − UI f = 1 MHz 0.3 1 − UI f = 20 MHz 0.3 0.5 − UI − − 16 mUI − − 4 mUI − − 4 mUI f = 1 kHz to 5 MHz − − 63 mUI f = 12 kHz to 5 MHz − − 13 mUI f = 250 kHz to 5 MHz − − 13 mUI f = 5 kHz to 20 MHz − 32 250 mUI f = 12 kHz to 20 MHz − 30 50 mUI f = 1 MHz to 20 MHz − 6 50 mUI STM4/OC12 mode; PRBS(223 − 1) STM16/OC48 mode; PRBS(223 − 1) Jgen(p-p) jitter generation at STM1/OC3 mode; serial data and notes 8 and 9 clock output f = 500 Hz to 1.3 MHz (peak-to-peak f = 12 kHz to 1.3 MHz value) f = 65 kHz to 1.3 MHz STM4/OC12 mode; notes 8 and 9 STM16/OC48 mode; note 8 PLL characteristics receiver tacq acquisition time 30 Mbit/s; note 6 − − 200 µs tacq(pc) acquisition time at 30 Mbit/s; note 6 power cycle − − 10 ms tacq(o) acquisition time octave change − − 10 µs 30 Mbit/s; note 6 I2C-bus input and output: pins SCL and SDA VIL LOW-level input voltage − − 0.2VCC V VIH HIGH-level input voltage 0.8VCC − − V 2003 Dec 16 53 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver SYMBOL PARAMETER TZA3015HW CONDITIONS MIN. TYP. MAX. UNIT Vhys hysteresis of Schmitt-trigger inputs note 6 0.05VCC − − V VOL LOW-level output voltage on pin SDA (open-drain) IOL = 3 mA 0 − 0.4 V ILI input leakage current −10 − +10 µA Ci input capacitance note 6 − − 10 pF I2C-bus timing; note 6 fSCL SCL clock frequency − − 100 kHz tLOW SCL LOW time 1.3 − − µs tHD;STA hold time START condition 0.6 − − µs tHIGH SCL HIGH time 0.6 − − µs tSU;STA set-up time START condition 0.6 − − µs tHD;DAT data hold time 0 − 0.9 µs tSU;DAT data set-up time 100 − − ns tSU;STO set-up time STOP condition 0.6 − − µs tr SCL and SDA rise time 20 − 300 ns tf SCL and SDA fall time 20 − 300 ns tBUF bus free time between STOP and START 1.3 − − µs Cb capacitive load for each bus line − − 400 pF tSP pulse width of allowable spikes 0 − 50 ns VnL noise margin at LOW-level 0.1VCC − − V VnH noise margin at HIGH-level 0.2VCC − − V Notes 1. For the typical specification LVDS outputs: RXPAR(Q), RXPRSCL(Q), TXPARERR(Q), TXPCO(Q) and TXPRSCL(Q) are disabled. Also serial output TXSC(Q) is disabled. 2. The following conditions are valid for the maximum specification and are additional to the default settings: bit CLUPPLLEN = 1 (clean-up PLL is enabled); bit CLUPPLLHG = 1 (high gain); line loop back is enabled; pin LOWSWING = LOW (high swing for LVDS outputs); bits RFS[3:0] = 1111 (maximum output swing for TXSD(Q) and 2003 Dec 16 54 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW TXSC(Q). These maximum settings yield the following maximum specification values: ICCD = 680 mA, ICC(tot) = 774 mA and Ptot = 2.7 W. 3. The output swing is adjustable between 70 mV (typical) and 1100 mV (typical) in 16 steps controlled by bits RFS[3:0] of the register TXRFOUTC0 (F4h). 4. The RF input is protected against a differential overvoltage; the maximum input current is 30 mA. 5. The slice level is adjustable in 256 steps controlled by register LIMSL (D2h). 6. Guaranteed by design. 7. The hysteresis is adjustable in 8 steps controlled by bits HTLCB[2:0] of register LIMLOSCON (D1h). 8. Reference frequency of 19.44 MHz, with a phase-noise of less than −140 dBc for frequencies of more than 12 kHz from the carrier (measured during 60 seconds, within the appropriate bandwidth). 9. For bit rates lower than 1.8 Gbit/s, the jitter decreases by the octave division ratio M. Table 60 Default test settings PIN SETTING UI = LOW pre-programmed mode DR0 = LOW, DR1 = HIGH, DR2 = LOW STM16/OC48 LM0 = HIGH, LM1 = HIGH, LM2 = HIGH normal mode ENRX = HIGH receiver enabled ENTX = HIGH transmitter enabled ENDDR = LOW DDR mode disabled LOWSWING = HIGH low LVDS swing FREF0 = HIGH, FREF1 = HIGH 19.44 MHz reference RREF RRREF = 10 kΩ to VEE IPUMP open circuit RSSI open circuit LOSTH VLOSTH = 0.6 V ENTXSC = HIGH serial output clock enabled WINSIZE = HIGH 1000 ppm ENBA = HIGH automatic byte alignment PAREVEN = HIGH even parity CREF(Q) AC-coupled, fi = 19.44 MHz, Vi = 0.2 V (p-p) single-ended RXSD(Q) input STM16; PRBS (223 − 1) RXPD0(Q) to RXPD3(Q), RXFP(Q), RXPAR(Q), RXPC(Q), TXPCO(Q), TXPARERR(Q), TXPRSCL(Q) and RXPRSCL(Q) 100 Ω differential outputs TXPC(Q), TXPD0(Q) to TXPD3(Q) and TXPAR open circuit FIFORESET = LOW normal mode CLKDIR = HIGH co-directional clocking TXSD(Q) and TXSC(Q) external load of 50 Ω to VCC CMOS outputs not loaded 2003 Dec 16 55 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth TXSC t D-C TXSD MGX390 The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential). Fig.27 Serial bus output timing. handbook, full pagewidth RXPC t D-C RXPD0 to RXPD3 RXFP, RXPAR MGX478 The timing is measured from the crossover point of the clock output signal to the crossover point of the data output (all signals are differential). Fig.28 Parallel bus output timing. T clk handbook, full pagewidth TXPCO, TXPC th t su TXPD0 to TXPD3 valid data MCE422 The timing is measured from the crossover point of the reference signal to the crossover point of the input. Fig.29 Parallel bus co-directional (TXPC) and contra-directional (TXPCO) timing. 2003 Dec 16 56 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW APPLICATION INFORMATION The transfer has a first order roll-off (i.e. 20 dB/decade), up to the bandwidth of the VCXO control input. If a second order roll-off is required C2 may be added, as long as C1 + C2 ----------------------------------------- > 2 × f –3dB 2 × π × C1 × C2 Calculations on the clean-up PLL The important specifications of the clean-up PLL are the bandwidth (f−3dB) and the jitter peaking. If these are known, the component parameters can be calculated. First assume that the bandwidth of the VCXO control input (f−3dB(vcxo)) is much higher than f−3dB and C2 is left out. This simplifies the loop into a second order, type II PLL. In a second order PLL, the damping factor ζ determines the amount of peaking. To obtain peaking of less than 0.1 dB, ζ must be higher than 4.3. For peaking of less than 0.05 dB, ζ must be higher than 6. See Fig.30 for an example. Example: The clean-up PLL uses a VCXO with a frequency of 20 MHz and has a gain KVCXO = 2000 Hz/V. The bandwidth of the control input is f−3dB(VCXO) = 10 kHz. Since the reference frequency is 20 MHz, the reference divider ratio RDIV = 1. According to the specification, the maximum allowed jitter peaking is 0.1 dB. To add some margin the design is for less than 0.05 dB peaking, so ζ = 6. Also according to the specification, f−3dB should be less than 100 kHz. To satisfy the conditions as previously described, f−3 dB < 0.5 × f−3 dB(VCXO) < 5 kHz. To cope with component tolerances, f−3dB(VCXO) = 2.5 kHz is chosen. Now R and C1 may be calculated with the following formulas: RDIV × 2 × π × f –3dB R = ----------------------------------------------------K VCXO × I CP 1 × 2 × π × 2500 R = ----------------------------------------------Ω = 78540Ω –6 2000 × 100 × 10 2 K VCXO × I CP × ζ C 1 = -----------------------------------------------------2 2 RDIV × π × ( f –3dB ) 2000 × 100µF × 6 C 1 = ------------------------------------------------- = 116.7nF 2 2 1 × π × 2500 Where: Choosing ICP = 1 mA yields R = 7854 Ω and C1 = 1.167 µF. 2 RDIV = reference divider ratio (1, 2, 4, 8, 16 or 32) To calculate f-3dB and ζ, if R and C1 are known, use the following formulas: f−3dB = clean-up PLL bandwidth in Hz KVCXO = VCXO gain in Hz/V K VCXO × I CP × R f –3dB = -----------------------------------------2 × π × RDIV ICP = charge pump current in A (100 µA or 1 mA, depending on I2C-bus bit CLUPPLLHG) ζ = damping factor. K VCXO × I CP × C1 R ζ = ---- × ----------------------------------------------RDIV 2 These formulas are valid if: ζ >> 1 and f−3dB(VCXO) > 2 × f−3dB and C1 + C2 ---------------------------------------------------- > 2 × f –3dB . 2 × π × R × C1 × C2 2003 Dec 16 57 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth MCE423 Jtransfer [dB] jitter peaking f−3 dB f−3 dB (VCXO) log(f) [Hz] −3 20 dB/decade 40 dB/decade Fig.30 Clean-up PLL jitter transfer. I/O CONFIGURATIONS handbook, full pagewidth SWING CONTROL VCC 50 Ω Vbias 50 Ω 50 Ω transmission lines OUT 50 Ω to highimpedance input 50 Ω OUTQ Iswing in on-chip off-chip Fig.31 Serial RF output (AC-coupled). 2003 Dec 16 58 50 Ω MDB068 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth SWING CONTROL VCC 50 Ω 50 Ω 50 Ω transmission lines OUT 50 Ω to highimpedance input 50 Ω OUTQ Iswing in on-chip off-chip MDB069 Fig.32 Serial RF output (DC-coupled). VCCD handbook, halfpage D 50 Ω 30 kΩ 300 Ω 50 Ω 1.8 pF 30 kΩ DQ VEE MGX391 Fig.33 LVDS input. 2003 Dec 16 59 50 Ω Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW handbook, full pagewidth VCC COMMON MODE CONTROL transmission lines OUT 50 Ω Vref to highimpedance input 100 Ω OUTQ 50 Ω in MGX392 swing-setting on-chip off-chip Fig.34 LVDS output (DC-coupled). handbook, full pagewidth VCC COMMON MODE CONTROL Vbias AC coupling transmission lines 50 Ω 50 Ω OUT 50 Ω Vref OUTQ to highimpedance input 50 Ω in MGX393 swing-setting on-chip off-chip Fig.35 LVDS output (AC-coupled). 2003 Dec 16 60 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW VCC 50 Ω CREF 50 Ω CREFQ VEE Fig.36 Reference clock input. 2003 Dec 16 61 001aaa056 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW PACKAGE OUTLINE HTQFP100: plastic thermal enhanced thin quad flat package; 100 leads; body 14 x 14 x 1 mm; exposed die pad SOT638-1 c y exposed die pad side X Dh A 75 51 76 50 ZE e E HE Eh A A2 (A3) A1 wM θ bp Lp pin 1 index L detail X 26 100 1 25 bp e w M ZD v M A D B HD v M B 0 10 mm scale DIMENSIONS (mm are the original dimensions) A UNIT max. mm 1.2 A1 A2 A3 bp c D(1) Dh E(1) Eh e 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.20 0.09 14.1 13.9 7.1 6.1 14.1 13.9 7.1 6.1 0.5 HD HE 16.15 16.15 15.85 15.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.08 ZD(1) ZE(1) θ 1.15 0.85 7° 0° 1.15 0.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEITA ISSUE DATE 01-03-30 03-04-07 SOT638-1 2003 Dec 16 EUROPEAN PROJECTION 62 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW To overcome these problems the double-wave soldering method was specifically developed. SOLDERING Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 225 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all BGA, HTSSON-T and SSOP-T packages – for packages with a thickness 2.5 mm Manual soldering – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. • below 240 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Dec 16 63 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE REFLOW(2) BGA, HTSSON..T(3), LBGA, LFBGA, SQFP, SSOP..T(3), TFBGA, USON, VFBGA not suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS not suitable(4) suitable PLCC(5), SO, SOJ suitable suitable not recommended(5)(6) suitable SSOP, TSSOP, VSO, VSSOP not recommended(7) suitable CWQCCN..L(8), PMFP(9), WQCCN..L(8) not suitable LQFP, QFP, TQFP not suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 °C ± 10 °C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. 4. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 5. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 6. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 7. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 8. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. ADDITIONAL SOLDERING INFORMATION The die pad has to be soldered to the PCB for thermal and grounding reasons. 2003 Dec 16 64 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Dec 16 65 Philips Semiconductors Preliminary specification 30 Mbit/s to 3.2 Gbit/s A-rate 4-bit fibre optic transceiver TZA3015HW PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Dec 16 66 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands R56/04/pp67 Date of release: 2003 Dec 16 Document order number: 9397 750 12216