PHILIPS TSA5059

INTEGRATED CIRCUITS
DATA SHEET
TSA5059
2.7 GHz I2C-bus controlled
low phase noise frequency
synthesizer
Preliminary specification
File under Integrated Circuits, IC02
1999 Oct 05
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
FEATURES
• Complete 2.7 GHz single chip system
• Optimized for low phase noise
• Selectable divide-by-two prescaler
• Operation up to 2.7 GHz with and without divide-by-two
prescaler
existing ICs. In this case, the step size is twice the
comparison frequency.
• Selectable reference divider ratio
• Compatible with UK-DTT (Digital Terrestrial Television)
offset requirements
The comparison frequency is obtained from an on-chip
crystal oscillator that can also be driven from an external
source. Either the crystal frequency or the comparison
frequency can be switched to the XT/COMP output pin to
drive the reference input of another synthesizer or the
clock input of a digital demodulation IC.
• Selectable crystal/comparison frequency output
• Four selectable charge pump currents
• Four selectable I2C-bus addresses
• Standard and fast mode I2C-bus
Both divided and comparison frequency are compared into
the fast phase detector which drives the charge pump.
The loop amplifier is also on-chip, including the
high-voltage transistor to drive directly the 33 V tuning
voltage, without the need of an external transistor.
• I2C-bus compatible with 3.3 and 5 V microcontrollers
• 5-level Analog-to-Digital Converter (ADC)
• Low power consumption
• 33 V tuning voltage drive
Control data is entered via the I2C-bus; five serial bytes are
required to address the device, select the main divider
ratio, the reference divider ratio, program the four output
ports, set the charge pump current, select the prescaler by
two, select the signal to switch to the XT/COMP output pin
and/or select a specific test mode. Three of the four output
ports can also be used as input ports and a 5-level ADC is
provided. Digital information concerning the input ports
and the ADC can be read out of the TSA5059 on the SDA
line (one status byte) during a READ operation. A flag is
set when the loop is ‘in-lock’ and is read during a READ
operation, as well as the Power-on reset flag. The device
has four programmable addresses, programmed by
applying a specific voltage at pin AS, enabling the use of
multiple synthesizers in the same system.
• Three I/O ports and one output port.
APPLICATIONS
• SAT, TV, VCR and cable tuning systems
• Digital set-top boxes.
GENERAL DESCRIPTION
The TSA5059 is a single chip PLL frequency synthesizer
designed for satellite and terrestrial tuning systems up to
2.7 GHz.
The RF preamplifier drives the 17-bit main divider enabling
a step size equal to the comparison frequency, for an input
frequency up to 2.7 GHz. A fixed divide-by-two additional
prescaler can be inserted between the preamplifier and
the main divider to give a software compatibility with
1999 Oct 05
2
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
QUICK REFERENCE DATA
VCC = 4.5 to 5.5 V; Tamb = −20 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
VCC
supply voltage
ICC
supply current
fi(RF)
RF input frequency
Vi(RF)(rms)
RF input voltage (RMS value)
CONDITIONS
MIN.
TYP.
MAX.
UNIT
4.5
5.0
5.5
V
30
37
45
mA
64
−
2700
MHz
fi(RF) from 64 to 150 MHz;
note 1
12.6
−
300
mV
−25
−
+2.5
dBm
fi(RF) from 150 to 2200 MHz;
note 1
7.1
−
300
mV
−30
−
+2.5
dBm
fi(RF) from 2.2 to 2.7 GHz;
note 1
22.4
−
300
mV
−20
−
+2.5
dBm
Tamb = 25 °C
fxtal
crystal frequency
4
−
16
MHz
Tamb
ambient temperature
−20
−
+85
°C
Tstg
storage temperature
−40
−
+150
°C
Note
1. Asymmetrical drive on pin RFA or RFB; see Fig.3.
ORDERING INFORMATION
TYPE
NUMBER
TSA5059T
TSA5059TS
1999 Oct 05
PACKAGE
NAME
SO16
SSOP16
DESCRIPTION
VERSION
plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
plastic shrink small outline package; 16 leads; body width 4.4 mm
SOT369-1
3
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
BLOCK DIAGRAM
handbook, full pagewidth
3
XTAL
2
XTAL
OSCILLATOR
XT/COMP
REFERENCE
DIVIDER
LOCK
DETECT
4-BIT LATCH
DIGITAL PHASE
COMPARATOR
RFA
RFB
13
14
DIVIDER
1/2
PRE
AMP
17-BIT
DIVIDER
CHARGE PUMP
1-BIT
LATCH
1
17-BIT LATCH
DIVIDE RATIO
33 V
AMP
AS
SCL
SDA
16
6
5
I2C-BUS
TRANSCEIVER
12
11
3-BIT
ADC
3-BIT
INPUT
PORTS
4-BIT LATCH
AND
OUTPUT PORTS
POWER-ON
RESET
MODE
CONTROL
LOGIC
TSA5059
7
8
9
10
FCE120
P3 P2 P1 P0
Fig.1 Block diagram.
1999 Oct 05
VT
4
15
ADC
CP
2-BIT
LATCH
4
VCC
GND
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
PINNING
SYMBOL
PIN
DESCRIPTION
CP
1
charge pump output
XTAL
2
crystal oscillator input
XT/COMP
3
fxtal or fcomp signal output
AS
4
SDA
handbook, halfpage
CP
1
16 VT
I2C-bus address selection input
XTAL
2
15 GND
5
I2C-bus serial data input/output
XT/COMP
3
14 RFB
SCL
6
I2C-bus serial clock input
AS
4
P3
7
general purpose output Port 3
SDA
5
12 VCC
P2
8
general purpose input/output Port 2
SCL
6
11 ADC
P1
9
general purpose input/output Port 1
P3
7
10 P0
P0
10
general purpose input/output Port 0
ADC
11
analog-to-digital converter input
P2
8
VCC
12
supply voltage
RFA
13
RF signal input A
RFB
14
RF signal input B
GND
15
ground supply
VT
16
tuning voltage output
9
P1
FCE121
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
with a reference signal from an external source.
The reference divider can have a dividing ratio selected
from 16 different values between 2 and 320, including the
ratio 24 to cope with the offset requirement of the UK-DTT
system, see Table 8.
The TSA5059 contains all the necessary elements but a
reference source and a loop filter to control a varicap tuned
local oscillator forming a phase locked loop frequency
synthesized source. The IC is designed in a high speed
process with a fast phase detector to allow a high
comparison frequency to reach a low phase noise level on
the oscillator.
The output of the phase comparator drives the
charge pump and the loop amplifier section. This amplifier
has an on-chip high voltage drive transistor which avoids
the use of an additional external component. Pin CP is the
output of the charge pump, and pin VT is the pin to drive
the tuning voltage to the varicap diode of the Voltage
Controlled Oscillator (VCO). The loop filter has to be
connected between pins CP and VT.
The block diagram is shown in Fig.1. The RF signal is
applied at pins RFA and RFB. Thanks to the input
preamplifier a good sensitivity is provided. The output of
the preamplifier is fed to the 17-bit programmable divider
either through a divide-by-two prescaler or directly.
Because of the internal high speed process, the RF divider
is working for a frequency up to 2.7 GHz, without the need
for the divide-by-two prescaler to be used. This prescaler
is present on chip for compatibility reasons with existing
circuits.
In addition, it is possible to drive another PLL synthesizer,
or the clock input of a digital demodulation IC, from the
pin XT/COMP. It is possible to select by software either
fxtal, the crystal oscillator frequency or fcomp, the frequency
present after the reference divider at this pin. It is also
possible to switch off this output, in case it is not used.
The output of the 17-bit programmable divider fDIV is fed
into the phase comparator, where it is compared in both
phase and frequency with the comparison frequency fcomp.
This frequency is derived from the signal present at
pin XTAL, fxtal, divided down in the reference divider. It is
possible either to connect a quartz crystal to pin XTAL and
then using the on-chip crystal oscillator, or to feed this pin
1999 Oct 05
13 RFA
TSA5059
For test and alignment purposes, it is possible to release
the tuning voltage output to be able to apply an external
voltage on it, to select one of the three charge pump test
modes, and to monitor half the fDIV at Port P0. See
Table 10 for all possible modes.
5
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
The TSA5059 can also be partly programmed on the
condition that the first data byte following the address is
byte 2 or byte 4. The meaning of the bits in the data bytes
is given in Table 1. The first bit of the first data byte
transmitted indicates whether byte 2 (first bit is logic 0) or
byte 4 (first bit is logic 1) will follow. Until an I2C-bus STOP
condition is sent by the controller, additional data bytes
can be entered without the need to re-address the device.
To allow a smooth frequency sweep for fine tuning, and
while the data of the dividing ratio of the main divider is in
data bytes 2, 3 and 4, it is necessary for changing the
frequency to send the data bytes 2 to 5 in a repeated
sending, or to finish an incomplete transmission by a
STOP condition. Repeated sending of data bytes 2 and 3
without ending the transmission does not change the
dividing ratio. To illustrate, the following data sequences
will change the dividing ratio:
Four open-collector output ports are provided on the IC for
general purpose; three of these can also be used as input
ports. A 3-bit ADC is also available.
The TSA5059 is controlled via the two-wire I2C-bus.
For programming, there is one 7-bit module address and
the R/W bit for selecting READ or WRITE mode. To be
able to have more than one synthesizer in an I2C-bus
system, one of four possible addresses is selected
depending on the voltage applied at pin AS (see Table 3).
The TSA5059 fulfils the fast mode I2C-bus, according to
the Philips I2C-bus specification. The I2C-bus interface is
designed in such a way that pins SCL and SDA can be
connected either to 5 or to 3.3 V pulled-up I2C-bus lines,
allowing the PLL synthesizer to be connected directly to
the bus lines of a 3.3 V microcontroller.
WRITE mode: R/W = 0
• Bytes 2, 3, 4 and 5
After the address transmission (first byte), data bytes can
be sent to the device (see Table 1). Four data bytes are
needed to fully program the TSA5059. The bus transceiver
has an auto-increment facility that permits programming of
the TSA5059 within one single transmission
(address + 4 data bytes).
• Bytes 4, 5, 2 and 3
• Bytes 2, 3, 4 and STOP
• Bytes 4, 5, 2 and STOP
• Bytes 2, 3 and STOP
• Bytes 2 and STOP
• Bytes 4 and STOP.
Table 1
Write data format
BYTE
DESCRIPTION
MSB(1)
LSB
CONTROL BIT
1
address
1
1
0
0
0
MA1
MA0
0
A
2
programmable divider
0
N14
N13
N12
N11
N10
N9
N8
A
3
programmable divider
N7
N6
N5
N4
N3
N2
N1
N0
A
4
control data
1
N16
N15
PE
R3
R2
R1
R0
A
5
control data
C1
C0
XCE
XCS
P3
P2/T2
P1/T1
P0/T0
A
Note
1. MSB is transmitted first.
1999 Oct 05
6
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
Table 2
TSA5059
Explanation of Table 1
BIT
DESCRIPTION
MA1 and MA0
programmable address bits; see Table 3
A
acknowledge bit
N16 to N0
programmable main divider ratio control bits; N = N16 × 216 + N15 × 215 + ... + N1 × 21 + N0
PE
prescaler enable (prescaler by 2 is active when bit PE = 1)
R3 to R0
programmable reference divider ratio control bits; see Table 8
C1 and C0
charge pump current select bits; see Table 9
XCE
XT/COMP enable; XT/COMP output active when bit XCE = 1; see Table 10
XCS
XT/COMP select; signal select when bit XCE = 1, test mode enable when bit XCE = 0; see Table 10
T2, T1 and T0
test mode select when bit XCE = 0 and bit XCS = 1; see Table 10
P3, P2 and P1
Port P3, P2 and P1 output states
P0
Port P0 output state, except in test mode; see Table 10
Address selection (see Table 3)
The module address contains programmable address bits (MA1 and MA0), which offer the possibility of having
up to 4 synthesizers in one system. The relationship between MA1 and MA0 and the input voltage at pin AS is given in
Table 3.
Table 3
Address selection
MA1
MA0
VOLTAGE APPLIED TO PIN AS
0
0
0 to 0.1VCC
0
1
open-circuit
1
0
0.4VCC to 0.6VCC; note 1
1
1
0.9VCC to VCC
Note
1. This address is selected by connecting a 15 kΩ resistor between pin AS and pin VCC.
Status at Power-On Reset (POR)
At power-on or when the supply voltage drops below approximately 2.75 V, internal registers are set according to
Table 4.
Table 4
Status at Power-on reset; note 1
BYTE
DESCRIPTION
MSB
LSB
CONTROL BIT
1
address
1
1
0
0
0
MA1
MA0
0
A
2
programmable divider
0
X
X
X
X
X
X
X
A
3
programmable divider
X
X
X
X
X
X
X
X
A
4
control data
1
X
X
X
X
X
X
X
A
1
X(2)
1(2)
X(2)
X(2)
A
5
control data
0
0
0
Notes
1. X = don’t care.
2. At Power-on reset, all output ports are in high-impedance state.
1999 Oct 05
7
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
READ mode: R/W = 1
TSA5059
It is reset to logic 0 when an end of data is detected by the
TSA5059 (end of a READ sequence).
Data can be read out of the TSA5059 by setting the
bit R/W to logic 1 (see Table 5). After the slave address
has been recognized, the TSA5059 generates an
acknowledge pulse and the first data byte (status word) is
transferred on the SDA line (MSB first). Data is valid on the
SDA line during a HIGH-level of the SCL clock signal.
Control of the loop is made possible with the in-lock flag
which indicates (bit FL = 1) when the loop is phase-locked.
The bits I2, I1 and I0 represent the status of the I/O ports
P2, P1 and P0 respectively. A logic 0 indicates a
LOW-level and a logic 1 indicates a HIGH-level.
A second data byte can be read out of the TSA5059 if the
controller generates an acknowledge on the SDA line.
End of transmission will occur if no acknowledge from the
controller occurs.The TSA5059 will then release the data
line to allow the controller to generate a STOP condition.
When ports P0 to P2 are used as inputs, they must be
programmed in their high-impedance state.
A built-in 5-level ADC is available at pin ADC. This
converter can be used to feed AFC information to the
microcontroller through the I2C-bus. The relationship
between bits A2, A1, A0 and the input voltage at pin ADC
is given in Table 7.
The POR flag is set to logic 1 when VCC drops below
approximately 2.75 V and at power-on.
Table 5
Read data format
BYTE
MSB(1)
DESCRIPTION
1
address
2
status byte
1
0
0
0
MA1
MA0
1
A
POR
FL
I2
I1
I0
A2
A1
A0
−
1. MSB is transmitted first.
Explanation of Table 5
BIT
DESCRIPTION
A
acknowledge bit
MA1 and MA0
programmable address bits; see Table 3
POR
Power-on reset flag (bit POR = 1 on power-on)
FL
in-lock flag (bit FL = 1 when the loop is phase-locked)
I2, I1 and I0
digital information for I/O ports P2, P1 and P0 respectively
A2, A1 and A0
digital outputs of the 5-level ADC; see Table 7
Table 7
ADC levels
VOLTAGE APPLIED TO PIN ADC(1)
A2
A1
A0
1
0
0
0.6VCC to VCC
0
1
1
0.45VCC to 0.6VCC
0
1
0
0.3VCC to 0.45VCC
0
0
1
0.15VCC to 0.3VCC
0
0
0
0 to 0.15VCC
Note
1. Accuracy is ±0.03VCC.
1999 Oct 05
CONTROL BIT
1
Note
Table 6
LSB
8
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
Reference divider ratio
Table 8 shows the different dividing ratios and the
corresponding comparison frequencies and step size,
assuming the device is provided with a 4 MHz signal at
pin XTAL.
The reference divider ratio is set by 4 bits in the WRITE
mode, giving 16 different ratios which allow to adjust the
comparison frequency to different values, depending on
the compromise which has to be found between step size
and phase noise.
Table 8
TSA5059
The dividing ratio of 24 is implemented to fulfil the UK-DTT
recommendation regarding offset frequency of 1⁄6 MHz.
Reference dividing ratios
STEP
R3
R2
R1
R0
RATIO
COMPARISON
FREQUENCY(1)
BIT PE = 0(1)
BIT PE = 1(1)
0
0
0
0
2
2 MHz
2 MHz
4 MHz
0
0
0
1
4
1 MHz
1 MHz
2 MHz
0
0
1
0
8
500 kHz
500 kHz
1 MHz
0
0
1
1
16
250 kHz
250 kHz
500 kHz
0
1
0
0
32
125 kHz
125 kHz
250 kHz
0
1
0
1
64
62.5 kHz
62.5 kHz
125 kHz
0
1
1
0
128
31.25 kHz
31.25 kHz
62.5 kHz
0
1
1
1
256
15.625 kHz
15.625 kHz
31.25 kHz
1
0
0
0
24
166.67 kHz
166.67 kHz
333.33 kHz
1
0
0
1
5
800 kHz
800 kHz
1.6 MHz
1
0
1
0
10
400 kHz
400 kHz
800 kHz
1
0
1
1
20
200 kHz
200 kHz
400 kHz
1
1
0
0
40
100 kHz
100 kHz
200 kHz
1
1
0
1
80
50 kHz
50 kHz
100 kHz
1
1
1
0
160
25 kHz
25 kHz
50 kHz
1
1
1
1
320
12.5 kHz
12.5 kHz
25 kHz
Note
1. Only valid when the IC is used with a 4 MHz crystal.
Charge pump current
The charge pump current can be chosen from 4 different values depending on the value of bits C1 and C0 in the I2C-bus
byte 4, according to Table 9.
Table 9
Charge pump current
C1
Icp (µA) (absolute value)
C0
MIN.
TYP.
MAX.
0
0
100
135
170
0
1
210
280
350
1
0
450
600
750
1
1
920
1230
1560
1999 Oct 05
9
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
for which this relation is only valid for an RF frequency up
to 2.0 GHz and in which it is necessary to select a fixed
divide-by-two prescaler for frequencies between 2.0 and
2.7 GHz.
XT/COMP frequency output
It is possible to output either the crystal or the comparison
frequency at this pin to be used in the application, for
example to drive a second PLL synthesizer, saving a
quartz crystal in the bill of material. To output fxtal, it is
necessary to set bit XCE to logic 1 and bit XCS to logic 0,
or bit XCE to logic 0 and bit XCS to logic 1 during a test
mode, while to output fcomp, it is necessary to set both
bits XCE and XCS to logic 1.
The prescaler is selected by setting bit PE to logic 1 and
it is not in use if bit PE is set to logic 0.
For new designs, and especially if it is important to reach
a low phase noise on the controlled VCO, it is
recommended to set bit PE to logic 0, and not to use the
prescaler, allowing the comparison frequency to be equal
to the step size, whatever the RF frequency is between
64 and 2700 MHz.
If the output signal at this pin is not used, it is
recommended to disable it, setting both bits XCE and XCS
to logic 0. Table 10 shows how this pin is programmed.
At power-on, the XT/COMP output is set, with the fxtal
signal selected.
Test modes
It is possible to access the test modes setting bit XCE to
logic 0 and bit XCS to logic 1. One specific test mode is
then selected using bits T2, T1 and T0, as described in
Table 10.
Prescaler enable
Even if the TSA5059 is able to work with the relation
fcomp = step size for an input frequency up to 2.7 GHz, this
IC is designed to be backward compatible with existing ICs
Table 10 XT/COMP and test mode selection; note 1
XCE
XCS
T2
T1
T0
XT/COMP OUTPUT
0
0
X
X
X
disabled
normal operation
1
0
X
X
X
fxtal
normal operation
1
1
X
X
X
fcomp
normal operation
0
1
0
0
0
fxtal
test operation: charge pump sink;
status byte: bit FL = 1
0
1
0
0
1
fxtal
test operation: charge pump source;
status byte: bit FL = 0
0
1
0
1
0
fxtal
test operation: charge pump disabled;
status byte: bit FL = 0
0
1
0
1
1
fxtal
test operation: 1⁄2fDIV switched to Port P0
0
1
1
X
X
fxtal
test operation: tuning voltage (pin VT) is
off (high-impedance); note 2
Notes
1. X = don’t care.
2. Status at Power-on reset.
1999 Oct 05
10
TEST MODE
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); note 1.
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
−0.3
+6.0
V
CP, XTAL, XT/COMP, AS, P0, P1,
P2, P3, ADC, RFA and RFB
−0.3
VCC + 0.3
V
SCL and SDA
−0.3
+6.0
V
VT
−0.3
+35
V
−1.0
+10.0
mA
−1.0
+20.0
mA
VCC
supply voltage
V(n)
voltage on pins
IO(SDA)
serial data output current
IO(Px)
P0, P1, P2 and P3 output current
IO(ΣPx)
sum of currents in P0, P1, P2 and P3
−
50.0
mA
Tamb
ambient temperature
−20
+85
°C
Tstg
storage temperature
−40
+150
°C
Tj(max)
maximum junction temperature
−
150
°C
tsc
short-circuit time
−
10
s
port switched on
each pin to VCC or GND
Note
1. Maximum ratings cannot be exceeded, not even momentarily without causing irreversible IC damage. Maximum
ratings cannot be accumulated.
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be completely safe, it is
desirable to take normal precautions appropriate to handling integrated circuits.
THERMAL CHARACTERISTICS
SYMBOL
Rth(j-a)
1999 Oct 05
PARAMETER
CONDITIONS
VALUE
UNIT
TSA5059T (SOT109-1; SO16)
115
K/W
TSA5059TS (SOT369-1; SSOP16)
144
K/W
thermal resistance from junction to ambient
in free air
11
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
CHARACTERISTICS
VCC = 4.5 to 5.5 V; Tamb = −20 to +85 °C; fxtal = 4 MHz; measured according to Fig.4; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply (pin VCC)
VCC
supply voltage
4.5
5.0
5.5
V
ICC
supply current
30
37
45
mA
VCC(POR)
supply voltage below which POR is active Tamb = 25 °C
−
2.75
−
V
64
−
2700
MHz
fi(RF) between 64 and
150 MHz; note 1
12.6
−
300
mV
−25
−
+2.5
dBm
fi(RF) between 150 and
2200 MHz; note 1
7.1
−
300
mV
−30
−
+2.5
dBm
fi(RF) between 2.2 and
2.7 GHz; note 1
22.4
−
300
mV
−20
−
+2.5
dBm
Tamb = 25 °C
RF inputs (pins RFA and RFB)
fi(RF)
RF input frequency
Vi(RF)(rms)
RF input voltage (RMS value)
Zi(RF)
RF input impedance
see Fig.7
−
−
−
Ω
Ci(RF)
RF input capacitance
see Fig.7
−
−
−
pF
MDR
main divider ratio
prescaler disabled
64
−
131071
prescaler enabled
128
−
262142
4
−
16
Crystal oscillator (pin XTAL)
fxtal
crystal frequency
MHz
ZXTAL
crystal oscillator negative impedance
4 MHz crystal
400
680
−
Ω
ZXTAL
recommended crystal series resistance
4 MHz crystal
−
−
200
Ω
PXTAL
crystal drive level
4 MHz crystal; note 2
−
40
−
µW
fi(ext)
external reference input frequency
note 3
2
−
20
MHz
Vi(ext)(p-p)
external reference input voltage
(peak-to-peak value)
note 3
200
−
500
mV
−
−
2
MHz
−
−157
−
dBc/Hz
Phase comparator and charge pump
fcomp
comparison frequency
Ncomp
equivalent phase noise at the phase
detector input
Icp
charge pump current
Icpl
1999 Oct 05
fcomp = 250 kHz;
C1 = C0 = 1;
in the loop bandwidth
C1 = 0; C0 = 0
100
135
170
µA
C1 = 0; C0 = 1
210
280
350
µA
C1 = 1; C0 = 0
450
600
750
µA
C1 = 1; C0 = 1
920
1230
1540
µA
−10
0
+10
nA
charge pump leakage current
12
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
SYMBOL
TSA5059
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Tuning voltage output (pin VT)
IlO(off)
leakage current when switched off
XCE = 0; XCS = 1;
T2 = 1; VVT = 33 V
−
−
−10
µA
VO
output voltage
when the loop is
locked; normal mode;
VVT = 33 V; pull-up
resistor of 27 kΩ
0.25
−
32.7
V
XCE = 1
−
400
−
mV
XT/COMP output (pin XT/COMP)
VO(p-p)
AC output voltage (peak-to-peak value)
Input/output and output ports (pins P0, P1, P2 and P3)
IlO
port leakage current
port off; VO = VCC
−
−
10
µA
VO(sat)
output port saturation voltage
port on; Isink = 10 mA
−
0.2
0.4
V
VIL
LOW-level input voltage
−
−
1.5
V
VIH
HIGH-level input voltage
3.0
−
−
V
ADC input (pin ADC)
ILIH
HIGH-level input leakage current
VADC = VCC
−
−
10
µA
ILIL
LOW-level input leakage current
VADC = 0 V
−10
−
−
µA
Address selection (pin AS)
ILIH
HIGH-level input leakage current
VAS = VCC
−
−
1
mA
ILIL
LOW-level input leakage current
VAS = 0 V
−0.5
−
−
mA
SCL and SDA inputs (pins SCL and SDA)
VIL
LOW-level input voltage
−
−
1.5
V
VIH
HIGH-level input voltage
2.3
−
−
V
ILIH
HIGH-level input leakage current
VCC = 5.5 V
−
−
10
µA
VCC = 0 V
−
−
10
µA
−10
−
−
µA
−
−
400
kHz
Isink = 3 mA
−
−
0.4
V
Isink = 6 mA
−
−
0.6
V
ILIL
LOW-level input leakage current
fSCL
SCL clock frequency
VIH = 5.5 V
VIL = 0 V; VCC = 5.5 V
SDA output (pin SDA)
VO(ack)
output voltage during acknowledge
Notes
1. Asymmetrical drive on pin RFA or RFB; see Fig.3.
2. The drive level is expected with the crystal at series resonance with a series resistance of 50 Ω. The value will be
different with another crystal.
3. To drive pin XTAL from the pin XT/COMP of another TSA5059, couple the signal through a capacitor of 1 nF
(to remove the DC level), in series with an 1.2 kΩ resistor, see Fig.5.
1999 Oct 05
13
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
FCE416
+6
handbook, full pagewidth
Vi(RF)
(dBm)
0
−6
−12
guaranteed area
−18
−24
−30
−36
−42
−48
−54
−60
0
500
1000
1500
2000
2500
3000
f (MHz)
Fig.3 Sensitivity curve.
1999 Oct 05
14
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
APPLICATION INFORMATION
An example of a typical application is given in Fig.4. In this application the VCO centre frequency is 1.5 GHz, with a slope
of 100 MHz/V; the expected loop bandwidth is 10 kHz with a charge pump current of 555 µA and fcomp of 250 kHz. Filter
components need to be adapted to each application depending on the VCO characteristics and the required performance
of the loop.
33 V
5V
handbook, full pagewidth
27 kΩ
2.7 kΩ
3.9 kΩ
47 nF
CP
4 MHz
18 pF XTAL
XT/COMP
AS
SDA
MICROCONTROLLER
P3
tuning
voltage
1
16
2
15
3
14
4
13
5
SCL
1 nF
2.2 nF
TSA5059
12
6
11
7
10
8
9
P2
VT
GND
RFB
1 nF
RFA
1 nF
VCC
10 nF
P1 P0 ADC
VCO
output
VCO
FCE123
Fig.4 Typical application.
Loop bandwidth
It is however possible to use a crystal with an higher
frequency (up to 16 MHz) to improve the noise
performance. When choosing a crystal, one should take
notice to select a crystal able to withstand the drive level of
the TSA5059 without suffering from accelerated ageing.
Most of the applications the TSA5059 are dedicated for
require a large loop bandwidth, in the order of a few kHz to
a few tens of kHz. The calculation of the loop filter
elements has to be done for each application, while it
depends on the VCO slope and phase noise, as well as the
reference frequency and charge pump current.
A simulation of the loop can easily be done by using the
SIMPATA software from Philips.
It is also possible to feed pin XTAL with an external signal
between 2 and 20 MHz, coming from an external oscillator
or from the pin XT/COMP of another TSA5059, when more
than one synthesizer is present in the same application.
Then the application given in Fig.5 should be used.
Reference source
If the signal at pin XT/COMP is not used in an application,
the output should be switched off (XCE = 0, XCS = 0).
This pin should then be open.
The TSA5059 is well suited to be used with a 4 MHz
crystal connected to pin XTAL. Philips crystal ordering
code 4322 143 04093 is recommended in this case.
1999 Oct 05
15
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
handbook, full pagewidth
4 MHz
1
16
2
15
14
3
14
13
4
1.0 nF
2
18 pF
1
16
15
1.2 kΩ
3
4
5
TSA5059
13
TSA5059
12
5
6
11
6
11
7
10
7
10
8
9
8
9
12
FCE124
Fig.5 Application for using one crystal with two TSA5059s.
If I2C-bus crosstalk is still a problem, it is possible not to
use the internal amplifier, and to replace it with a NMOS
transistor in the application as given in Fig.6. In this case
the pin VT is left open, and it is possible to implement on
the PCB the foot print for a jumper between the tuning
voltage line and pin VT to be able to choose either the
internal amplifier (mounting the jumper and not the NMOS
transistor) or the external amplifier (mounting the NMOS
transistor and not the jumper). It is recommended to use a
BSH111 or BSH121 N-channel MOS transistor. The
threshold voltage of the transistor has to be lower than
2.0 V.
I2C-bus crosstalk and loop amplifier
The TSA5059 includes a loop amplifier between pin CP
and pin VT. While this amplifier shares the same ground
pin as the I2C-bus, there may be some I2C-bus crosstalk.
The best way to avoid any I2C-bus crosstalk, both in the
PLL IC and in the application (i.e. parasitic coupling
between the I2C-bus lines and the VCO coil), is to avoid
the I2C-bus signal to come in the RF part by using an
I2C-bus gate that allows only the messages for the PLL to
go to the PLL, and to avoid unnecessary repeated
sending. Such a gate is integrated in most of the Philips
digital demodulators.
1999 Oct 05
16
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
33 V
handbook, full pagewidth
27 kΩ
2.7 kΩ
3.9 kΩ
47 nF
1 nF
tuning
voltage
2.2 nF
2.7
pF
jumper
(optional)
BSH111
or BSH121
CP
1
16
VCO
VT
FCE417
Fig.6 Application for using an external loop amplifier.
RF input impedance
1
handbook, full pagewidth
0.5
2
0.2
5
10
+j
0
0.2
0.5
1
2
5
64MHz
10
−j
10
2.7GHz
5
0.2
2
0.5
1
Fig.7 RF input impedance.
1999 Oct 05
17
FCE418
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
PACKAGE OUTLINES
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.069
0.010 0.057
0.004 0.049
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.16
0.15
0.050
0.039
0.016
0.028
0.020
0.01
0.01
0.004
0.028
0.012
inches
0.244
0.041
0.228
θ
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07S
MS-012AC
1999 Oct 05
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-01-23
97-05-22
18
o
8
0o
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm
D
SOT369-1
E
A
X
c
y
HE
v M A
Z
9
16
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
1
8
detail X
w M
bp
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.5
0.15
0.00
1.4
1.2
0.25
0.32
0.20
0.25
0.13
5.30
5.10
4.5
4.3
0.65
6.6
6.2
1.0
0.75
0.45
0.65
0.45
0.2
0.13
0.1
0.48
0.18
10
0o
Note
1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
EIAJ
ISSUE DATE
94-04-20
95-02-04
SOT369-1
1999 Oct 05
EUROPEAN
PROJECTION
19
o
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
SOLDERING
TSA5059
If wave soldering is used the following conditions must be
observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering
The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Wave soldering
Manual soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
1999 Oct 05
20
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
REFLOW(1)
WAVE
BGA, SQFP
not suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
suitable(2)
suitable
suitable
suitable
not
recommended(3)(4)
suitable
not
recommended(5)
suitable
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
1999 Oct 05
21
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
TSA5059
DEFINITIONS
Data sheet status
Objective specification
This data sheet contains target or goal specifications for product development.
Preliminary specification
This data sheet contains preliminary data; supplementary data may be published later.
Product specification
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
1999 Oct 05
22
Philips Semiconductors
Preliminary specification
2.7 GHz I2C-bus controlled low phase
noise frequency synthesizer
NOTES
1999 Oct 05
23
TSA5059
Philips Semiconductors – a worldwide company
Argentina: see South America
Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140,
Tel. +61 2 9704 8141, Fax. +61 2 9704 8139
Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213,
Tel. +43 1 60 101 1248, Fax. +43 1 60 101 1210
Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6,
220050 MINSK, Tel. +375 172 20 0733, Fax. +375 172 20 0773
Belgium: see The Netherlands
Brazil: see South America
Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor,
51 James Bourchier Blvd., 1407 SOFIA,
Tel. +359 2 68 9211, Fax. +359 2 68 9102
Canada: PHILIPS SEMICONDUCTORS/COMPONENTS,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
China/Hong Kong: 501 Hong Kong Industrial Technology Centre,
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Tel. +852 2319 7888, Fax. +852 2319 7700
Colombia: see South America
Czech Republic: see Austria
Denmark: Sydhavnsgade 23, 1780 COPENHAGEN V,
Tel. +45 33 29 3333, Fax. +45 33 29 3905
Finland: Sinikalliontie 3, FIN-02630 ESPOO,
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Tel. +33 1 4099 6161, Fax. +33 1 4099 6427
Germany: Hammerbrookstraße 69, D-20097 HAMBURG,
Tel. +49 40 2353 60, Fax. +49 40 2353 6300
Hungary: see Austria
India: Philips INDIA Ltd, Band Box Building, 2nd floor,
254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025,
Tel. +91 22 493 8541, Fax. +91 22 493 0966
Indonesia: PT Philips Development Corporation, Semiconductors Division,
Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510,
Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Italy: PHILIPS SEMICONDUCTORS, Via Casati, 23 - 20052 MONZA (MI),
Tel. +39 039 203 6838, Fax +39 039 203 6800
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5057
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
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Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Middle East: see Italy
Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB,
Tel. +31 40 27 82785, Fax. +31 40 27 88399
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Tel. +64 9 849 4160, Fax. +64 9 849 7811
Norway: Box 1, Manglerud 0612, OSLO,
Tel. +47 22 74 8000, Fax. +47 22 74 8341
Pakistan: see Singapore
Philippines: Philips Semiconductors Philippines Inc.,
106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI,
Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474
Poland: Al.Jerozolimskie 195 B, 02-222 WARSAW,
Tel. +48 22 5710 000, Fax. +48 22 5710 001
Portugal: see Spain
Romania: see Italy
Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW,
Tel. +7 095 755 6918, Fax. +7 095 755 6919
Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762,
Tel. +65 350 2538, Fax. +65 251 6500
Slovakia: see Austria
Slovenia: see Italy
South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale,
2092 JOHANNESBURG, P.O. Box 58088 Newville 2114,
Tel. +27 11 471 5401, Fax. +27 11 471 5398
South America: Al. Vicente Pinzon, 173, 6th floor,
04547-130 SÃO PAULO, SP, Brazil,
Tel. +55 11 821 2333, Fax. +55 11 821 2382
Spain: Balmes 22, 08007 BARCELONA,
Tel. +34 93 301 6312, Fax. +34 93 301 4107
Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM,
Tel. +46 8 5985 2000, Fax. +46 8 5985 2745
Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH,
Tel. +41 1 488 2741 Fax. +41 1 488 3263
Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1,
TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
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MIDDLESEX UB3 5BX, Tel. +44 208 730 5000, Fax. +44 208 754 8421
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Uruguay: see South America
Vietnam: see Singapore
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
Internet: http://www.semiconductors.philips.com
SCA 68
© Philips Electronics N.V. 1999
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Printed in The Netherlands
545004/01/pp24
Date of release: 1999
Oct 05
Document order number:
9397 750 05435