UC1854A/B UC2854A/B UC3854A/B Enhanced High Power Factor Preregulator FEATURES DESCRIPTION • Controls Boost PWM to Near Unity Power Factor • Limits Line Current Distortion To <3% • World-Wide Operation Without Switches • Accurate Power Limiting • Fixed Frequency Average Current Mode Control • High Bandwidth (5MHz), Low Offset Current Amplifier • Integrated Current and Voltage Amp Output Clamps • Multiplier Improvements: Linearity, 500mV VAC Offset (eliminates external resistor), 0-5V Multout Common Mode Range • VREF "GOOD" Comparator • Faster and Improved Accuracy ENABLE Comparator • UVLO Threshold Options (16/10V / 10.5/10V) • 300µA Startup Supply Current UC1854A UC1854B UVLO Turn on UVLO Turn off 16V 10V 10.5V 10V The UC1854A/B products are pin compatible enhanced versions of the UC1854. Like the UC1854, these products provide all of the functions necessary for active power factor corrected preregulators. The controller achieves near unity power factor by shaping the AC input line current waveform to correspond to the AC input line voltage. To do this the UC1854A/B uses average current mode control. Average current mode control maintains stable, low distortion sinusoidal line current without the need for slope compensation, unlike peak current mode control. The UC1854A/B products improve upon the UC1854 by offering a wide bandwidth, low offset Current Amplifier, a faster responding and improved accuracy enable comparator, a V REF "good" comparator, UVLO threshold options (16/10V for offline, 10.5/10V for startup from an auxiliary 12V regulator), lower startup supply current, and an enhanced multiply/divide circuit. New features like the amplifier output clamps, improved amplifier current sinking capability, and low offset VAC pin reduce the external component count while improving performance. Improved common mode input range of the Multiplier output/Current Amp input allow the designer greater flexibility in choosing a method for current sensing. Unlike its predecessor, RSET controls only oscillator charging current and has no effect on clamping the maximum multiplier output current. This current is now clamped to a maximum of 2 * IAC at all times which simplifies the design process and provides foldback power limiting during brownout and extreme low line conditions. A 1% 7.5V reference, fixed frequency oscillator, PWM, Voltage Amplifier with softstart, line voltage feedforward (VRMS squarer), input supply voltage clamp, and over current comparator round out the list of features. BLOCK DIAGRAM UDG-93001-1 6/98 UC1854A/B UC2854A/B UC3854A/B ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . GT Drv Current, Continuous . . . . . . . . . . . . . GT Drv Current, 50% Duty Cycle. . . . . . . . . . Input Voltage, VSENSE, VRMS . . . . . . . . . . . . . Input Voltage, ISENSE, Mult Out . . . . . . . . . . . Input Voltage, PKLMT . . . . . . . . . . . . . . . . . . Input Current, RSET, IAC , PKLMT, ENA . . . . . Power Dissipation . . . . . . . . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . Lead Temperature (Soldering, 10 Seconds) . . . . . . . . . . . 22V . . . . . . . . . . 0.5A . . . . . . . . . . 1.5A . . . . . . . . . . 11V . . . . . . . . . . 11V . . . . . . . . . . . 5V . . . . . . . . . 10mA . . . . . . . . . . . 1W –65°C to +150°C . . . . . . . . +300°C Note 1: All voltages with respect to Gnd (Pin 1). Note 2: All currents are positive into the specified terminal. Note 3: ENA imput is internally clamped to approximately 10V. Note 4: Consult Unitrode Integrated Circuits databook for information regarding thermal specifications and limitations of packages. CONNECTION DIAGRAMS DIL–16 & SOIC-16 (Top View) J, N & DW Packages PLCC-20 & LCC-20 (Top View) Q & L Packages PACKAGE PIN FUNCTION FUNCTION PIN N/C Gnd PKLMT CA Out ISENSE N/C Mult Out IAC VA Out VRMS N/C VREF ENA VSENSE RSET N/C SS CT VCC GT Drv 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 ELECTRICAL CHARACTERISTICS Unless otherwise stated, VCC=18V, RT=8.2k, CT=1.5nF, PKLMT=1V,o VRMS =1.5V, o IAC=100µA, ISENSE=0V, CA Out=3.5V, VA Out=5V, VSENSE=3V, –55 C<TA<125 C for the UC1854A/B, –40oC<TA<85oC for the UC2854A/B, and 0oC<TA<70oC for the UC3854A/B, and TA =TJ. PARAMETER OVERALL Supply Current, Off Supply Current, On VCC Turn-On Threshold VCC Turn-Off Threshold VCC Clamp VOLTAGE AMPLIFIER Input Voltage VSENSE Bias Current Open Loop Gain VOUT High VOUT Low Output Short Circuit Current Gain Bandwidth Product TEST CONDITIONS MIN TYP MAX UNITS 400 18 17.5 11.2 9 18 250 12 16 10.5 10 20 µA mA V V V V 3.0 –25 100 6 0.3 1.5 1 3.1 500 CAO, VAO = 0V, VCC = UVLO - 0.3V UC1854A UC1854B UC1854A / B I(VCC) = ICC(on) + 5mA VOUT = 2 to 5V ILOAD = –500µA ILOAD = 500µA VOUT = 0V Fin = 100kHz, 10mV p-p, (Note 1) 2 2.9 –500 70 22 0.5 3.5 V nA dB V V mA mHz UC1854A/B UC2854A/B UC3854A/B Unless otherwise stated, VCC=18V, RT=8.2k, CT=1.5nF, PKLMT=1V, VRMS=1.5V, ELECTRICAL =0V, CA Out=3.5V, VA Out=5V, VSENSE=3V, –55oC<TA<125oC for the CHARACTERISTICS (cont.) I AC=100µA, ISENSE o o o o UC1854A/B, –40 C<TA <85 C for the UC2854A/B, and 0 C<TA<70 C for the UC3854A/B, and TA =TJ. PARAMETER CURRENT AMPLIFIER Input Offset Voltage Input Bias Current(sense) Open Loop Gain VOUT High VOUT Low Output Short Circuit Current Common Mode Range Gain Bandwidth Product REFERENCE Output Voltage Load Regulation Line Regulation Short Circuit Current OSCILLATOR Initial Accuracy Voltage Stability Total Variation Ramp Amplitude (p-p) Ramp Valley Voltage ENABLE / SOFTSTART / CURRENT LIMIT Enable Threshold Enable Hysteresis Enable Input Bias Current Propagation Delay to Disable SS Charge Current PKLMT Offset Voltage PKLMT Input Current PKLMT Propagation Delay MULTIPLIER Output Current - IAC Limited Output Current - Zero Output Current - Power Limited Output Current Gain Constant TEST CONDITIONS VCM = 0V MIN TA = +25°C OverTemp VCM = 0V VCM = 0V, VOUT = 2 to 6V ILOAD = –500µA ILOAD = 500µA VOUT = 0V −4 –5.5 –500 80 TYP 110 8 0.3 1.5 MAX UNITS 0 0 500 mV mV nA dB V V mA V mHz 0.5 3.5 5 Fin = 100kHz, 10mV p-p, (Note 1) –0.3 3 5 IREF = 0mA, TA = 25oC IREF = 0mA IREF = 1 to 10mA VCC = 12 to 18V VREF = 0V 7.4 7.35 0 0 25 7.5 7.5 8 14 35 7.6 7.65 20 25 60 V V mV mV mA 85 100 1 115 kHz % kHz V V TA = 25oC VCC = 12 to 18V Line, Temp 80 4.9 0.8 2.35 VFAULT = 2.5V VENABLE = 0V Enable Overdrive = –100mV,(Note 1) VSOFTSTART = 2.5V 10 –15 120 5.9 1.3 2.55 2.8 V 500 –2 300 14 600 –5 mV µA ns VPKLMT = –0.1V (Note 1) –200 –100 150 IAC =100µA, VRMS = 1V, RSET = 10k IAC =0µA, RSET = 10k VRMS = 1.5V, Va = 6V VRMS = 1.5V, Va = 2V VRMS = 1.5V, Va = 5V VRMS = 5V, Va = 2V VRMS = 5V, Va = 5V (Note 2) VRMS = 1.5V, TJ = 25°C, Va = 6V –220 –2.0 –230 –200 –0.2 –200 –22 –156 –2 –14 –1.0 Note 1: Guaranteed by design, not 100% tested in production. IAC × (Va − 1.5V) Note 2: Gain constant (K) = VRMS 2 × IMO 3 –1.1 24 15 mV µA ns –170 2.0 –170 –0.9 µA µA µA µA µA µA µA A/A UC1854A/B UC2854A/B UC3854A/B Unless otherwise stated, VCC=18V, RT=8.2k, CT=1.5nF, PKLMT=1V, VRMS =1.5V, IAC=100µA, ELECTRICAL =0V, CA Out=3.5V, VA Out=5V, VSENSE=3V, –55oC<TA<125oC for the UC1854A/B, CHARACTERISTICS (cont.) ISENSE o o o o –40 C<TA<85 C for the UC2854A/B, and 0 C<TA <70 C for the UC3854A/B, and TA=TJ. PARAMETER GATE DRIVER Output High Voltage Output Low Voltage Output Low (UVLO) Output Rise / Fall Time Output Peak Current TEST CONDITIONS IOUT IOUT IOUT IOUT = –200mA, VCC = 15V = 200mA = 10mA = 50mA, VCC = 0V CLOAD = 1nF, (Note 1) CLOAD = 10nF, (Note 1) MIN TYP 12 12.8 1 300 0.9 35 1.0 MAX 2.2 500 1.5 UNITS V V mV V ns A Note 1: Guaranteed by design, not 100% tested in production. IAC × (Va − 1.5V) Note 2: Gain constant (K) = VRMS 2 × IMO FUNCTIONAL DESCRIPTION The UC1854A/B products were designed as pin compatible upgrades to the industry standard UC1854 active Power Factor correction circuits. The circuit enhancements allow the user to eliminate in most cases several external components currently required to successfully apply the UC1854. In addition, linearity improvements to the Multiply, Square, and Divide circuitry optimizes overall system performance. Detailed descriptions of the circuit enhancements are provided below. For in-depth design applications reference data refer to Unitrode application notes U-134 and DN-44. VRMS should produce 1.5V at low line (85VAC). This will put 4.77V on VRMS at high line (27VAC) which is well within its operating range. The VRMS pin linear operating range is improved with the UC1854A/B as well. The input range for VRMS extends from 0 to 5.5V. Since the UC1854A squaring circuit employs an analog multiplier, rather than a linear approximation, accuracy is improved, and discontinuities are eliminated. The external divider network connected to The Current Amplifier for an average current PFC controller needs a low offset voltage in order to minimize AC line current distortion. With this in mind, the UC1854A/B Current Amplifier has improved the input offset voltage from ±4mV to 0 to −3mV. The negative The Voltage Amplifier output forms the third input to the Multiplier and is internally clamped to 6.0V. This eliminates an external zenerclamp often used in UC1854 designs. The offset voltage at this input to the Multiplier has been raised on the UC1854A/B to 1.5V. The Multiplier output pin, which is also common to the Current Amplifier non-inverting input, has a −0.3V to 5.0V output range,compared to the −0.3 to 2.5V range of the MULTIPLY / SQUARE AND DIVIDE UC1854. This improvement allows the UC1854A/B to be The UC1854A/B Multiplier design maintains the same used in applications where the current sense signal gain constant (K = −1), as the UC1854. The relationship amplitude is very large. between the inputs and output current is given as: VOLTAGE AMPLIFIER IMO = IAC(V AO - 1.5V) / K•VRMS2 The UC1854A/B Voltage Amplifier design is essentially This is nearly the same as the UC1854, but circuit similar to the UC1854 with two exceptions. The first is with differences have improved the performance and the internal connection. The lower voltage reduces the application. amount of charge on the compensation capacitor, which The first difference is with the IAC input. The UC1854A/B provides improved recovery from large signal events, regulates this pin voltage to a nominal 500mV over the full such as line dropouts, or power interruption. It also operating temperature range, rather than the 6.0V used minimizes the DC current flowing through the feedback. on the UC1854. This low offset voltage eliminates the The output of the Voltage amplifier is also changed. In need for a line zero crossing compensating resistor to addition to a 6.0V temperature compensated clamp, the VREF from IAC that UC1854 designs require. The output short circuit current has been lowered to 2mA maximum current at high line into IAC should be limited to typical, and an active pull down has replaced the passive 250µA for best performance. Therefore, if VAC (max) = pulldown of the UC1854. 270V, then RAC = 270(1.414) / 250µA = 1.53MΩ. CURRENT AMPLIFIER 4 UC1854A/B UC2854A/B UC3854A/B FUNCTIONAL DESCRIPTION (cont.) offset of the UC1854A/B guarantees that the PWM circuit will not drive the MOSFET if the current command is zero (both Current amplifier inputs zero.).Previous designs required an external offset cancellation network to implement this key feature. The bandwidth of the Current Amplifier has been improved as well to 5mHz typical. While this is not generally an issue at 50 or 60Hz inputs, it is essential for 400Hz input avionics applications. desired. The lower startup supply current (250µA typical), substantially reduces the power requirements of an offline startup resistor. The 10.5/10V UVLO option (UC1854B) enables the controller to be powered off of an auxiliary 12V supply. The VREF "GOOD" comparator guarantees that the MOSFET driver output remains low if the supply or the 7.5V reference are not yet up. This improvement MISCELLANEOUS eliminates the need for external Schottky diodes on the Several other important enhancements have been PKL and CA+ pins that some UC1854 designs require. implemented in the UC1854A/B. A VCC supply voltage The propagation delay of the disable feature has been clamp at 20V allows the controller to be current fed if improved to 300ns typical. This delay was proportional to TYPICAL CHARACTERISTICS at TA = TJ = 25°C Gate Drive Rise and Fall Time Gate Drive Maximum Duty Cycle 700 100% 600 95% Rise Time 500 90% Fall Time 400 ns Duty 85% Cycle 300 80% 200 75% 100 0 70% 0 0.01 0.02 0.03 0.04 0.05 1 10 Load Capacitance, µF RSET, k Ω UC1854A/B Multiplier Linearity VAOUT = 3.5V UC1854A/B Multiplier Linearity VAOUT = 5V 1.2 1.2 1.16 1.16 1.12 1.12 1.08 1.04 K 100 VRMS= 1.5V 1 VRMS= 3.0V 1.08 VRMS= 5.0V 1.04 K 0.96 0.92 0.92 0.88 0.88 0.84 0.84 0.8 0 50 100 150 200 VRMS= 1.5V 1 0.96 VRMS= 3.0V VRMS= 5.0V 0.8 250 0 IAC Current (µA) 5 50 100 150 IAC Current (µA) 200 250 UC1854A/B UC2854A/B UC3854A/B TYPICAL CHARACTERISTICS at TA = TJ = 25°C (cont.) Current Amplifier Frequency Response Oscillator Frequency vs R SET and CT 1000 5.992 496 516 MHz 120 Gain -90 100 Phase -45 Phase Gain (dB) 80 Degrees 0 60 100pF Frequency kHz 100 40 200pF 20 500pF 0 1nF -20 10nF 5nF 3nF 2nF -40 10 -60 10kHz 100kHz 1MHz 1 10MHz 10 100 RSET, k Ω log f Voltage Amplifier Gain and Phase vs Frequency 120 Phase Margin degrees 100 80 60 Open-Loop 40 20 Gain dB 0 -20 0.1 1 10 100 1000 10000 Frequency kHz UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 FAX (603) 424-3460 These products contain patented circuitry and are sold under license from Pioneer Magnetics, Inc. 6 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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