RGT DGQ TPS65552A www.ti.com SLVS567 – JULY 2005 INTEGRATED PHOTO FLASH CHARGER AND IGBT DRIVER FEATURES APPLICATIONS • • • • • • • • • • • • • Digital Still Cameras (DSC) Optical Film Cameras Mobile Phones With Camera PDAs With Camera DESCRIPTION This device offers a complete solution for charging a photo flash capacitor from battery input, and subsequently discharging the capacitor to the xenon tube. The device has an integrated power switch, IGBT driver, and control logic blocks for charge applications. Compared with discreet solutions, the device significantly reduces the component count, shrinks the solution size, and eases design complexity. Additional advantages are fast charging time and high efficiency due to the optimized PWM control algorithm. Other provisions of the device includes four options for determining a different target voltage, programmable peak current, thermal disable monitor, input signal for charge enable, flash enable, and an output signal for charge completion status. VA T1 V5 V VCC SW VBAT D1 VOUT C1 1:10 or 1:11 or 1:12 VVF CHG D Q F1 Controller VVF Internal ENA R1 0 V DS XFULL or D Q F2 U1 VCC V_FULL ENA D/A Vonv. U0 or Max ON U2 LOGIC I_PEAK Analog Circuit 30 mΩ PGND U3 I_PEAK1 I_PEAK2 or TSD NC VCC F_ON G_IGBT U4 SW1 5[V] drive IGBT Figure 1. Typical Application Circuit Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. Copyright © 2005, Texas Instruments Incorporated PRODUCT PREVIEW • Highly Integrated Solution to Reduce Components Integrated 50-V Power Switch, R(ON) = 200 mΩ Typical Integrated IGBT Driver High Efficiency Programmable Peak Current, 0.95 A ~ 1.8 A Input Voltage of 1.8 V to 12 V Optimized Control Loop for Fast Charge Time Sensing All Trigger From Primary Side 10-Pin MSOP/16-Pin QFN Package Protection – MAX On Time – Over VDS Shutdown – Thermal Monitor TPS65552A www.ti.com SLVS567 – JULY 2005 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA TARGET VOLTAGE at PRIMARY SIDE PACKAGE MARKING PACKAGE PART NUMBER -35°C to 85°C 29 BKV 16-pin QFN TPS65552ARGT -35°C to 85°C 29 BMA 10-pin MSOP TPS65552ADGQ ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) UNIT VSS Supply voltage V(SW) Switch terminal voltage VCC -0.6 V to 6 V VBAT -0.6 V to 13 V -0.6 V to 50 V Switch current between SW and PGND, ISW PRODUCT PREVIEW VI Input voltage of CHG, I_PEAK, F_ON Tstg Storage temperature TJ Maximum junction temperature (1) 3A -0.3 V to VCC -40°C to 150°C 125°C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, VCC VSS Supply voltage, VBAT V(SW) Switch terminal voltage, NOM MAX UNIT 4.5 5.5 V 1.8 12 V -0.3 45 V 2 A 85 °C Switch current between SW and PGND Operating free-air temperature range -35 VIH High-level digital input voltage at CHG and F_ON 2.4 VIL Low-level digital input voltage at CHG and F_ON V 0.6 V DISSIPATION RATINGS (1) 2 PACKAGE RθJA (1) POWER RATING TA < 25°C POWER RATING TA = 70°C POWER RATING TA = 85°C MSOP 49.08 °C/W 2.04 W 1.12 W 815 mW QFN 47.40 °C/W 2.11 W 1.16 W 844 mW The thermal resistance, RθJA, is based on a soldered PowerPAD™ on a 2S2P JEDEC board using thermal vias. TPS65552A www.ti.com SLVS567 – JULY 2005 ELECTRICAL CHARACTERISTICS TA = 25°C, VBAT = 4.2 V, VCC = 5 V, V(SW) = 4.2 V (unless otherwise noted) TEST CONDITIONS ON resistance of XFULL V(PKH) (1) Upper threshold voltage of I_PEAK (1) Lower threshold voltage of I_PEAK V(PKL) MIN I(XFULL) = -1 mA TYP MAX 1.5 3 2.4 UNIT kΩ V 0.6 V ICC1 Supply current from VBAT CHG = H, V(SW) = 0 V (free run by tMAX) ICC2 Supply current from VCC CHG = H, V(SW) = 0 V (free run by tMAX) ICC3 Supply current from VCC and VBAT Ilkg1 Leakage current of SW terminal Ilkg2 Leakage current of XFULL terminal V(XFULL) = 5 V R(ONSW) SW ON resistance between SW and PGND I(SW) = 1 A R(IGBT1) G_IGBT pullup resistance V(G_IGBT) = 0 V R(IGBT2) G_IGBT pulldown resistance V(G_IGBT) = 5 V I(PEAK1) Upper peak of I(SW) V(I_IPEAK) = 3 V I(PEAK2) Lower peak of I(SW) V(I_IPEAK) = 0 V V(FULL) Charge completion detect voltage at V(SW) TPS65552A V(ZERO) Zero current detection at V(SW) 1 20 60 mV T(SD) (1) Thermal shutdown temperature 150 160 170 °C Over VDS detection at V(SW) 0.95 1.2 1.45 V 50 80 120 µs tMAX MAX ON time R(INPD) Pulldown resistance of CHG, F_ON (1) 27 2.5 µA 5 mA 1 µA 2 µA 1 µA 0.3 1 Ω 5 10 15 Ω 25 51 75 Ω 1.58 1.68 1.78 A 0.77 0.87 0.97 A 28.7 29 29.3 V CHG = L VCHG = V(F_ON) = 4.2 V 100 PRODUCT PREVIEW PARAMETER R(ONL) kΩ Specified by design. SWITCHING CHARACTERISTICS TA = 25°C, VBAT = 4.2 V, VCC = 5 V, V(SW) = 4.2 V (unless otherwise noted) PARAMETER tPD (1) (1) Propagation delay TEST CONDITIONS MIN TYP MAX UNIT F_ON↑↓ - G_IGBT↑↓ 50 ns SW ON after V(SW) dips from V(ZERO) 45 ns SW OFF after I(SW) exceeds I(PEAK) 270 ns XFULL↓ after V(SW) exceeds V(FULL) 300 ns SW ON after CHG↑ 20 ns SW OFF after CHG↓ 20 ns Specified by design. 3 TPS65552A www.ti.com SLVS567 – JULY 2005 PIN ASSIGNMENT DGQ PACKAGE (TOP VIEW) NC NC NC VBAT RGT PACKAGE (TOP VIEW) SW 1 16 15 14 13 12 PGND SW 2 11 PGND VCC 3 10 CHG F_ON 4 9 7 8 1 10 SW 2 9 PGND VCC 3 8 CHG 4 7 XFULL I_PEAK 5 6 G_IGBT Power PAD NC − No internal connection PRODUCT PREVIEW TERMINAL FUNCTIONS PIN NUMBER 4 SIGNAL I/O DESCRIPTION RGT DGQ 1, 2 2 SW O Primary side switch 3 3 VCC I Power supply voltage 4 4 F_ON I G_IGBT control input 5, 8, 13, 16 – NC 6 5 I_PEAK I Peak current control input 7 6 G_IGBT O IGBT gate driver output 9 7 XFULL O Charge completion output 10 8 CHG I Charge control input 11, 12 9 PGND 14 10 NC 15 1 VBAT No connection (internally open) Power ground No connection (used by TI, should be open pin) I NC F_ON NC NC 6 I_PEAK G_IGBT 5 XFULL VBAT Battery voltage input TPS65552A www.ti.com SLVS567 – JULY 2005 VCC VBAT CHG D Q F1 SW Internal ENA XFULL 0 V DS D Q F2 U1 VCC V_FULL ENA U0 Max ON U2 I_PEAK Logic 30 mΩ PGND U3 I_PEAK1 I_PEAK2 TSD NC F_ON G_IGBT U4 PRODUCT PREVIEW Figure 2. Functional Block Diagram I/O Equivalent Circuits CHG, F_ON SW VCC SW CHG, F_ON 100 k 30 m PGND PGND I_PEAK XFULL VCC XFULL I_PEAK PGND PGND VBAT G_IGBT VCC VBAT 10 G_IGBT 41 PGND PGND Figure 3. I/O Equivalent Circuits 5 TPS65552A www.ti.com SLVS567 – JULY 2005 PRINCIPLES OF OPERATION CHG (VOUT) XFULL F_ON G_IGBT (ENA) TimeA TimeB TimeC TimeD TimeE TimeF TimeG TimeH TimeI TimeJ Figure 4. Whole Operation Sequence Chart PRODUCT PREVIEW Start/Stop Charging TPS65552A has one internal enable latch, F1, that holds a charge (ON/OFF status) of the device. See Figure 2. The only way to start charging is to input CHG↑ (see time A/C/H in Figure 4). Each time CHG↑ is reached, the TPS65552A starts charging. There are three trigger events to stop charging: 1. Forced stop by inputting CHG = L from the controller (see timeB in Figure 4). 2. Automatic stop by detecting full charge. VOUT reaches the target value (see TimeD in Figure 4). 3. Protected stop by over VDS detection (see TimeI in Figure 4). Indicate Charging Status When the charging operation is completed, the TPS65552A drives the charge completion indicator pin, XFULL, to GND. XFULL is an open-drain type output. When connecting the indicator LED to XFULL, the LED lights are on when fully charged. The controller detects the status of the device as a logic signal when connecting a pullup resister, R1 (see Figure 1). XFULL enables the controller to detect the over VDS protection status using software time. If over VDS protection occurs, XFULL never goes L during CHG = H, provided that the timer that starts at CHG↑ stops at XFULL↑, and times out within a designed period of maximum charging times. The controller can detect over VDS at time out. The device starts charging at timeH, and over VDS protection occurs at TimeI (see Figure 4). At timeI, XFULL stays H, and the controller detects over VDS protection when the timer ends at timeJ. In this event, the controller inputs CHG = L to terminate the operation. 6 TPS65552A www.ti.com SLVS567 – JULY 2005 CHG SW LOGIC OFF ON OFF XFULL SW VSW VZERO OFF ON OF F OFF ON OFF V VSW VBAT VFULL V 0V VBAT VA VOUT VBAT 0V VOUT 0V VA V 0V ISW I VA IPEAK 0A I I IOUT IPEAK/NTURN 0A Time 1 Time 2 T VOUT Time 3 Time 5 Time 4 Figure 5. Timing Diagram at One Switching Cycle I ISW 0A 0A IPEAK IOUT IPEAK/NTURN ISW IOUT T Figure 6. Timing Diagram at Beginning/Ending Control Charging The TPS65552A provides three comparators to control charging. Figure 2 shows the block diagram of TPS65552A and Figure 5 shows one timing diagram switching cycle. Note that emphasis is placed on Time1 and Time3 of the waveform in Figure 5. While SW is ON (Time1 to Time2 in Figure 5), U3 monitors current flow through integrated power-MOSFET from SW to PGND. When I(SW) exceeds I(PEAK), SW turns OFF (Time2 in Figure 5). When SW turns OFF (Time2 in Figure 5), the magnetic energy in the transformer starts discharging. Meanwhile, U2 monitors the kickback voltage at the SW terminal. As the energy is discharging, the kickback voltage is increasing according to the increase of VOUT (Time2 to Time3 in Figure 5). When almost all energy is discharged, the system cannot continue rectification via the diode, and the charging current of IOUT goes to zero (Times3 in Figure 5). After rectification stops, the small amount of energy left in the transformer is released via the parasitic path, and the kickback voltage reaches zero (Time3 to Time4 in Figure 5). During this period, U2 makes SW turn ON when (V(SW) - VBAT) dips from V(ZERO) (Time5 in Figure 5). In the actual circuit, the period between Time4 and Time5 in Figure 5 is small or does not appear dependent on the delay time of the U2 detection to SW ON. U1 also monitors the kickback voltage. When (V(SW) - VBAT) exceeds V(FULL), TPS65552A stops charging (see Figure 6). In Figure 5 and Figure 6, ON time is always the same period in every switching. The ON time is calculated by Equation 1. This equation is not dependent on output voltage. æ I PEAK ö ÷ tON = L çç ÷ è V BAT ø (1) However, OFF time is dependant on output voltage. As the output voltage gets higher, the OFF time gets shorter (see Equation 2). 7 PRODUCT PREVIEW V TPS65552A www.ti.com SLVS567 – JULY 2005 æ IPEAK ö ÷ tOFF = N_TURN x L çç V ÷ è OUT ø (2) Reference Voltage The TPS65552A does not have its own reference voltage circuit inside, and the TPS65552A uses the VCC input voltage as a reference to detect I(PEAK), V(ZERO), and V(FULL). Therefore, voltage input at VCC is approximately 5 V. VCC differs from 5 V by system limitations. Table 1 shows the dependence of each function of TPS65552A to VCC. Table 1. VCC Dependence of TPS65552A PARAMETER V(FULL) EQUATION VCC 4.5 5 5.5 PRODUCT PREVIEW I(PEAK1) 0.52 x VCC - 0.92 1.42 1.68 1.94 I(PEAK2) 0.24 x VCC - 0.33 0.75 0.87 0.99 TPS65552A 5.8 x VCC 26.1 29.0 31.9 over VDS 0.24 x VCC 1.08 1.2 1.32 Termination Voltage Setting To obtain a different termination voltage, transformers of different turn ratio are required. Table 2 shows the matrix of termination voltage and the turn ratio of the transformer. The table only shows a ONE to integer ratio while there are no limitations for a turn ratio of the transformer in a real application circuit, example 1:10.5 (= 10:105). Table 2. Termination Voltage Setting Table TPS65552A 29 [V] 8 1:10 290 1:11 319 1:12 348 TPS65552A www.ti.com SLVS567 – JULY 2005 Programming Peak Current The TPS65552A provides a method to program I(PEAK) through the input voltage of the I_PEAK terminal. Figure 7 shows how to program I(PEAK). I_PEAK input is treated as a logic input, when its voltage is below V(PKL) (0.6 V) and above V(PKH) (2.4 V). Between V(PKL) and V(PKH), I_PEAK input is treated as an analog input. Using this characteristic, I(PEAK) can be set by the logic signal or by an analog input. Typical usages of this function are: 1. Charging I(PEAK) depends on the battery voltage. Large I(PEAK) for an adequate battery, small I(PEAK) for a poor battery. 2. Reducing I(PEAK) when zooming lens (motor works); this avoids shutdown of the battery with a large current output. In Figure 1, three optional connections to I_PEAK are shown. 1. Use the controller to treat I_PEAK as the logic input pin. This option is the easiest. 2. Use a D/A converter to force I(PEAK) to follow analog information, such as battery voltage. 3. Use an analog circuit to achieve the same results as the D/A converter. PRODUCT PREVIEW 2 1.80 I(SW) [A] 1.60 1.40 1.20 1 0.80 0 0.5 1 1.5 2 2.5 3 3.5 V(I_PEAK) [V] Figure 7. I_PEAK vs I(SW) IGBT Driver Control The IGBT driver provided by the TPS65552A is a simple buffer in the logical table. Table 3 shows the function (see Figure 4). Table 3. IBGT Driver Function Table F_ON G_IGBT L L H H 9 TPS65552A www.ti.com SLVS567 – JULY 2005 Protections TPS65552A provides three protections: thermal shutdown, max on time, and overvoltage at power SW. Thermal Shutdown When TPS65552A overheats, all functions stop. The only way to recover is to wait for the TPS65552A to cool down. This protection is not through SHUTDOWN, so the TPS65552A restarts charging if CHG stays H during the whole overheated period. MAX ON Time To prevent a condition such as pulling current from a poor power source (i.e., an almost empty battery), the TPS65552A provides a maximum ON time protection. If the ON time exceeds tMAX, the TPS555x is forced OFF regardless of I(PEAK) detection. Overvoltage at Power SW To avoid the stress of power dissipation, the TPS65552A provides an overvoltage monitor function at the SW terminal. If this protection occurs, the overvoltage status is latched (see Figure 4 and its descriptions). This function also protects short-circuit of the secondary side. In the short-circuit state of the secondary side, almost 100% of the battery voltage is supplied to SW, which stresses the device. PRODUCT PREVIEW PCB Information D1 VOUT C1 Note 1 5V POWER UNIT 3V T1 1:10 or 1:11 or 1:12 Note 4 C2 VCC VBAT R1 SW CHG D Q F1 Internal ENA R1 0 V DS XIFULL D Q F2 U1 Note 2 VCC V_FULL ENA U0 Max ON U2 I_PEAK LOGIC 30 mΩ PGND U3 I_PEAK1 I_PEAK2 TSD NC VCC F_ON G_IGBT U4 Note 3 Figure 8. PCB Design Guideline 10 SW1 5 V Drive IGBT www.ti.com TPS65552A SLVS567 – JULY 2005 Figure 8 shows key points when designing a PCB. 1. In many DSC designs, parasitic resistance that cannot be ignored, exists on the power line path from the battery to the primary side turn of the transformer. The TPS65552A has one ground point connection inside the IC at the PGND PAD. So, the PCB layout should also keep a one-point ground connection at the PGND terminal of TPS65552A. 2. The loop indicated by dotted-lines is laid out as small as possible to reduce the open area of the loop. 3. The TPS65552A uses the VCC input as a reference voltage. Considering Note 1, the ground of the power unit that sources VCC is connected to PGND. 4. Regarding Note 3, the bypass capacitor, C2, is required to avoid grounding noise. Additional Technical Information TI provides an application note for this device. For more technical information, please find the application note on the TI Web site or consult your sales contact. Literature number SLVA197. PRODUCT PREVIEW The application note provides the following information. 1. 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