UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com DUAL 4-A HIGH-SPEED LOW-SIDE MOSFET DRIVERS WITH ENABLE Check for Samples: UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 FEATURES 1 • • • • • 2 • • • • • • Qualified for Automotive Applications Industry-Standard Pinout Enable Functions for Each Driver High Current Drive Capability of ±4 A Unique Bipolar and CMOS True Drive Output Stage Provides High Current at MOSFET Miller Thresholds TTL/CMOS Compatible Inputs Independent of Supply Voltage 20-ns Typical Rise and 15-ns Typical Fall Times With 1.8-nF Load Typical Propagation Delay Times of 25 ns With Input Falling and 35 ns With Input Rising 4-V to 15-V Supply Voltage Dual Outputs Can Be Paralleled for Higher Drive Current Rated From –40°C to 125°C DESCRIPTION The UCC2742x high-speed dual MOSFET drivers can deliver large peak currents into capacitive loads. Two standard logic options are offered – dual inverting and dual noninverting drivers. They are offered in the standard SOIC-8 (D) package. Using a design that inherently minimizes shoot-through current, these drivers deliver 4-A current where it is needed most, at the Miller plateau region, during the MOSFET switching transition. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing and sinking at low supply voltages. The UCC2742x provide enable (ENBL) functions to have better control of the operation of the driver applications. ENBA and ENBB are implemented on pins 1 and 8, which were previously left unused in the industry standard pinout. They are internally pulled up to VDD for active-high logic and can be left open for standard operation. APPLICATIONS • • • • • Switch Mode Power Supplies DC/DC Converters Motor Controllers Line Drivers Class D Switching Amplifiers Figure 1. BLOCK DIAGRAM 8 ENBB 7 OUTA 6 VDD 5 OUTB ENBA 1 INVERTING INA 2 VDD NONINVERTING INVERTING GND 3 INB 4 NONINVERTING 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com ORDERING INFORMATION (1) (2) TA CONFIGURATION Dual Inverting Dual Noninverting –40°C to 125°C ORDERABLE PART NUMBER PACKAGE MSOP – DGN Reel of 2500 Dual Inverting Dual Noninverting SOIC – D Reel of 2500 One Inverting, One Noninverting (1) (2) TOP-SIDE MARKING UCC27423QDGNRQ1 EADQ UCC27424QDGNRQ1 EPJQ UCC27423QDRQ1 27423Q UCC27424QDRQ1 27424Q UCC27425QDRQ1 27425Q For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. UCC27423 D OR DGN PACKAGE (TOP VIEW) UCC27424 D OR DGN PACKAGE (TOP VIEW) UCC27425 D PACKAGE (TOP VIEW) ENBA 1 8 ENBB ENBA 1 8 ENBB ENBA 1 8 ENBB INA 2 7 OUTA INA 2 7 OUTA INA 2 7 OUTA GND 3 6 VDD GND 3 6 VDD GND 3 6 VDD INB 4 5 OUTB (DUAL INVERTING) INB 4 INB 4 5 OUTB 5 OUTB (ONE INVERTING, ONE NON-INVERTING) (DUAL NON-INVERTING) TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION 1 I Enable input for the driver A with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The output state when the device is disabled is low, regardless of the input state. INA 2 I Input A. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. GND 3 INB 4 I Input B. Input signal of the A driver which has logic compatible threshold and hysteresis. If not used, this input should be tied to either VDD or GND. It should not be left floating. OUTB 5 O Driver output B. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. VDD 6 OUTA 7 O Driver output A. The output stage is capable of providing 4-A drive current to the gate of a power MOSFET. ENBB 8 I Enable input for the driver B with logic compatible threshold and hysteresis. The driver output can be enabled and disabled with this pin. It is internally pulled up to VDD with 100-kΩ resistor for active high operation. The output state when the device is disabled is low, regardless of the input state. NAME NO. ENBA 2 Common ground. This ground should be connected very closely to the source of the power MOSFET which the driver is driving. Supply voltage and the power input connection for this device. Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com INPUT/OUTPUT TABLE INPUTS (VIN_L, VIN_H) UCC27423 UCC27424 UCC27425 ENBA ENBB INA INB OUTA OUTB OUTA OUTB OUTA H H L L H H L L H L H H L H H L L H H H H H H L L H H L L L H H H H L L H H L H L L X X L L L L L L ABSOLUTE MAXIMUM RATINGS (1) OUTB (2) over operating free-air temperature range (unless otherwise noted) VDD –0.3 V to 16 V Supply voltage DC 0.3 A Pulsed, 0.5 μs 4.5 A IOUT Output current VIN Input voltage INA, INB VEN Enable voltage ENBA, ENBB PD Power dissipation TA = 25°C TJ Junction operating temperature range –55°C to 150°C Tstg Storage temperature range –65°C to 150°C (1) (2) –5 V to 6 V or (VDD + 0.3) (whichever is larger) –0.3 V to 6 V or (VDD + 0.3) (whichever is larger) 650 mW Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive into, negative out of, the specified terminal. DISSIPATION RATINGS (1) (2) (3) PACKAGE θJC (°C/W) θJA (°C/W) POWER RATING TA = 70°C (mW) (1) DERATING FACTOR ABOVE TA = 70°C (mW/°C) (1) D (SOIC-8) 42 84 to 160 (2) 344 to 655 (2) 6.25 to 11.9 (2) DGN (MSOP PowerPAD) (3) 4.7 50 to 59 1370 17.1 125°C operating junction temperature is used for power rating calculations. The range of values indicates the effect of the PCB. These values are intended to give the system designer an indication of the bestand worst-case conditions. In general, the system designer should attempt to use larger traces on the PCB, where possible, to spread the heat away form the device more effectively. The PowerPAD™ is not directly connected to any leads of the package. However, it is electronically and thermally connected to the substrate which is the ground of the device. Copyright © 2008–2011, Texas Instruments Incorporated 3 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS VDD = 4.5 V to 15 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input (INA, INB) VIH Logic 1 input threshold VIL Logic 0 input threshold IIN Input current 2 –10 VIN = 0 V to VDD V 1 V 10 μA 330 450 mV 22 40 mV 30 35 0 Output (OUTA, OUTB) IOUT Output current VDD = 14 V (1) VOH High-level output voltage VOH = VDD – VOUT, IOUT = –10 mA, VDD = 14 V VOL Low-level output voltage IOUT = 10 mA, VDD = 14 V ROH Output resistance high ROL Output resistance low (2) 4 TA = 25°C, IOUT = –10 mA, VDD = 14 V (3) 25 TA = full range, IOUT = –10 mA, VDD = 14 V (3) 18 TA = 25°C, IOUT = 10 mA, VDD = 14 V (3) 1.9 TA = full range, IOUT = 10 mA, VDD = 14 V (3) 1.2 Latch-up protection (1) A 45 2.2 2.5 4 500 Ω Ω mA Switching Time tr Rise time (OUTA, OUTB) CLOAD = 1.8 nF (1) 20 40 ns tf Fall time (OUTA, OUTB) CLOAD = 1.8 nF (1) 15 40 ns tD1 Delay time, IN rising (IN to OUT) CLOAD = 1.8 nF (1) 25 50 ns tD2 Delay time, IN falling (IN to OUT) CLOAD = 1.8 nF (1) UCC27423, UCC27424 35 60 UCC27425 35 70 ns Enable (ENBA, ENBB) VIN_H High-level input voltage Low to high transition 1.7 2.4 2.9 V VIN_L Low-level input voltage High to low transition 1.1 1.8 2.2 V 0.15 0.55 0.90 V 75 Hysteresis RENBL Enable impedance VDD = 14 V, ENBL = GND 100 145 kΩ tD3 Propagation delay time (see Figure 3) CLOAD = 1.8 nF (1) (4) 30 60 ns tD4 Propagation delay time (see Figure 3) CLOAD = 1.8 nF (1) (4) 100 150 ns (1) (2) (3) (4) 4 Specified by design The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The pulsed output current rating is the combined current from the bipolar and MOSFET transistors. The pullup/pulldown circuits of the driver are bipolar and MOSFET transistors in parallel. The output resistance is the Rds(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Not production tested Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 4.5 V to 15 V, TA = –40°C to 125°C, TA = TJ (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX INB = 0 V 900 1350 INB = High 750 1100 INB = 0 V 750 1100 INB = High 600 900 INB = 0 V 300 450 INB = High 750 1100 INB = 0 V 750 1100 INB = High 1200 1800 INB = 0 V 600 900 INB = High 1050 1600 INB = 0 V 450 700 INB = High 900 1350 INB = 0 V 300 450 INB = High 450 700 INB = 0 V 450 700 INB = High 600 900 UNIT Overall INA = 0 V UCC27423 INA = High INA = 0 V Static, VDD = 15 V, ENBA = ENBB = 15 V UCC27424 INA = High IDD Operating current INA = 0 V UCC27425 INA = High INA = 0 V Disabled, VDD = 15 V, ENBA = ENBB = 0 V All INA = High Copyright © 2008–2011, Texas Instruments Incorporated μA 5 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com (a) (b) +5V 90% 90% INPUT INPUT 10% 10% 0V td1 tf td2 tf tf tf 16V 90% 90% 90% td1 OUTPUT td2 OUTPUT 10% 10% 0V A. The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 2. Switching Waveforms for (a) Inverting Driver and (b) Noninverting Driver 5V ENBx VIN_L VIN_H 0V td3 td4 VDD 90% OUTx 90% tr tf 10% 0V A. The 10% and 90% thresholds depict the dynamics of the bipolar output devices that dominate the power MOSFET transition through the Miller regions of operation. Figure 3. Switching Waveform for Enable to Output 6 Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY (VDD = 8.0 V) 100 100 80 80 10 nF IDD − Supply Current − mA IDD − Supply Current − mA SUPPLY CURRENT vs FREQUENCY (VDD = 4.5 V) 60 4.7 nF 40 2.2 nF 20 10 nF 4.7 nF 60 40 2.2 nF 1 nF 20 1 nF 470 pF 0 470 pF 0 500 K 1M 1.5 M 0 2M 0 f - Frequency − Hz 500 K 1.5 M 2M f - Frequency − Hz Figure 4. <br/> <br/> Figure 5. <br/> <br/> SUPPLY CURRENT vs FREQUENCY (VDD = 15 V) SUPPLY CURRENT vs FREQUENCY (VDD = 12 V) 150 200 100 10 nF IDD − Supply Current − mA IDD − Supply Current − mA 1M 4.7 nF 2.2 nF 50 1 nF 150 10 nF 4.7 nF 100 2.2 nF 50 1 nF 470 pF 470 pF 0 0 0 500 K 1M f - Frequency − Hz Figure 6. <br/> <br/> Copyright © 2008–2011, Texas Instruments Incorporated 1.5 M 2M 0 500 K 1M 1.5 M 2M f - Frequency − Hz Figure 7. <br/> <br/> 7 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs SUPPLY VOLTAGE (CLOAD = 4.7 nF) SUPPLY CURRENT vs SUPPLY VOLTAGE (CLOAD = 2.2 nF) 90 160 80 140 2 MHz 70 IDD − Supply Current − mA IDD − Supply Current − mA 120 60 50 1 MHz 40 30 500 kHz 20 2 MHz 100 1 MHz 80 60 500 kHz 40 200 kHz 200 kHz 10 20 100/50 kHz 0 100 kHz 50/20 kHz 0 4 6 8 10 12 14 16 4 9 Figure 8. <br/> <br/> Figure 9. <br/> <br/> SUPPLY CURRENT vs SUPPLY VOLTAGE (UCC27423) SUPPLY CURRENT vs SUPPLY VOLTAGE (UCC27424) 0.9 19 0.60 0.8 0.55 Input = V DD Input = VDD I DD − Supply Current − mA IDD − Supply Current − mA 14 VDD − Supply Voltage − V VDD − Supply Voltage − V 0.7 0.6 0.5 0.4 0.50 Input = 0 V 0.45 0.40 0.35 Input = 0 V 0.3 0.30 4 6 8 10 12 VDD − Supply Voltage − V Figure 10. <br/> <br/> 8 14 16 4 6 8 10 12 VDD − Supply Voltage − V 14 16 Figure 11. <br/> <br/> Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) SUPPLY CURRENT vs SUPPLY VOLTAGE (UCC27425) 0.75 0.70 Input = VDD 0.60 0.55 ns IDD - Supply Current - mA 0.65 0.50 Input = 0 V 0.45 0.40 0.35 0.30 4 6 8 10 12 14 16 VDD - Supply Voltage - V Figure 13. <br/> <br/> ns ns Figure 12. Figure 14. <br/> <br/> Copyright © 2008–2011, Texas Instruments Incorporated Figure 15. <br/> <br/> 9 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) DELAY TIME (tD2) vs SUPPLY VOLTAGE (UCC27423) DELAY TIME (tD1) vs SUPPLY VOLTAGE (UCC27423) 30 38 28 36 10 nF 34 10 nF 24 22 td2 − Delay Time − ns td1 − Delay Time − ns 26 4.7 nF 20 18 2.2 nF 16 32 4.7 nF 30 28 2.2 nF 26 470 pF 24 1 nF 470 pF 14 22 1 nF 12 20 4 6 8 10 12 14 4 16 6 8 VDD − Supply Voltage − V Figure 16. <br/> <br/> 14 16 100 125 ENABLE RESISTANCE vs TEMPERATURE 3.0 150 140 ENBL − ON 2.5 130 RENBL − Enable Resistance − Ω Enable threshold and hysteresis − V 12 Figure 17. <br/> <br/> ENABLE THRESHOLD AND HYSTERESIS vs TEMPERATURE 2.0 1.5 1.0 ENBL − OFF 0.5 ENBL − HYSTERESIS 0 −50 −25 0 25 50 75 TJ − Temperature − °C Figure 18. <br/> <br/> 10 10 VDD − Supply Voltage − V 120 110 100 90 80 70 60 100 125 50 −50 −25 0 25 50 75 TJ − Temperature − °C Figure 19. <br/> <br/> Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT BEHAVIOR vs SUPPLY VOLTAGE (INVERTING) OUTPUT BEHAVIOR vs SUPPLY VOLTAGE (INVERTING) IN = GND ENBL = VDD VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = GND ENBL = VDD VDD VDD OUT 0V 0V OUT 10 nF Between Output and GND 50 µs/div 10 nF Between Output and GND 50 µs/div Figure 20. <br/> <br/> Figure 21. <br/> <br/> OUTPUT BEHAVIOR vs VDD (INVERTING) OUTPUT BEHAVIOR vs VDD (INVERTING) VDD OUT IN = VDD ENBL = VDD VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = VDD ENBL = VDD VDD OUT 0V 0V 10 nF Between Output and GND 50 µs/div Figure 22. <br/> <br/> Copyright © 2008–2011, Texas Instruments Incorporated 10 nF Between Output and GND 50 µs/div Figure 23. <br/> <br/> 11 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT BEHAVIOR vs VDD (NONINVERTING) OUTPUT BEHAVIOR vs VDD (NONINVERTING) IN = VDD ENBL = VDD VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = VDD ENBL = VDD VDD VDD OUT OUT 0V 0V 10 nF Between Output and GND 50 µs/div 10 nF Between Output and GND 50 µs/div Figure 24. <br/> <br/> Figure 25. <br/> <br/> OUTPUT BEHAVIOR vs VDD (NONINVERTING) OUTPUT BEHAVIOR vs VDD (NONINVERTING) IN = GND ENBL = VDD VDD OUT 0V VDD OUT 0V 10 nF Between Output and GND 50 µs/div Figure 26. <br/> <br/> 12 VDD − Supply Voltage − V 1 V/div VDD − Supply Voltage − V 1 V/div IN = GND ENBL = VDD 10 nF Between Output and GND 50 µs/div Figure 27. <br/> <br/> Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) INPUT THRESHOLD vs TEMPERATURE VON − Input Threshold Voltage − V 2.0 1.9 VDD = 15 V 1.8 1.7 1.6 1.5 VDD = 10 V VDD = 4.5 V 1.4 1.3 1.2 −50 −25 0 25 50 75 100 125 TJ − Temperature − °C Figure 28. <br/> <br/> Copyright © 2008–2011, Texas Instruments Incorporated 13 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION General Information High frequency power supplies often require high-speed, high-current drivers such as the UCC27423/UCC27424. A leading application is the need to provide a high power buffer stage between the PWM output of the control IC and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver IC is utilized to drive the power device gates through a drive transformer. Synchronous rectification supplies also have the need to simultaneously drive multiple devices which can present an extremely large load to the control circuitry. Driver ICs are utilized when it is not feasible to have the primary PWM regulator IC directly drive the switching devices for one or more reasons. The PWM IC may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases there may be a desire to minimize the effect of high frequency switching noise by placing the high current driver physically close to the load. Also, newer ICs that target the highest operating frequencies may not incorporate onboard gate drivers at all. Their PWM outputs are only intended to drive the high impedance input to a driver such as the UCC27423/UCC27424. Finally, the control IC may be under thermal stress due to power dissipation, and an external driver can help by moving the heat from the controller to an external package. Input Stage The input thresholds have a 3.3-V logic sensitivity over the full range of VDD voltages; yet it is equally compatible with 0 to VDD signals. The inputs of UCC2742x drivers are designed to withstand 500-mA reverse current without either damage to the IC for logic upset. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency. Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power device, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor may also help remove power dissipation from the device package, as discussed in the section on Thermal Considerations. Output Stage Inverting outputs of the UCC2742x are intended to drive external P-channel MOSFETs. Noninverting outputs of the UCC2742x are intended to drive external N-channel MOSFETs. Each output stage is capable of supplying ±4-A peak current pulses and swings to both VDD and GND. The pullup/ pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot due to the body diode of the external MOSFET. This means that in many cases, external Schottky-clamp diodes are not required. The UCC2742x family delivers the 4-A gate drive where it is most needed during the MOSFET switching transition – at the Miller plateau region – providing improved efficiency gains. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages. Source/Sink Capabilities During Miller Plateau Large power MOSFETs present a large load to the control circuitry. Proper drive is required for efficient, reliable operation. The UCC2742x drivers have been optimized to provide maximum drive to a power MOSFET during the Miller plateau region of the switching transition. This interval occurs while the drain voltage is swinging between the voltage levels dictated by the power topology, requiring the charging/discharging of the drain-gate capacitance with current supplied or removed by the driver device. [1] 14 Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com Two circuits are used to test the current capabilities of the UCC27423 driver. In each case external circuitry is added to clamp the output near 5 V while the IC is sinking or sourcing current. An input pulse of 250 ns is applied at a frequency of 1 kHz in the proper polarity for the respective test. In each test there is a transient period where the current peaked up and then settled down to a steady-state value. The noted current measurements are made at a time of 200 ns after the input pulse is applied, after the initial transient. The circuit in Figure 29 is used to verify the current sink capability when the output of the driver is clamped around 5 V, a typical value of gate-source voltage during the Miller plateau region. The UCC27423 is found to sink 4.5 A at VDD = 15 V and 4.28 A at VDD = 12 V. VDD UCC27423 ENBA 1 INPUT 2 3 4 ENBB OUTA INA GND VDD OUTB INB 8 DSCHOTTKY 10 Ω 7 C2 1 µF 6 C3 100 µF 5 + VSUPPLY 5.5 V VSNS 100 µF 1 µF AL EL CER RSNS 0.1 Ω Figure 29. Current Sinking The circuit shown in Figure 30 is used to test the current source capability with the output clamped to around 5 V with a string of Zener diodes. The UCC27423 is found to source 4.8 A at VDD = 15 V and 3.7 A at VDD = 12 V. VDD INPUT UCC27423 ENBA 1 ENBB 8 2 INA 3 GND 4 INB OUTA C2 1 µF VDD 6 OUTB 10 Ω DSCHOTTKY 7 5 1 µF CER 100 µF AL EL C3 + 100 µF DADJ 5.5 V VSNS RSNS 0.1 Ω Figure 30. Current Sourcing The current sink capability is slightly stronger than the current source capability at lower VDD. This is due to the differences in the structure of the bipolar-MOSFET power output section, where the current source is a P-channel MOSFET and the current sink has an N-channel MOSFET. In a large majority of applications it is advantageous that the turn-off capability of a driver is stronger than the turn-on capability. This helps to ensure that the MOSFET is held OFF during common power supply transients which may turn the device back ON. Copyright © 2008–2011, Texas Instruments Incorporated 15 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com Parallel Outputs The A and B drivers may be combined into a single driver by connecting the INA/INB inputs together and the OUTA/OUTB outputs together. Then, a single signal can control the paralleled combination as shown in Figure 31. VDD INPUT UCC27423 ENBA 1 ENBB 2 INA 3 GND 4 INB OUTA 8 7 VDD 6 OUTB CLOAD 5 1 µF CER 2.2 µF Figure 31. Parallel Outputs Operational Waveforms and Circuit Layout Figure 32 shows the circuit performance achievable with a single driver (half of the 8-pin IC) driving a 10-nF load. The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform. Note the linear rise and fall edges of the switching waveforms. This is due to the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers. Figure 32. Pulse Response In a power driver operating at high frequency, it is a significant challenge to get clean waveforms without much overshoot/undershoot and ringing. The low output impedance of these drivers produces waveforms with high di/dt. This tends to induce ringing in the parasitic inductances. Utmost care must be used in the circuit layout. It is advantageous to connect the driver IC as close as possible to the leads. The driver IC layout has ground on the opposite side of the output, so the ground should be connected to the bypass capacitors and the load with copper trace as wide as possible. These connections should also be made with a small enclosed loop area to minimize the inductance. 16 Copyright © 2008–2011, Texas Instruments Incorporated UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 www.ti.com SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 VDD Although quiescent VDD current is very low, total supply current is higher, depending on OUTA and OUTB current and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from: IOUT = Qg × f, where f is frequency For the best high-speed circuit performance, two VDD bypass capacitors are recommended tp prevent noise problems. The use of surface mount components is highly recommended. A 0.1-μF ceramic capacitor should be located closest to the VDD to ground connection. In addition, a larger capacitor (such as 1-μF) with relatively low ESR should be connected in parallel, to help deliver the high current peaks to the load. The parallel combination of capacitors should present a low impedance characteristic for the expected current levels in the driver application. Drive Current and Power Requirements The UCC2742x drivers are capable of delivering 4 A of current to a MOSFET gate for a period of several hundred nanoseconds. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground. This repeats at the operating frequency of the power device. A MOSFET is used in this discussion because it is the most common type of switching device used in high frequency power conversion equipment. References 1 and 2 discuss the current required to drive a power MOSFET and other capacitive-input switching devices. Reference 2 includes information on the previous generation of bipolar IC gate drivers. When a driver IC is tested with a discrete, capacitive load it is a fairly simple matter to calculate the power that is required from the bias supply. The energy that must be transferred from the bias supply to charge the capacitor is given by: E = ½CV2, where C is the load capacitor, and V is the bias voltage feeding the driver There is an equal amount of energy transferred to ground when the capacitor is discharged. This leads to a power loss given by the following: P = 2 × ½CV2f, where f is the switching frequency This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is charged, and the other half is dissipated when the capacitor is discharged. An actual example using the conditions of the previous gate drive waveform should help clarify this. With VDD = 12 V, CLOAD = 10 nF, and f = 300 kHz, the power loss can be calculated as: P = 10 nF × (12)2 × (300 kHz) = 0.432 W With a 12-V supply, this would equate to a current of: I = P / V = 0.432 W / 12 V = 0.036 A The actual current measured from the supply was 0.037 A, and is very close to the predicted value. But, the IDD current that is due to the IC internal consumption should be considered. With no load, the IC current draw is 0.0027 A. Under this condition, the output rise and fall times are faster than with a load. This could lead to an almost insignificant, yet measurable, current due to cross-conduction in the output stages of the driver. However, these small current differences are buried in the high-frequency switching spikes and are beyond the measurement capabilities of a basic lab setup. The measured current with 10-nF load is reasonably close to that expected. The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain of the device between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Using the gate charge Qg, one can determine the power that must be dissipated when charging a capacitor. This is done by using the equivalence Qg = CeffV to provide the following equation for power: P = C × V2 × f = Qg × f Copyright © 2008–2011, Texas Instruments Incorporated 17 UCC27423-Q1 UCC27424-Q1 UCC27425-Q1 SGLS274D – SEPTEMBER 2008 – REVISED AUGUST 2011 www.ti.com This equation allows a power designer to calculate the bias power required to drive a specific MOSFET gate at a specific bias voltage. Enable UCC2742x provide dual enable inputs for improved control of each driver channel operation. The inputs incorporate logic compatible thresholds with hysteresis. They are internally pulled up to VDD with 100-kΩ resistor for active high operation. When ENBA and ENBB are driven high, the drivers are enabled; when ENBA and ENBB are low, the drivers are disabled. The default state of the enable pin is to enable the driver and, therefore, can be left open for standard operation. The output states when the drivers are disabled is low, regardless of the input state. See for operation using enable logic. Enable inputs are compatible with both logic signals and slowly changing analog signals. They can be directly driven, or a power-up delay can be programmed with a capacitor between ENBA/ENBB and GND. ENBA and ENBB control input A and input B, respectively. Thermal Information The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the IC package. For a power driver to be useful over a particular temperature range, the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits. As shown in the power dissipation rating table, the SOIC-8 (D) package has a power rating of approximately 0.5 W with TA = 70°C. This limit is imposed in conjunction with the power derating factor also given in the table. Note that the power dissipation in the previous example is 0.432 W with a 10-nF load, 12-V VDD, switched at 300 kHz. Thus, only one load of this size could be driven using the D package, even if the two onboard drivers are paralleled. References [1] Laszlo Balogh, Power Supply Seminar SEM-1400 Topic 2: Design And Application Guide For High Speed MOSFET Gate Drive Circuits (SLUP133) [2] Bill Andreycak, Practical Considerations in High Performance MOSFET, IGBT and MCT Gate Drive Circuits (SLUA105) 18 Copyright © 2008–2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) UCC27423QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC27423QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27424QDGNRQ1 ACTIVE MSOPPowerPAD DGN 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR UCC27424QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM UCC27425QDRQ1 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. 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Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 15-Jul-2011 OTHER QUALIFIED VERSIONS OF UCC27423-Q1, UCC27424-Q1, UCC27425-Q1 : • Catalog: UCC27423, UCC27424, UCC27425 • Enhanced Product: UCC27423-EP, UCC27424-EP NOTE: Qualified Version Definitions: • Catalog - TI's standard catalog product • Enhanced Product - Supports Defense, Aerospace and Medical Applications Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2011 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCC27423QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27424QDGNRQ1 MSOPPower PAD DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 UCC27425QDRQ1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2011 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27423QDGNRQ1 MSOP-PowerPAD DGN 8 2500 346.0 346.0 29.0 UCC27424QDGNRQ1 MSOP-PowerPAD DGN 8 2500 346.0 346.0 29.0 UCC27425QDRQ1 SOIC D 8 2500 340.5 338.1 20.6 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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