UCC18500/1/2/3 UCC28500/1/2/3 UCC38500/1/2/3 BiCMOS PFC/PWM Combination Controller FEATURES PRELIMINARY DESCRIPTION • Combines PFC and 2 Converter Function nd Stage Down The UCC18500 family provides all of the functions necessary for an active power factor corrected preregulator and a second stage DC-to-DC converter. The controller achieves near-unity power factor by shaping the AC input line current waveform to correspond to the AC input line voltage using average current mode control. The DC-to-DC converter uses peak current mode control to perform the step down power conversion. • Controls Boost PWM to Near-unity Power Factor • Accurate Power Limiting • Average Current Mode Control in PFC Stage The PFC stage is leading edge modulated while the second stage is trailing edge synchronized to allow for minimum overlap between the boost and PWM switches. This reduces ripple current in the bulk output capacitor. • Peak Current Mode Control in Second Stage • Programmable Oscillator In order to operate with a three to one range of input line voltages, a line feedforward (VFF) in used to keep input power constant with varying input voltage. Generation of VFF is done using IAC in conjunction with an external single pole filter. This not only reduces external parts count, but avoids the use of high voltage components offering a lower cost solution. The multiplier then divides the line current by the square of VFF. • Leading Edge/Trailing Edge Modulation for Reduced Output Ripple Using SmartSync™ • Low Startup Supply Current • Synchronized Second Stage Start-up, with Programmable Soft-start (continued) • Programmable Second Stage Shut-down BLOCK DIAGRAM VERR ISENSE2 8 7 SS2 VCC GND 13 9 6 7.5V REFERENCE SECOND STAGE SOFT START UVLO2 6.75V OVP/ENBL 4 1.5V UVLO 16V/10 ENABLE – 8.0V + R R S 1.5V 1.3V PFCOVP – 1 VOLTAGE ERROR AMP VSENSE 3 – 0.25V – ZERO POWER PWM (VFF – – PWM + OSC + )2 CLK1 18 MOUT 17 GT1 11 PWRGND 14 PKLMT CURRENT AMP MIRROR 2:1 IAC 12 CLK2 VCC MULT 7.5V 19 GT2 Q X X VFF 10 VCC + ÷ + VREF ILIMIT + VAOUT 20 Q PWM LATCH S R R CLK2 CLK2 CLK1 OSCILLATOR ILIMIT – + 16 15 2 5 ISENSE1 CAOUT RT CT UDG-98189 SLUS419 - AUGUST 1999 UCC18500/1/2/3 UCC28500/1/2/3 UCC38500/1/2/3 DESCRIPTION (cont.) The UCC18500 PFC section incorporates a low offset voltage amplifier with 7.5V reference, a highly linear multiplier capable of a wide current range, a high bandwidth, low offset current amplifier, with a novel noise attenuation configuration, PWM comparator and latch and a high current output driver. Additional PFC features include over-voltage protection, zero power detection to turn-off the output when VAOUT is below 0.25V and peak current and power limiting. ating range with selectable options, and 50% maximum duty cycle. The UCC38500 and UCC38502 have a wide PFC-UVLO threshold (16.5V/10V) for bootstrap bias supply operation. The UCC38501 and UCC38503 are designed with a narrow UVLO range (10.5V/10V) more suitable for fixed bias operation. The UCC38500 and UCC38501 have a narrow UVLO threshold for PWM stage (to allow operation down to 75% of nominal bulk voltage), while the UCC38502 and UCC38503 are configured for a much wider operation range for the PWM stage (down to 50% of bulk nominal voltage). The DC-to-DC section relies on an error signal generated on secondary-side and processes it by performing peak current mode control. The DC-to-DC section also features current limiting, a controlled soft-start, preset oper- CONNECTION DIAGRAMS ABSOLUTE MAXIMUM RATINGS Supply Voltage VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18V Gate Drive Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2A 50% Duty Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1A Input Voltage ISENSE1, ISENSE2 MOUT,VSENSE, OVP, ENBL, . . . . . . . . 11V PKLMT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Input Current, RSET, IAC, PKLMT, ENA . . . . . . . . . . . . . . 10mA Maximum Negative Voltage, GT1, GT2, PKLMT, MOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5V Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DIL-20, SOIC-20 (TOP VIEW) N, DW and J Packages Currents are positive into, negative out of the specified terminal. Consult Packaging Section of Databook for thermal limitations and considerations of packages. All voltages are referenced to GND. ORDERING INFORMATION UCC 850 VAOUT 1 20 VREF RT 2 19 VFF VSENSE 3 18 IAC OVP/ENA 4 17 MOUT CT 5 16 ISENSE1 GND 6 15 CAOUT VERR 7 14 PKLMT ISENSE2 8 13 SS2 VCC 9 12 GT1 GT2 10 11 PWRGND PACKAGE INFORMATION TEMPERATURE RANGE UCC18500 UCC18501 UCC18502 UCC18503 UCC28500 UCC28501 UCC28502 UCC28503 UCC38500 UCC38501 UCC38502 UCC38503 –55° C to +125° C –40° C to +85° C 0° C to +70° C UVLO 16 10.5 16 10.5 16 10.5 16 10.5 16 10.5 16 10.5 2 PRODUCT OPTION UVLO2 HYSTERESIS 1.2 1.2 3.0 3.0 1.2 1.2 3.0 3.0 1.2 1.2 3.0 3.0 PACKAGE J-CDIP N-PDIP DW-SOIC N-PDIP DW-SOIC UCC18500/1/2/3 UCC28500/1/2/3 UCC38500/1/2/3 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications hold for TA=0°C to 70°C for the UCC3850X, –40°C to +85°C for the UCC2850X, and –55°C to +125°C for the UCC1850X, TA = TJ. VCC = 12V, RT = 22k, CT = 330pF. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Supply Current Section Supply Current, Off VCC = 12V (VCC Turn-on Threshold –300mV) Supply Current, On VCC = 12V 150 300 A 4 6 mA UVLO Section VCC Turn-On Threshold (UCCX8500/502) 15.4 16 16.6 V UVLO Hysteresis (UCCX8500/502) 5.4 6 6.2 V 17 17.5 V Shunt Voltage (UCCX8500/502) IVCC = 10mA VCC Turn-On Threshold (UCCX8501/503) 10.2 10.5 10.8 V UVLO Hysteresis (UCCX8501/503) 0.4 0.5 0.6 V TA = 0°C to 70°C 7.388 7.500 7.613 V TA = –40°C to 85°C 7.369 7.500 7.631 V TA = –55°C to125°C 7.313 7.500 7.687 V Voltage Amplifier Section Input Voltage VSENSE Bias Current Open Loop Gain VAOUT = 2V to 5V VOUT High ILOAD = –150 A VOUT Low ILOAD = 150µA 5.4 50 nA 80 dB 5.5 5.6 V 0.05 0.10 V Over Voltage Protection and Enable Section Over Voltage Reference 7.8 8.0 8.2 V Hysteresis 400 500 600 mV 1 1.5 2 V –5 0 5 mV Enable Threshold Current Amplifier Section Input Offset Voltage VCM = 0V, VCAOUT = 3V Input Bias Current VCM = 0V, VCAOUT = 3V –50 nA Input Offset Current VCM = 0V, VCAOUT = 3V 25 nA Open Loop Gain VCM = 0V, VCAOUT = 2V to 5V 90 dB CMRR VCM = 0V to 1.5V, VCAOUT = 3V 80 dB VOUT High ILOAD = –120 A 6.3 V VOUT Low ILOAD = 1mA 0.2 V Gain Bandwidth Product (Note 1) 2.5 MHz Voltage Reference Section Input Voltage TA = 0° C to 70° C 7.388 7.500 7.613 V TA = –40° C to 85° C 7.369 7.500 7.631 V TA = –55° C to 125° C 7.313 7.500 7.687 V Load Regulation IREF = 1mA to 2mA 5 10 mV Line Regulation VCC = 12V to 16V 10 20 mV Short Circuit Current VREF = 0V –25 mA Oscillator Section Initial Accuracy TA = 25°C Voltage Stability VCC = 10.8V to 15V 85 Total Variation Line, Temp 100 80 Ramp Peak Voltage 4.5 Ramp Amplitude Voltage (peak to peak) 5 4 3 115 1 kHz % 120 kHz 5.5 V V UCC18500/1/2/3 UCC28500/1/2/3 ELECTRICAL CHARACTERISTICS: Unless otherwise specified, these specifications hold for TA=0°C to 70°C for the UCC3850X, –40°C to +85°C for the UCC2850X, and –55°C to +125°C for the UCC1850X, TA = TJ. VCC = 12V, RT = 22k, CT = 330pF. PARAMETER TEST CONDITIONS MIN TYP –15 0 MAX UNITS Peak Current Limit Section PKLMT Reference Voltage PKLMT Propogation Delay 15 mV 300 ns Multiplier Section High Line, Low Power IAC = 500 A, VFF = 4.7V, VAOUT = 1.25V –6 A High Line, High Power IAC = 500 A, VFF = 4.7V, VAOUT = 5V –90 A Low Line, Low Power IAC = 150 A, VFF = 1.4V, VAOUT = 1.25V –19 A Low Line, High Power IAC = 150 A, VFF = 1.4V, VAOUT = 5V –300 A IAC Limited IAC = 150 A, VFF = 1.3V, VAOUT = 5V –300 A Gain Constant (K) IAC = 300 A, VFF = 2.8V, VAOUT = 2.5V 1 Zero Current IAC = 150 A, VFF = 1.4V, VAOUT = 0.25V 0 –2 IAC = 500 A, VFF = 4.7V, VAOUT = 0.25V 0 –2 A –3 µA IAC = 500 A, VFF = 4.7V, VAOUT = 0.5V Power Limit IAC = 150 A, VFF = 1.4V, VAOUT = 5V 1/V –420 A W Zero Power Section Zero Power Comparator Threshold Measured on VAOUT 0.10 0.25 0.40 V PFC Gate Driver Section GT1 Pull Up Resistance IOUT = –100mA 7 GT1 Pull Down Resistance IOUT = 100mA 3 GT1 Output Rise Time CLOAD = 1nF, RLOAD = 10 25 ns GT1 Output Fall Time CLOAD = 1nF, RLOAD = 10 10 ns 94 % Maximum Duty Cycle Second Stage UVLO (UVLO2) PWM Turn-on Reference (UCCX8500/501) 6.30 Hysteresis (UCCX8500/501) 6.75 7.30 1.2 PWM Turn-on Reference (UCCX8502/503) 6.30 Hysteresis (UCCX8502/503) 6.75 V V 7.30 3 V V Second Stage Soft Start Section SS2 Charge Current –7.5 VERR IVERR = 2mA, UVLO = Low SS2 Discharge Current ENA = High, UVLO = Low, SS2 = 2.5V –10 –12.5 µA 300 mV 3 10 mA 44 50 % Second Stage Duty Cycle Clamp Section Maximum Duty Cycle Second Stage Pulse by Pulse Current Sense Section Current Sense Comparator Threshold VERR = 2.5V, Measured on ISENSE2 .95 1.05 1.15 V 1.15 1.30 1.45 V Second Stage Over Current Limit Section Peak Current Comparator Threshold Input Bias Current 50 nA Second Stage Gate Driver Section GT2 Pull Up Resistance IOUT = –200mA 7 GT2 Pull Down Resistance IOUT = 100mA 3 GT2 Output Rise Time CLOAD = 1nF, RLOAD = 10 25 ns GT2 Output Fall Time CLOAD = 1nF, RLOAD = 10 25 ns Note 1: Guaranteed by design, not 100% tested in production. 4 UCC18500/1/2/3 UCC28500/1/2/3 UCC38500/1/2/3 PIN DESCRIPTIONS CAOUT: (current amplifier output) This is the output of a wide bandwidth op amp that senses line current and commands the PFC pulse width modulator (PWM) to force the correct current. This output can swing close to GND, allowing the PWM to force zero duty cycle when necessary. IMO = K • VFF 2 Connect current loop compensation components between MOUT and CAOUT. OVP/ENBL: (over-voltage/enable) A window comparator input which will disable the PFC output driver if the boost output is 6.67% above nominal or will disable both the PFC and second stage output drivers and reset SS2 if pulled below 1.5V. This input is also used to determine the active range of the second stage PWM. CT: (Oscillator timing capacitor) A capacitor from CT to GND will set the oscillator frequency according to: f= (VAOUT − 1.0) • I AC 0 .725 (RT • CT ) GND: (ground) All voltages measured with respect to ground. VCC and VREF should be bypassed directly to GND with a 0.1µF or larger ceramic capacitor. The timing capacitor discharge current also returns to this pin, so the lead from the oscillator timing capacitor to GND should be as short and direct as possible. PKLMT: (PFC peak current limit) The threshold for peak limit is 0V. Use a resistor divider from the negative side of the current sense resistor to VREF to level-shift this signal to a voltage corresponding to the desired overcurrent threshold across the current sense resistor. PWRGND: Ground for totem pole output drivers. GT1: (gate drive) The output drive for the PFC stage is a totem pole MOSFET gate driver on GT1. Use a series gate resistor of at least 5 ohms to prevent interaction between the gate impedance and the GT1 output driver that might cause the GT1 to overshoot excessively. Some overshoot of the GT1 output is always expected when driving a capacitive load. RT: (oscillator charging current) A resistor from RT to GND is used to program oscillator charging current. A resistor between 10kΩ and 100kΩ is recommended. SS2: (soft start for PWM) SS2 is at ground for either enable low or OVP/ENBL below the UVLO2 threshold conditions. When enabled, SS2 will charge an external capacitor with a current source. This voltage will be used as the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a disable command or a UVLO2 dropout, SS2 will quickly discharge to disable the PWM. GT2: (gate drive) Same as output GT1 for the second stage output drive. Limited to 50% maximum duty cycle. IAC: (input ac current) This input to the analog multiplier is a current. The multiplier is tailored for very low distortion from this current input (IAC) to MOUT, so this is the only multiplier input which should be used for sensing instantaneous line voltage. Recommended maximum IAC is 500µA. VAOUT: (voltage amplifier output) This is the output of the opamp that regulates output voltage. The voltage amplifier output is internally limited to approximately 5.5V to prevent overshoot. ISENSE1: (current sense) This is the non-inverting input to the current amplifier. This input and the inverting input MOUT remain functional down to and below GND. VCC: (positive supply voltage) Connect to a stable source of at least 20mA between 12V and 17V for normal operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET gate capacitances. To prevent inadequate Gate Drive signals, the output devices will be inhibited unless VCC exceeds the upper under-voltage lockout threshold and remains above the lower threshold. ISENSE2: (current sense) A resistor from the source of the lower FET to ground generates the input signal for the peak limit control of the second stage. The oscillator ramp can also be summed into this pin, for slope compensation. MOUT: (multiplier output and current sense amplifier inverting input) The output of the analog multiplier and the inverting input of the current amplifier are connected together at MOUT. As the multiplier output is a current, this is a high impedance input so the amplifier can be configured as a differential amplifier to reject ground noise. Multiplier output current is given by: VERR: Voltage amp error signal for the second stage. The error signal is generated by an external amplifier which drives this pin. VFF: (RMS feed forward signal) VFF signal generated at this pin by mirroring Iac into a single pole external filter. 5 UCC18500/1/2/3 UCC28500/1/2/3 UCC38500/1/2/3 PIN DESCRIPTIONS RVFF = VFFMAX IACMAX 2• • 0.9 2 VREF: (voltage reference output) VREF is the output of an accurate 7.5V voltage reference. This output is capable of delivering 10mA to peripheral circuitry and is internally short circuit current limited. VREF is disabled and will remain at 0V when VCC is below the UVLO threshold. Bypass VREF to GND with a 0.1µF or larger ceramic capacitor for best stability. VSENSE: (voltage amplifier inverting input) This is normally connected to a compensation network and to the boost converter output through a divider network. APPLICATION INFORMATION The UCC38500 is designed to incorporate all the control functions required for a power factor correction circuit and a second stage dc-dc converter. The PFC function is implemented as a full feature, average current mode controller Integrated Circuit for excellent performance. In addition, the input voltage feedforward function is implemented in a simplified manner. Current from IAC is mirrored over to the VFF pin. By simply adding a resistor and capacitor (to attenuate 120Hz ripple) a voltage is developed which is proportional to line voltage. This eliminates several components normally connected to the line. One of the main system challenges in designing systems with a PFC front end is coordinating the turn-on and turn-off on the dc-dc converter. If the dc-dc converter is allowed to turn on before the boost converter is operational, it must operate at a much-reduced voltage and therefore can represent a large current draw to the boost converter. This start-up sequencing is handled internally by the UCC38500. The UCC38500 monitors the output voltage of the PFC converter and holds the dc-dc converter off until the output is within 10% of its regulation point. Once the trip point is reached the dc-dc section goes through a soft start sequence for a controlled, low stress start-up. Similarly if the output voltage drops too low (2 voltage options are available) the dc-dc converter shuts down thereby preventing overstress of the converter. The UCC38500 uses leading edge modulation for the PFC stage and trailing edge modulation for the dc-dc stage. This reduces ripple current in the output capacitor by reducing the overlap in conduction time of the PFC and dc-dc switches. In addition to the reduced ripple current, noise immunity is improved through the current error amplifier implementation. Design details of the PFC section can be found in several references shown below. • UCC3817 data sheet The UCC38500 is optimized to control a boost PFC stage operating in continuous conduction mode, followed by a dc-dc converter (typically a forward topology). It is usual that the dc-dc converter is transformer isolated and therefore its error amplifier will be located on the secondary side. The UCC38500 is configured without an internal error amplifier. The externally generated error signal is fed into the VERR pin. • High Power Factor Preregulator for Off-Line Power Supplies, SEM-800 • Optimizing the Design of a High Power Factor Switching Regulator, SEM-800 A design example for a 2 switch forward converter can be found in: • 250W Off-Line Forward Converter Design Review, SEM-500 The UCC38500 can be configured for voltage mode or current mode control of the second stage. The application figure shows a typical current mode configuration. For voltage mode control the ramp generated by CT is simply fed into the ISENSE2 pin. 6 UNITRODE CORPORATION 7 CONTINENTAL BLVD. • MERRIMACK, NH 03054 TEL. (603) 424-2410 • FAX (603) 424-3460 C1 D3 L1 7 D7 R14 R16 D5 R1 GT1 L1 C5 R11 C20 C12 R3 R10 C6 D1 PGND Q1 R18 VCC BIAS CIRCUIT R17 PKLIMIT VREF R15 C2 R13 VCC BIAS CURRENT VAC 85-260V RMS D2 VCC R4 R3 R10 C4 SGND C7 C3 R2 SGND VSENSE OVP/ENBL SLOPE COMP 20 VREF 8 7 SGND R33 C9 D4 C12 C11 R8 C14 R24 R9 VREF T1 SGND 4 5 6 SGND SGND C10 R27 D6 PGND C16 U3 H11AV1 SGND D8 C17 D7 R22 3 2 1 R32 ISENSE2 L2 SGND R23 PGND C28 VCC C15 PGND R25 Q4 Q3 SLOPE COMP D5 GT2 D12 ISENSE2 Q2 SGND R34 VREF ISENSE2 VERR SS2 13 19 VFF 14 PKLIMIT PWRGND 11 GND 6 18 IAC 15 CAOUT RT 2 9 17 MOUT VCC GT2 10 GT1 12 T2 CT 5 1 VAOUT 3 4 UCC38500 U1 C13 16 ISENSE C8 PKLIMIT R12 R7 R6 R5 PWR GND GT2 GT2 C23 GT1 PGND2 C18 SGND2 C22 D9 1N5819 VO 12V 10A – + 4 3 2 1 GND VOUT VCC U2 NI VREF VFB UC3965 COMP OFFSET 5 6 7 8 C12 R30 R31 C19 C20 R29 R28 TYPICAL APPLICATION CIRCUIT UCC18500/1/2/3 UCC28500/1/2/3 UCC38500/1/2/3 UDG-99138 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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