INTEGRATED CIRCUITS DATA SHEET UDA1345TS Economy audio CODEC Product specification Supersedes data of 2000 Dec 19 2002 May 28 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS CONTENTS 1 FEATURES 1.1 1.2 1.3 1.4 General Multiple format input interface DAC digital sound processing Advanced audio configuration 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 QUICK REFERENCE DATA 5 BLOCK DIAGRAM 6 PINNING 7 FUNCTIONAL DESCRIPTION 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.10.1 7.10.2 7.10.3 7.10.4 7.10.5 7.10.6 7.11 7.11.1 7.11.2 7.11.3 7.11.4 7.11.5 7.12 7.12.1 7.12.2 Analog-to-Digital Converter (ADC) Analog front-end Decimation filter (ADC) Interpolation filter (DAC) Double speed Noise shaper (DAC) The Filter Stream DAC (FSDAC) Power control L3MODE or static pin control L3 microcontroller mode Pinning definition System clock Multiple format input/output interface ADC input voltage control Overload detection (ADC) DC cancellation filter (ADC) Static pin mode Pinning definition System clock Mute and de-emphasis Multiple format input/output interface ADC input voltage control L3 interface Address mode Data transfer mode 2002 May 28 8 LIMITING VALUES 9 THERMAL CHARACTERISTICS 10 DC CHARACTERISTICS 11 AC CHARACTERISTICS (ANALOG) 12 AC CHARACTERISTICS (DIGITAL) 13 APPLICATION INFORMATION 14 PACKAGE OUTLINE 15 SOLDERING 15.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 15.2 15.3 15.4 15.5 2 16 DATA SHEET STATUS 17 DISCLAIMERS NXP Semiconductors Product specification Economy audio CODEC 1 UDA1345TS FEATURES 1.1 General • Low power consumption • 2.4 to 3.6 V power supply range with 3.0 V typical • 5 V tolerant TTL compatible digital inputs • 256, 384 and 512fs system clock • Supports sampling frequencies from 8 to 100 kHz • Non-inverting ADC plus integrated high-pass filter to cancel DC offset 1.4 Advanced audio configuration • Stereo single-ended input configuration • The ADC supports 2 V (RMS) input signals • Overload detector for easy record level control • Stereo line output (under microcontroller volume control), no post filter required • Separate power control for ADC and DAC • High linearity, dynamic range and low distortion. • Integrated digital interpolation filter plus non-inverting DAC 2 • Functions controllable either by L3 microcontroller interface or via static pins The UDA1345TS is a single-chip stereo Analog-to-Digital Converter (ADC) and Digital-to-Analog Converter (DAC) with signal processing features employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in low-voltage low-power portable digital audio equipment which incorporates recording and playback functions. • The UDA1345TS is pin and function compatible with the UDA1344TS • Small package size (SSOP28). 1.2 Multiple format input interface • I2S-bus, MSB-justified up to 24 bits and LSB-justified 16, 18 and 20 bits format compatible The UDA1345TS supports the I2S-bus data format with word lengths of up to 24 bits, the MSB justified data format with word lengths of up to 20 bits and the LSB justified serial data format with word lengths of 16, 18 and 20 bits. The UDA1345TS also supports three combined data formats with MSB justified data output and LSB 16, 18 and 20 bits data input. • Three combined data formats with MSB data output and LSB 16, 18 and 20 bits data input • 1fs input and output format data rate. 1.3 GENERAL DESCRIPTION DAC digital sound processing The sound processing features of the UDA1345TS can only be used in L3 microcontroller mode: The UDA1345TS can be used either with static pin control or under L3 microcontroller interface. In L3 mode the UDA1345TS has basic sound features in playback mode such as de-emphasis, volume control and soft mute. • Digital dB-linear volume control (low microcontroller load) via L3 microcontroller with 1 dB steps • Digital de-emphasis for 32, 44.1 and 48 kHz • Soft mute via cosine roll-off (in 1024 samples). Note: in contrast to the UDA1344TS, the UDA1345TS does not have bass-boost and treble. 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1345TS 2002 May 28 SSOP28 DESCRIPTION plastic shrink small outline package; 28 leads; body width 5.3 mm 3 VERSION SOT341-1 NXP Semiconductors Product specification Economy audio CODEC 4 UDA1345TS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT 2.4 2.4 2.4 operating mode − ADC power-down − ADC power-down all − operating mode − DAC power-down − operating mode − DAC power-down − operating mode − ADC and DAC power-down − −40 3.0 3.0 3.0 10 600 300 4 50 2.0 200 5 350 − 3.6 3.6 3.6 14 800 800 7.0 150 3.0 400 8 500 +85 V V V mA μA μA mA μA mA μA mA μA °C −2.5 −1.5 −0.5 dBFS − − −85 −80 −80 −75 dB dB − − −36 −34 −30 −30 dB dB 90 90 − 96 94 100 − − − dB dB dB 850 900 950 mV − − −85 −80 −80 −71 dB dB − − − −37 −35 100 −30 −30 − dB dB dB 90 90 100 98 − − dB dB Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current IDDA(DAC) DAC analog supply current IDDO(DAC) DAC operational amplifier supply current IDDD digital supply current Tamb ambient temperature Analog-to-digital converter digital output level at 1 V (RMS) input voltage (THD + N)/S total harmonic distortion-plus-noise to signal ratio Do S/N αcs signal-to-noise ratio notes 1 and 2 at 0 dB, 1 V (RMS) fs = 44.1 kHz fs = 96 kHz at −60 dB, 1 mV (RMS); A-weighted fs = 44.1 kHz fs = 96 kHz Vi = 0 V; A-weighted fs = 44.1 kHz fs = 96 kHz channel separation Digital-to-analog converter output voltage (RMS value) Vo(rms) (THD + N)/S total harmonic distortion plus noise-to-signal ratio αcs S/N 2002 May 28 channel separation signal-to-noise ratio note 3 at 0 dB fs = 44.1 kHz fs = 96 kHz at −60 dB; A-weighted fs = 44.1 kHz fs = 96 kHz code = 0; A-weighted fs = 44.1 kHz fs = 96 kHz 4 NXP Semiconductors Product specification Economy audio CODEC SYMBOL UDA1345TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT − 64 − mW − − − 36 46 2.2 − − − mW mW mW Power performance PADDA PDA PAD PPD power consumption in record and playback mode power consumption in playback only mode power consumption in record only mode power consumption in Power-down mode Notes 1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. 3. The output voltage of the DAC scales proportionally with the power supply voltage. 2002 May 28 5 NXP Semiconductors Product specification Economy audio CODEC 5 UDA1345TS BLOCK DIAGRAM VDDA(ADC) VSSA(ADC) handbook, full pagewidth 2 VINL 3 VADCP 1 VADCN 7 Vref(A) 6 0 dB/6 dB SWITCH 4 5 0 dB/6 dB SWITCH ADC ADC 8 VDDD VSSD DATAO BCK WS DATAI 21 DECIMATION FILTER 10 20 11 MC1 MC2 MP5 DC-CANCELLATION FILTER 18 13 16 L3-BUS INTERFACE DIGITAL INTERFACE 17 14 15 19 12 MP1 VINR 9 MP2 MP3 MP4 SYSCLK INTERPOLATION FILTER UDA1345TS NOISE SHAPER DAC DAC VOUTL 26 24 25 27 VDDO VSSO 23 VDDA(DAC) 22 VSSA(DAC) Fig.1 Block diagram. 2002 May 28 6 28 Vref(D) VOUTR MGS875 NXP Semiconductors Product specification Economy audio CODEC 6 UDA1345TS PINNING SYMBOL PIN TYPE DESCRIPTION VSSA(ADC) 1 analog ground pad ADC analog ground VDDA(ADC) 2 analog supply pad ADC analog supply voltage VINL 3 analog input pad ADC input left Vref(A) 4 analog pad ADC reference voltage VINR 5 analog input pad ADC input right VADCN 6 analog pad ADC negative reference voltage VADCP 7 analog pad ADC positive reference voltage MC1 8 5 V tolerant digital input pad with internal pull-down pad mode control 1 (pull-down) MP1 9 5 V tolerant slew rate controlled digital output pad multi purpose pin 1 VDDD 10 digital supply pad digital supply voltage VSSD 11 digital ground pad digital ground SYSCLK 12 5 V tolerant digital Schmitt triggered input pad system clock 256, 384 or 512fs MP2 13 3-level input pad multi purpose pin 2 MP3 14 5 V tolerant digital Schmitt triggered input pad multi purpose pin 3 MP4 15 3-level input pad multi purpose pin 4 BCK 16 5 V tolerant digital Schmitt triggered input pad bit clock input WS 17 5 V tolerant digital Schmitt triggered input pad word select input DATAO 18 5 V tolerant slew rate controlled digital output pad data output DATAI 19 5 V tolerant digital Schmitt triggered input pad data input MP5 20 5 V tolerant digital Schmitt triggered input pad multi purpose pin 5 (pull down) MC2 21 5 V tolerant digital input pad with internal pull-down pad mode control 2 (pull-down) VSSA(DAC) 22 analog ground pad DAC analog ground VDDA(DAC) 23 analog supply pad DAC analog supply voltage VOUTR 24 analog output pad DAC output right VDDO 25 analog supply pad operational amplifier supply voltage VOUTL 26 analog output pad DAC output left VSSO 27 analog ground pad operational amplifier ground Vref(D) 28 analog pad DAC reference voltage 2002 May 28 7 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 7.1 The stereo ADC of the UDA1345TS consists of two 5th-order Sigma-Delta modulators. They have a modified Ritchie-coder architecture in a differential switched capacitor implementation. The oversampling ratio is 64. handbook, halfpage VSSA(ADC) 1 28 Vref(D) VDDA(ADC) 2 27 VSSO 26 VOUTL VINL 3 Vref(A) 4 VINR 5 VADCP 7 25 VDDO 7.2 24 VOUTR The analog front-end is equipped with a selectable 0 dB or 6 dB gain block (the pin to select this mode is given in Section 7.10). This block can be used in applications in which both 1 V (RMS) and 2 V (RMS) input signals can be input to the UDA1345TS. 23 VDDA(DAC) VADCN 6 UDA1345TS 22 VSSA(DAC) MC1 8 21 MC2 MP1 9 20 MP5 VDDD 10 19 DATAI VSSD 11 18 DATAO MP2 13 16 BCK MP3 14 15 MP4 Analog front-end In applications in which a 2 V (RMS) input signal is used, a 12 kΩ resistor must be used in series with the input of the ADC. This forms a voltage divider together with the internal ADC resistor and ensures that only 1 V (RMS) maximum is input to the IC. Using this application for a 2 V (RMS) input signal, the switch must be set to 0 dB. When a 1 V (RMS) input signal is input to the ADC in the same application, the gain switch must be set to 6 dB. 17 WS SYSCLK 12 Analog-to-Digital Converter (ADC) An overview of the maximum input voltages allowed against the presence of an external resistor and the setting of the gain switch is given in Table 1; the power supply voltage is assumed to be 3 V. MGS876 Fig.2 Pin configuration. Table 1 7 FUNCTIONAL DESCRIPTION RESISTOR (12 kΩ) The UDA1345TS accommodates slave mode only, this means that in all applications the system devices must provide the system clocks (being the system clock itself and the digital audio interface signals). Present The system clock must be locked in frequency to the audio digital interface input signals. The BCK clock can be up to 128fs, or in other words the BCK frequency is 128 times the Word Select (WS) frequency or less: fBCK ≤ 128 × fWS. INPUT GAIN SWITCH MAXIMUM INPUT VOLTAGE 0 dB 2 V (RMS) Present 6 dB 1 V (RMS) Absent 0 dB 1 V (RMS) Absent 6 dB 0.5 V (RMS) 7.3 Decimation filter (ADC) The decimation from 64fs to 1fs is performed in two stages. Important: the WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface. sin x The first stage realizes a 4th-order ------------ characteristic. x This filter decreases the sample rate by 8. The second stage consists of 2 half-band filters and a recursive filter, each decimating by a factor of 2. Note: the sampling frequency range is from 8 to 100 kHz, however for the 512fs clock mode the sampling range is from 8 to 55 kHz. 2002 May 28 Application modes using input gain stage 8 NXP Semiconductors Product specification Economy audio CODEC Table 2 UDA1345TS Digital decimation filter characteristics ITEM Pass-band ripple Stop band Dynamic range Overall gain when a 0 dB signal is input to ADC to digital output CONDITIONS VALUE (dB) 0 − 0.45fs ±0.05 >0.55fs −60 0 − 0.45fs 114 DC −1.16 7.7 The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC is scaled proportionally with the power supply voltage. Note: the digital output level is inversely proportional to the ADC analog power supply. This means that with a constant analog input level and increasing power supply the digital output level will decrease proportionally. 7.4 7.8 The digital filter interpolates from 1 to 128fs by means of a cascade of a recursive filter and an FIR filter. Digital interpolation filter characteristics ITEM Passband ripple Stopband Dynamic range Gain 7.5 CONDITIONS VALUE (dB) 0 − 0.45fs ±0.03 >0.55fs −65 0 − 0.45fs 116.5 DC −3.5 Power control In the event that the DAC is powered-up or powered-down, a cosine roll-off mute will be performed (when powering down) or a cosine roll-up de-mute (when powering up) will be performed. This is in order to prevent clicks when powering up or down. This power-on/off mute takes 32 × 4 = 128 samples. Interpolation filter (DAC) Table 3 The Filter Stream DAC (FSDAC) 7.9 L3MODE or static pin control The UDA1345TS can be used under L3 microcontroller interface mode or under static pin control. The mode can be set via the Mode Control (MC) pins MC1 (pin 8) and MC2 (pin 21). The function of these pins is given in Table 4. Double speed Table 4 Mode Control pins MC1 and MC2 Since the device supports a sampling range of 8 to 100 kHz, the device can support double speed (e.g. for 44.1 kHz and 48 kHz sampling frequency) by just doubling the system speed. In double speed all features are available. L3MODE LOW LOW Test modes LOW HIGH HIGH LOW 7.6 Static pin mode HIGH HIGH MODE Noise shaper (DAC) The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a filter stream digital-to-analog converter. 2002 May 28 MC2 MC1 Important: in L3MODE the UDA1345TS is completely pin and function compatible with the UDA1340M and the UDA1344TS. Note: the UDA1345TS does NOT support bass-boost and treble. 9 NXP Semiconductors Product specification Economy audio CODEC 7.10 UDA1345TS L3 microcontroller mode The UDA1345TS is set to the L3 microcontroller mode by setting both MC1 (pin 8) and MC2 (pin 21) LOW. In practice the output is used to indicate whenever the output data, in either the left or right channel, is greater than −1 dB (the actual figure is −1.16 dB) of the maximum possible digital swing. When this condition is detected the OVERFL output is forced HIGH for at least 512fs cycles (11.6 ms at fs = 44.1 kHz). This time-out is reset for each infringement. The definition of the control registers is given in Section 7.12. 7.10.1 PINNING DEFINITION The pinning definition under L3 microcontroller interface is given in Table 5. Table 5 9 OVERFL output MP2 13 L3MODE input MP3 14 L3CLOCK input MP4 15 L3DATA input MP5 20 ADC 1 V or 2 V (RMS) input control 7.10.2 An optional IIR high-pass filter is provided to remove unwanted DC components. The operation is selected by the microcontroller via the L3-bus. The filter characteristics are given in Table 6. DESCRIPTION MP1 DC CANCELLATION FILTER (ADC) 7.10.6 Pinning definition under L3 control SYMBOL PIN OVERLOAD DETECTION (ADC) 7.10.5 Table 6 DC cancellation filter characteristics ITEM CONDITIONS Pass-band ripple none Pass-band gain 0 Droop SYSTEM CLOCK at 0.00045fs Attenuation at DC Under L3 control the options are 256, 384 and 512fs. >40 0 − 0.45fs >110 MULTIPLE FORMAT INPUT/OUTPUT INTERFACE 7.11 The UDA1345TS supports the following data input/output formats under L3 control: • 0.031 at 0.00000036fs Dynamic range 7.10.3 VALUE (dB) I2S-bus Static pin mode The UDA1345TS is set to static pin control mode by setting both MC1 (pin 8) and MC2 (pin 21) HIGH. with data word length of up to 24 bits • MSB-justified serial format with data word length of up to 20 bits 7.11.1 • LSB-justified serial format with data word lengths of 16, 18 or 20 bits The pinning definition under static pin control is given in Table 7. • Three combined data formats with MSB data output and LSB 16, 18 and 20 bits data input. Table 7 Pinning definition for static pin control SYMBOL PIN The formats are illustrated in Fig.3. Left and right data channel words are time multiplexed. 7.10.4 PINNING DEFINITION MP1 9 data input/output setting MP2 13 3-level pin controlling de-emphasis and mute MP3 14 256fs or 384fs system clock MP4 15 3-level pin to control ADC power mode and 1 V (RMS) or 2 V (RMS) input MP5 20 data input/output setting ADC INPUT VOLTAGE CONTROL The UDA1345TS supports a 2 V (RMS) input using a series resistor of 12 kΩ as described in Section 7.2. In L3 microcontroller mode, the gain can be selected via pin MP5. When MP5 is set LOW, 0 dB gain is selected. When MP5 is set HIGH, 6 dB gain is selected. 2002 May 28 10 DESCRIPTION NXP Semiconductors Product specification Economy audio CODEC 7.11.2 UDA1345TS SYSTEM CLOCK 7.11.5 Under static pin control the options are 256fs and 384fs. With pin MP3 (pin 14) the mode can be set as is given in Table 8. Table 8 In static pin mode the 3-level pin MP4 (pin 15) is used to select 0 or 6 dB gain mode. When MP4 is set LOW the ADC is powered-down. When MP4 is set to half the power supply voltage, then 6 dB gain is selected, and when MP4 is set HIGH then 0 dB gain is selected. MP3 256fs system clock LOW 384fs system clock HIGH 7.11.3 The UDA1345TS supports a 2 V (RMS) input using a series resistor as described in Section 7.2. System clock settings under static pin mode MODE Table 11 MP4 mode settings (static mode) MODE MUTE AND DE-EMPHASIS Under static pin control via MP2 de-emphasis and mute can be selected for the playback path. The definition of the MP2 pin is given in Table 9. Table 9 Settings for pin MP2 MODE MP2 No de-emphasis and mute LOW De-emphasis 44.1 kHz 0.5VDDD Muted 7.11.4 HIGH MULTIPLE FORMAT INPUT/OUTPUT INTERFACE The data input/output formats supported under static pin control are as follows: • I2S-bus with data word length of up to 24 bits • MSB-justified serial format with data word length of up to 24 bits • Two combined data formats with MSB data output and LSB 16 and 20 bits data input. The data formats can be selected using pins MP1 (pin 9) and MP5 (pin 20) as given in Table 10. Table 10 Data format settings under static pin control INPUT FORMAT MP1 MP5 MSB-justified LOW LOW I2S-bus LOW HIGH MSB output LSB 20 input HIGH LOW MSB output LSB 16 input HIGH HIGH The formats are illustrated in Fig.3. Left and right data channel words are time multiplexed. 2002 May 28 ADC INPUT VOLTAGE CONTROL 11 MP4 ADC Power-down mode LOW 6 dB gain mode MID 0 dB gain mode HIGH RIGHT >=8 3 1 2 3 BCK DATA MSB B2 LSB MSB >=8 B2 LSB MSB INPUT FORMAT I2S-BUS LEFT WS 1 2 RIGHT >=8 3 1 2 LSB MSB B2 >=8 3 BCK DATA MSB B2 LSB MSB B2 NXP Semiconductors 2 Economy audio CODEC 1 handbook, full pagewidth 2002 May 28 LEFT WS MSB-JUSTIFIED FORMAT WS RIGHT LEFT 16 15 2 1 16 B15 LSB MSB 15 2 1 BCK 12 MSB DATA B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS RIGHT LEFT 18 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 B17 LSB 2 1 BCK DATA MSB B2 B3 B4 B2 B3 B4 LSB-JUSTIFIED FORMAT 18 BITS WS LEFT 19 18 RIGHT 17 16 15 1 20 B19 LSB MSB 19 18 17 16 15 BCK DATA MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 B19 LSB MGG841 LSB-JUSTIFIED FORMAT 20 BITS Fig.3 Serial interface formats. Product specification 2 UDA1345TS 20 NXP Semiconductors Product specification Economy audio CODEC 7.12 UDA1345TS L3 interface Table 12 Selection of data transfer The UDA1345TS has a microcontroller input mode. In the microcontroller mode, all of the digital sound processing features and the system controlling features can be controlled by the microcontroller. The controllable features are: • System clock frequency • Data input format • Power control • DC filtering • Volume • Mute. The exchange of data and control information between the microcontroller and the UDA1345TS is accomplished through a serial hardware interface comprising the following pins: 0 0 DATA (volume, de-emphasis, mute, and power control) 0 1 not used 1 0 STATUS (system clock frequency, data input format and DC filter) 1 1 not used 7.12.2 TRANSFER DATA TRANSFER MODE The selection preformed in the address mode remains active during subsequent data transfers, until the UDA1345TS receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, shown in Fig.4. The maximum input clock and data rate is 128fs. All transfers are byte wise, i.e. they are based on groups of 8 bits. Data will be stored in the UDA1345TS after the eighth bit of a byte has been received. A multibyte transfer is illustrated in Fig.6. • L3DATA: microcontroller interface data line • L3MODE: microcontroller interface mode line • L3CLOCK: microcontroller interface clock line. Information transfer via the microcontroller bus is LSB first, and is organized in accordance with the so called ‘L3’ format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 5). 7.12.2.1 The address mode is required to select a device communicating via the L3-bus and to define the destination register set for the data transfer mode. Data transfer for the UDA1345TS can only be in one direction: for the UDA1345TS, data can only be written to the device. Programming the sound processing and other features The feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred, being DATA or STATUS. This is performed in the address mode, bit 1 and bit 0 (see Table 12). The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) are the values that are placed in the selected registers. Important: since the UDA1345TS does not have a Power-up reset circuit, after power up the L3 interface registers MUST be initialized. ADDRESS MODE When the data transfer of type DATA is selected, the features Volume, De-emphasis, Mute and Power control can be controlled. When the data transfer of type STATUS is selected, the features system clock frequency, data input format and DC filter can be controlled. The address mode is used to select a device for subsequent data transfer and to define the destination register set (DATA or STATUS). The address mode is characterized by L3MODE being LOW and a burst of 8 pulses on L3CLOCK, accompanied by 8 data bits. The fundamental timing is shown in Fig.4. Data bits 0 and 1 indicate the type of subsequent data transfer as given in Table 12. 2002 May 28 BIT 0 Data bits 7 to 2 represent a 6-bit device address, with bit 7 being the MSB and bit 2 the LSB. The address of the UDA1345TS is 000101 (bit 7 to bit 2). In the event that the UDA1345TS receives a different address, it will deselect its microcontroller interface logic. • De-emphasis 7.12.1 BIT 1 13 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS handbook, full pagewidth L3MODE t s(MA) t h(MA) tLC tHC t s(MA) t h(MA) L3CLOCK Tcy t s(DAT) t h(DAT) BIT 0 L3DATA BIT 7 MGL883 Fig.4 Timing address mode. handbook, full pagewidth thalt thalt L3MODE tLC t s(MT) Tcy tHC t h(MT) L3CLOCK t h(DAT) L3DATA write t s(DAT) BIT 7 BIT 0 MGL884 Fig.5 Timing for data transfer mode. 2002 May 28 14 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS thalt handbook, full pagewidth L3MODE L3CLOCK L3DATA address data byte #1 data byte #2 address MGD018 Fig.6 Multibyte transfer. Table 13 Data transfer of type status LAST IN TIME FIRST IN TIME REGISTER SELECTED BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 SC1 SC0 IF2 IF1 IF0 DC System Clock frequency (5 : 4); data Input Format (3 : 1); DC-filter Table 14 Data transfer of type data LAST IN TIME FIRST IN TIME REGISTER SELECTED BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 VC5 VC4 VC3 VC2 VC1 VC0 0 1 0 0 0 0 0 0 not used 1 0 0 DE1 DE0 MT 0 0 De-Emphasis (4 : 3); MuTe 1 1 0 0 0 0 PC1 PC0 2002 May 28 15 Volume Control (5 : 0) Power Control (1 : 0) NXP Semiconductors Product specification Economy audio CODEC 7.12.2.2 UDA1345TS System clock frequency Table 18 Volume settings A 2-bit value (SC1 and SC0) to select the used external clock frequency (see Table 15). VC5 VC4 VC3 VC2 VC1 VC0 Table 15 System clock frequency settings VOLUME (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 −1 0 0 0 0 1 1 −2 SC1 SC0 FUNCTION 0 0 512fs : : : : : : : 0 1 384fs 1 1 0 0 1 1 1 0 256fs −50 1 1 0 1 0 0 −52 1 1 not used 1 1 0 0 0 1 −54 1 1 0 0 1 0 −57 1 1 0 1 1 1 −60 1 1 1 0 0 0 −66 1 1 1 0 0 1 −∞ 7.12.2.3 Data input format A 3-bit value (IF2 to IF0) to select the used data format (see Table 16). Table 16 Data input format settings IF2 IF1 IF0 FUNCTION 0 0 0 I2S-bus 0 0 1 LSB-justified; 16 bits 0 1 0 LSB-justified; 18 bits 0 1 1 LSB-justified; 20 bits 1 0 0 MSB-justified 1 0 1 MSB-justified output/ LSB-justified 16 bits input 1 1 1 1 0 1 : : : : : : : 1 1 1 1 1 1 −∞ 7.12.2.6 A 2-bit value to enable the digital de-emphasis filter. Table 19 De-emphasis settings DE1 DE0 0 0 no de-emphasis MSB-justified output/ LSB-justified 18 bits input 0 1 de-emphasis; 32 kHz 1 0 de-emphasis; 44.1 kHz MSB-justified output/ LSB-justified 20 bits input 1 1 de-emphasis; 48 kHz 7.12.2.7 7.12.2.4 De-emphasis DC filter FUNCTION Mute A 1-bit value to enable the digital DAC mute (playback). A 1-bit value to enable the digital DC filter (see Table 17). Table 20 DAC mute Table 17 DC filtering DC 7.12.2.5 FUNCTION 0 no DC filtering 1 DC filtering Volume control A 6-bit value to program the left and right channel volume attenuation (VC5 to VC0). The range is 0 dB to −∞ dB in steps of 1 dB (see Table 18). 2002 May 28 16 MT FUNCTION 0 no muting 1 muting NXP Semiconductors Product specification Economy audio CODEC 7.12.2.8 UDA1345TS Power control A 2-bit value to disable the ADC and/or DAC to reduce power consumption. Table 21 Power control settings FUNCTION PC1 PC0 ADC DAC off off 0 0 0 1 off on 1 0 on off 1 1 on on 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages referenced to ground; VDDD = VDDA = VDDO = 3 V; Tamb = 25 °C; unless otherwise specified. SYMBOL PARAMETER VDDD Txtal(max) Tstg Tamb Vesd Ilu(prot) digital supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling latch-up protection current Isc(DAC) short-circuit current of DAC CONDITIONS MIN. − − −65 −40 according to JEDEC II specification Tamb = 125 °C; − VDD = 3.6 V Tamb = 0 °C; VDD = 3 V; note 2 − output short-circuited to VSSA(DAC) − output short-circuited to VDDA(DAC) note 1 MAX. UNIT 5.0 150 +125 +85 V °C °C °C 200 mA 450 mA 325 mA Notes 1. All VDD and VSS connections must be made to the same power supply. 2. DAC operation after short-circuiting cannot be guaranteed. 9 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2002 May 28 PARAMETER thermal resistance from junction to ambient CONDITIONS in free air 17 VALUE UNIT 90 K/W NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 10 DC CHARACTERISTICS VDDD = VDDA = VDDO = 3.0 V; fs = 44.1 kHz; Tamb = 25 °C; RL = 5 kΩ; note 1; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies VDDA(ADC) VDDA(DAC) VDDD IDDA(ADC) ADC analog supply voltage DAC analog supply voltage digital supply voltage ADC analog supply current IDDA(DAC) DAC analog supply current IDDO(DAC) DAC operational amplifier supply current IDDD digital supply current operating mode ADC power-down ADC power-down all operating mode DAC power-down operating mode DAC power-down operating mode ADC and DAC power-down 2.4 2.4 2.4 − − − − − − − − − 3.0 3.0 3.0 10 600 300 4 50 2.0 200 5 350 3.6 3.6 3.6 14 800 800 7.0 150 3.0 400 8 500 V V V mA μA μA mA μA mA μA mA μA 2.0 −0.5 1.3 − − − 5.0 +0.8 1.9 V V V 0.9 0.4 − − − − − − 1.35 0.7 10 10 V V μA pF 0.9VDDD 0.4VDDD −0.5 − − − VDDD + 0.5 V 0.6VDDD V +0.5 V Digital input pins (5 V tolerant TTL compatible) VIH VIL VIH(th) VIL(th) Vhys ⎪ILI⎪ Ci HIGH-level input voltage LOW-level input voltage HIGH-level threshold input voltage LOW-level threshold input voltage Schmitt trigger hysteresis voltage input leakage current input capacitance 3-level input pins (MP2; MP4) VIH VIM VIL HIGH-level input voltage MIDDLE-level input voltage LOW-level input voltage Digital output pins VOH VOL HIGH-level output voltage LOW-level output voltage IOH = −2 mA IOL = 2 mA 0.85VDDD − − − − 0.4 V V with respect to VSSA 0.45VDDA 0.5VDD 0.55VDDA V − − kΩ kΩ Analog-to-digital converter Vref(A) reference voltage Ro(ref) Ri Vref(A) reference output resistance input resistance fi = 1 kHz A 2002 May 28 18 − − 24 12 NXP Semiconductors Product specification Economy audio CODEC SYMBOL Ci PARAMETER UDA1345TS CONDITIONS MIN. − input capacitance TYP. 20 MAX. UNIT − pF 0.55VDDA V Digital-to-analog converter Vref(D) reference voltage with respect to VSSA 0.45VDDA 0.5VDD A Ro(ref) Ro Io(max) RL CL Vref(D) reference output resistance DAC output resistance maximum output current (THD + N)/S < 0.1%; RL = 800 Ω load resistance load capacitance note 2 − − − 12.5 0.13 1.7 − 3.0 − kΩ Ω mA 3 − − − − 200 kΩ pF Notes 1. All power supply pins (VDD and VSS) must be connected to the same external power supply unit. 2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output in order to prevent oscillations in the output operational amplifier. 2002 May 28 19 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 11 AC CHARACTERISTICS (ANALOG) VDDD = VDDA = VDDO = 3.0 V; fi = 1 kHz; fs = 44.1 kHz; Tamb = 25 °C; RL = 5 kΩ; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Analog-to-digital converter Do digital output level at 1 V (RMS) input voltage ΔVi unbalance between channels −2.5 −1.5 −0.5 dBFS − 0.1 − dB − −85 −80 dB − −80 −75 dB fs = 44.1 kHz − −36 −30 dB fs = 96 kHz − −34 −30 dB fs = 44.1 kHz 90 96 − dB fs = 96 kHz 90 94 − dB − 100 − dB fripple = 1 kHz; Vripple(p-p) = 1% − 30 − dB note 3 850 900 950 mV − 0.1 − dB fs = 44.1 kHz − −85 −80 dB fs = 96 kHz − −80 −71 dB fs = 44.1 kHz − −37 −30 dB fs = 96 kHz − −35 −30 dB notes 1 and 2 (THD + N)/S total harmonic distortion-plus-noise at 0 dB, 1 V (RMS) to signal ratio fs = 44.1 kHz fs = 96 kHz at −60 dB, 1 mV (RMS); A-weighted S/N signal-to-noise ratio αcs channel separation PSRR power supply rejection ratio Vi = 0 V; A-weighted Digital-to-analog converter Vo(rms) output voltage (RMS value) ΔVo unbalance between channels (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB at −60 dB; A-weighted S/N signal-to-noise ratio αcs channel separation PSRR power supply rejection ratio code = 0; A-weighted fs = 44.1 kHz 90 100 − dB fs = 96 kHz 90 98 − dB − 100 − dB fripple = 1 kHz; Vripple(p-p) = 1% − 60 − dB Notes 1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately 1 mA by using a series resistor. 2. The input voltage to the ADC scales proportionally with the power supply voltage. 3. The output voltage of the DAC scales proportionally with the power supply voltage. 2002 May 28 20 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 12 AC CHARACTERISTICS (DIGITAL) VDDD = VDDA = VDDO = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ; all voltages referenced to ground (pins 1, 11, 22 and 27); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT System clock timing; see Fig.7 Tsys system clock cycle fsys = 256fs; note 1 39 88 488 ns fsys = 384fs; note 1 26 59 325 ns fsys = 512fs; note 2 36 44 244 ns 0.30Tsys − 0.70Tsys ns tCWL fsys LOW-level pulse width fsys < 19.2 MHz fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns tCWH fsys HIGH-level pulse width fsys < 19.2 MHz 0.30Tsys − 0.70Tsys ns fsys ≥ 19.2 MHz 0.40Tsys − 0.60Tsys ns tr rise time − − 20 ns tf fall time − − 20 ns Serial input/output data timing; see Fig.8 tBCK bit clock period 1⁄ 128fs − − ns tBCKH bit clock HIGH time 34 − − ns tBCKL bit clock LOW time 34 − − ns tr rise time − − 20 ns tf fall time − − 20 ns ts(DATAI) data input set-up time 20 − − ns th(DATAI) data input hold time 0 − − ns td(DATAO−BCK data output delay time (from BCK falling edge) − − 80 ns td(DATAO−WS) data output delay time (from WS edge) MSB-justified format − − 80 ns 0 − − ns ) th(DATAO) data output hold time ts(WS) word select set-up time 20 − − ns th(WS) word select hold time 10 − − ns Address and data transfer mode timing; see Figs 4 and 5 Tcy L3CLOCK cycle time 500 − − ns tHC L3CLOCK HIGH period 250 − − ns tLC L3CLOCK LOW period 250 − − ns ts(MA) L3MODE set-up time address mode 190 − − ns th(MA) L3MODE hold time address mode 190 − − ns ts(MT) L3MODE set-up time data transfer mode 190 − − ns th(MT) L3MODE hold time data transfer mode 190 − − ns 2002 May 28 21 NXP Semiconductors Product specification Economy audio CODEC SYMBOL UDA1345TS PARAMETER CONDITIONS MIN. TYP. MAX. UNIT ts(DAT) L3DATA set-up time data transfer mode and address mode 190 − − ns th(DAT) L3DATA hold time data transfer mode and address mode 30 − − ns thalt L3MODE halt time 190 − − ns Notes 1. Sampling range from 5 to 100 kHz is supported, with fs = 44.1 kHz typical. 2. Sampling range from 5 to 55 kHz is supported, with fs = 44.1 kHz typical. t CWH handbook, full pagewidth MGR984 t CWL Tsys Fig.7 System clock timing. handbook, full pagewidth WS tBCKH tr ts(WS) td(DATAO-BCK) th(WS) tf BCK tBCKL Tcy th(DATAO) td(DATAO-WS) DATAO ts(DATAI) th(DATAI) DATAI MGL885 Fig.8 Serial interface timing. 2002 May 28 22 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 13 APPLICATION INFORMATION The application information as given in Fig.9 is an optimum application environment. Simplification is possible at the cost of some performance degradation. The following notes apply: • The capacitors at the output of the DAC can be reduced. It should be noted that the cut-off frequency of the DC filter also changes. • The capacitors at the input of the ADC can also be reduced. It should be noted that the cut-off frequency of the capacitor with the 12 kW input resistance of the ADC will also change. VDDA 8LM32A07 R21 1Ω L2 VDDD 8LM32A07 C12 100 μF (16 V) ground C2 C11 100 μF (16 V) R24 R30 SYSCLK DATAO BCK WS DATAI MP1 overload flag left input R28 10 Ω C25 100 nF (63 V) VSSA(ADC) VDDA(ADC) 47 Ω VDDD 10 Ω 100 μF (16 V) C21 system clock handbook, full pagewidth VDDA L1 3V 2 1 100 nF (63 V) VADCN VADCP 6 7 VSSD VDDD 10 11 12 18 4 C22 100 nF (63 V) 16 17 C1 VINL 9 3 47 μF (16 V) 24 right input C6 VOUTR X2 100 Ω left output R22 10 kΩ C8 47 μF (16 V) VINR 5 R23 R26 100 Ω X3 right output R27 10 kΩ 47 μF (16 V) MP2 MP3 MP4 13 28 14 25 27 23 22 VDDO VSSA(DAC) C26 C27 100 nF (63 V) 100 nF (63 V) C7 C10 100 μF (16 V) R25 1Ω 100 μF (16 V) VDDO Fig.9 Application diagram. 23 Vref(D) C23 100 nF (63 V) 15 VSSO 2002 May 28 C5 VOUTL UDA1345TS 47 μF (16 V) X5 C3 47 μF (16 V) 19 26 X4 Vref(A) C4 47 μF (16 V) MGS877 VDDA(DAC) R29 1Ω VDDA NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 14 PACKAGE OUTLINE SSOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm D SOT341-1 E A X c HE y v M A Z 28 15 Q A2 pin 1 index A (A 3) A1 θ Lp L 1 14 w M bp e detail X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 10.4 10.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.1 0.7 8 o 0 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT341-1 2002 May 28 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 24 o NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 15 SOLDERING 15.1 If wave soldering is used the following conditions must be observed for optimal results: Introduction to soldering surface mount packages • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • For packages with leads on two sides and a pitch (e): – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. 15.2 The footprint must incorporate solder thieves at the downstream end. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 220 °C for thick/large packages, and below 235 °C for small/thin packages. 15.3 15.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. 2002 May 28 Manual soldering 25 NXP Semiconductors Product specification Economy audio CODEC 15.5 UDA1345TS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO REFLOW(1) suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2002 May 28 26 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS 16 DATA SHEET STATUS DOCUMENT STATUS(1) PRODUCT STATUS(2) DEFINITION Objective data sheet Development This document contains data from the objective specification for product development. Preliminary data sheet Qualification This document contains data from the preliminary specification. Product data sheet Production This document contains the product specification. Notes 1. Please consult the most recently issued document before initiating or completing a design. 2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17 DISCLAIMERS property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Limited warranty and liability ⎯ Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Applications ⎯ Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Right to make changes ⎯ NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use ⎯ NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe 2002 May 28 27 NXP Semiconductors Product specification Economy audio CODEC UDA1345TS Limiting values ⎯ Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Quick reference data ⎯ The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products ⎯ Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. Terms and conditions of commercial sale ⎯ NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. No offer to sell or license ⎯ Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control ⎯ This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 2002 May 28 28 NXP Semiconductors provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise Customer notification This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. Contact information For additional information please visit: http://www.nxp.com For sales offices addresses send e-mail to: [email protected] © NXP B.V. 2010 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 753503/04/pp29 Date of release: 2002 May 28 Document order number: 9397 750 09587