INTEGRATED CIRCUITS DATA SHEET UDA1320ATS Low-cost stereo filter DAC Preliminary specification Supersedes data of 1999 Oct 11 File under Integrated Circuits, IC01 2000 Jan 10 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS CONTENTS 1 FEATURES 1.1 1.2 1.3 1.4 General Multiple format input interface DAC digital sound processing Advanced audio configuration 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 ORDERING INFORMATION 5 QUICK REFERENCE DATA 6 BLOCK DIAGRAM 7 PINNING 8 FUNCTIONAL DESCRIPTION 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 System clock Application modes Multiple format input interface Static pin mode Pin compatibility Interpolation filter (DAC) Noise shaper Filter-Stream DAC 9 L3 INTERFACE DESCRIPTION 9.1 9.2 9.3 The L3 interface Data transfer mode Programming the features 10 LIMITING VALUES 11 HANDLING 12 QUALITY SPECIFICATION 13 THERMAL CHARACTERISTICS 14 DC CHARACTERISTICS 15 AC CHARACTERISTICS 15.1 15.2 Analog Digital 16 APPLICATION INFORMATION 17 PACKAGE OUTLINE 18 SOLDERING 18.1 18.2 18.3 18.4 Introduction Reflow soldering Wave soldering Repairing soldered joints 19 DEFINITIONS 20 LIFE SUPPORT APPLICATIONS 2000 Jan 10 2 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC 1 UDA1320ATS FEATURES 1.1 General • Low power consumption. • 2.7 to 3.6 V power supply. • Selectable control via L3 microcontroller interface or via static pin control. • 256, 384 and 512fs system clock (fsys), selectable via the L3 interface or 256 and 384fs clock mode via static pin control 2 • supports sampling frequencies from 16kHz to 48kHz. • Portable digital audio equipment, see Fig.8. • Integrated digital filter plus non inverting DAC Digital-to-Analog Converter (DAC). • Set-top boxes • Easy application and no analog post filtering required for DAC. 3 • Slave mode only applications. • Multiple format input interface I2S-bus, MSB-justified and LSB-justified 16,18 and 20 bits format compatible (in L3-mode). The UDA1320ATS/N2 supports the I2S-bus data format with word lengths of up to 20 bits, the MSB-justified data format with word lengths of up to 20 bits and the LSB-justified serial data format with word lengths of 16, 18 and 20 bits. • I2S-bus and LSB-justified 16,18 and 20 bits format compatible in static mode. • 1fs input format data rate. 1.3 The UDA1320ATS/N2 can be used in two modes, either L3-mode or static pin mode. DAC digital sound processing • Digital logarithmic volume control via L3. In the L3-mode, all digital sound processing features must be controlled via the L3 interface, including the selection of the system clock setting. • Digital de-emphasis for 32, 44.1 and 48 kHz fs via L3 or 44.1 kHz fs via static pin control. • Soft mute via static pin control or via L3 interface. 1.4 In the two static-modes, the UDA1320ATS/N2 can be operated in the 256fs and 384fs system clock mode. The mute, de-emphasis for 44.1 kHz and 4 digital input formats (I2S and 16, 18, 20 bits LSB formats) can be selected via static pins. The L3 interface cannot be used in this application mode, also, volume control is not available in this mode. Advanced audio configuration • Stereo line output (under L3 volume control) • High linearity, wide dynamic range, low distortion. 4 GENERAL DESCRIPTION The UDA1320ATS/N2 is a single-chip non inverting stereo DAC employing bitstream conversion techniques. The low power consumption and low voltage requirements make the device eminently suitable for use in digital audio equipment which incorporates playback functions. • Small package size (SSOP16). 1.2 APPLICATIONS ORDERING INFORMATION PACKAGE TYPE NUMBER NAME UDA1320ATS 2000 Jan 10 SSOP16 DESCRIPTION plastic shrink small outline package; 16 leads; body width 4.4 mm 3 VERSION SOT369-1 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC 5 UDA1320ATS QUICK REFERENCE DATA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDDA analog supply voltage 2.7 3.3 3.6 V VDDD digital supply voltage 2.7 3.3 3.6 V IDDA DAC supply current − 6.5 − mA IDDD digital supply current − 3.0 − mA Tamb ambient temperature −40 − +85 °C − 1.0 − V DAC Vo(rms) output voltage (RMS value) note 1, 2 (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB − −90 −85 dB at −60 dB; A-weighted − −38 −35 dB S/N signal-to-noise ratio code = 0; A-weighted − 100 95 dB αcs channel separation − 100 − dB Tamb ambient temperature −40 − +85 °C Notes 1. the output voltage has been changed with respect to the UDA1320TZ/N1. 2. the output voltage scales linearly with the power supply voltage. 6 BLOCK DIAGRAM VSSD VDDD handbook, full pagewidth 4 BCK WS DATAI 7 11 1 2 3 DIGITAL INTERFACE UDA1320A SYSCLK 5 6 CONTROL INTERFACE 10 9 8 APPSEL APPL0 APPL1 APPL2 APPL3 VOLUME/MUTE/DE-EMPHASIS INTERPOLATION FILTER NOISE SHAPER VO(L) DAC 14 13 15 VDDA VSSA Fig.1 Block diagram. 2000 Jan 10 16 DAC 4 12 VREF(DAC) VO(R) MGM816 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC 7 UDA1320ATS PINNING SYMBOL 8 PIN FUNCTIONAL DESCRIPTION 8.1 DESCRIPTION System clock The UDA1320ATS/N2 operates in slave mode only. This means in all applications the system devices must provide the system clock. The system frequency is selectable and depends on the mode of operation. BCK 1 bit clock WS 2 word select DATAI 3 data input VDDD 4 digital power supply VSSD 5 digital ground SYSCLK 6 system clock: 256fs, 384fs, 512fs APPSEL 7 application mode select APPL3 8 application pin 3 APPL2 9 application pin 2 APPL1 10 application pin 1 APPL0 11 application pin 0 VREF(DAC) 12 DAC reference voltage VDDA 13 analog supply voltage VO(L) 14 left output voltage VSSA 15 analog ground VO(R) 16 right output voltage The options are 256fs, 384fs and 512fs for the L3 mode and 256fs plus 384fs for the static mode. The system clock must be locked in frequency to the digital interface input signals. The UDA1320ATS/N2 supports sampling frequencies from 16kHz up to 48kHz 8.2 Application modes The application mode can be set with the tri-value APPSEL pin, to L3 mode (APPSEL = VSSD) or to either of two static modes (APPSEL = 0.5VDDD or APPSEL = VDDD). See Table 1 for APPL0 to APPL3 pin functions (active = HIGH). Table 1 Selection modes via APPSEL (note 1) APPSEL PIN VSSD handbook, halfpage 0.5VDDD (384fs) VDDD (256fs) BCK 1 16 VO(R) APPL0 TEST WS 2 15 VSSA APPL1 L3CLOCK DEEM DEEM DATAI 3 14 VO(L) APPL2 L3MODE SF0 SF0 13 VDDA APPL3 L3DATA SF1 SF1 VDDD 4 UDA1320A VSSD 5 MUTE MUTE 12 VREF(DAC) SYSCLK 6 11 APPL0 APPSEL 7 10 APPL1 APPL3 8 9 For example, in static pin control mode, the output signal can be soft muted by setting APPL0 HIGH. De-emphasis can be switched on for 44.1 kHz by setting APPL1 HIGH. APPL1 LOW will disable de-emphasis. APPL2 Note that when L3 interface is used, an L3 initialisation must be done when the IC is powered up! MGM817 In L3 mode pin APPL0 must be set to LOW. Fig.2 Pin configuration. 2000 Jan 10 5 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC 8.3 UDA1320ATS Multiple format input interface IMPORTANT: UDA1320ATS/N2 differs from the UDA1320TZ/N1 with respect to: L3 mode: • in the static mode 384fs is supported instead of 512fs. • I2S-bus with data word length of up to 20 bits • the output voltage of the DAC. In the UDA1320TZ/N1 this is 800mVrms at 3.0V, now it is 1Vrms at 3.3V power supply • MSB-justified format with data word length up to 20 bits • LSB-justified format with data word length of 16, 18 or 20 bits. 8.6 8.4 Static pin mode The digital filter interpolates from 1 to 128fs by cascading a recursive filter and a FIR filter, see Table 3. The UDA1320ATS/N2 supports the following data input name formats in the static pin mode (via SF0 and SF1): • I2S bus with data word length of up to 20 bits Table 3 • LSB-justified format with data word length of 16, 18 or 20 bits. Pass-band ripple 8.7 SF0 SF1 0 0 LSB-justified 16 bits 0 1 LSB-justified 18 bits 1 0 LSB-justified 20 bits 1 1 8.8 For BCK and WS holds that the BCK frequency must be equal or smaller then 64 times WS, or fBCK =< 64*fWS in both L3 and static mode. Pin compatibility In L3 interface mode the UDA1320ATS/N2 can be used on boards that are designed for the UDA1322. The software for UDA1322 can be used for the UDA1320ATS/N2 to control de-emphasis, volume control and mute and also the status settings like system clock setting and input data format. 2000 Jan 10 0 to 0.45fs ±0.1 >0.55fs −50 0 to 0.45fs 108 Noise shaper Filter-Stream DAC The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to be analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. A post-filter is not needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The formats are illustrated in Fig.3. Left and right data-channel words are time multiplexed. The WS signal must have 50% duty-factor for all LSB-justified modes. 8.5 VALUE (dB) The 3rd-order noise shaper operates at 128fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter-Stream DAC (FSDAC). Input format selection using SF0 and SF1 I2S CONDITION Stop band Dynamic range The UDA1320ATS/N2 also accepts double speed data for double speed data monitoring purposes. FORMAT Interpolation filter characteristics ITEM See Table 2, for the static pin codes of the 4 formats, selectable via SF0 and SF1. Table 2 Interpolation filter (DAC) The output voltage of the FSDAC scales linearly with the power supply voltage. 6 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... RIGHT ≥8 3 1 2 3 BCK DATAI MSB B2 LSB MSB B2 LSB MSB INPUT FORMAT LEFT WS 1 2 ≥8 I2S-BUS RIGHT ≥8 3 1 2 LSB MSB B2 ≥8 3 BCK DATAI MSB B2 LSB MSB B2 Philips Semiconductors 2 Low-cost stereo filter DAC 1 handbook, full pagewidth 2000 Jan 10 LEFT WS MSB-JUSTIFIED FORMAT WS RIGHT LEFT 16 15 2 1 16 B15 LSB MSB 15 2 1 BCK 7 MSB DATAI B2 B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS WS RIGHT LEFT 18 17 16 15 2 1 18 B17 LSB MSB 17 16 15 2 1 B17 LSB 2 1 B19 LSB BCK DATAI MSB B2 B3 B4 B2 B3 B4 LSB-JUSTIFIED FORMAT 18 BITS 19 18 RIGHT 17 16 15 2 1 20 B19 LSB MSB 19 18 17 16 15 BCK DATAI MSB B2 B3 B4 B5 B6 B2 B3 B4 B5 B6 MBK071 LSB-JUSTIFIED FORMAT 20 BITS Fig.3 Serial interface; input format I2S-bus. Preliminary specification LEFT 20 UDA1320ATS WS Philips Semiconductors Preliminary specification Low-cost stereo filter DAC 9 9.1 UDA1320ATS L3 INTERFACE DESCRIPTION Data transfer can only be in one direction, consisting of input to the UDA1320ATS/N2 to program sound processing and other functional features. The L3 interface The following system and digital sound processing features can be controlled in the microcontroller mode of the UDA1320ATS/N2: Data bits 7 to 2 represent a 6-bit device address, bit 7 being the MSB. The address of the UDA1320ATS/N2 is 000101 (bit 7 to bit 2). If the UDA1320ATS/N2 receives a different address, it will deselect its microcontroller interface logic. • System clock frequency • Data input format • De-emphasis for 32 kHz, 44.1 kHz and 48 kHz 9.2 • Volume Data transfer mode The selected address remains active during subsequent data transfers until the UDA1320ATS/N2 receives a new address command. The fundamental timing of data transfers is essentially the same as in the address mode, see Fig.6. The maximum input clock and data rate is 64 fs. All transfers are by 8-bit bytes. Data will be stored in the UDA1320ATS/N2 after reception of a complete byte. See Fig.5 for a multi-byte transfer. • Soft mute. The exchange of data and control information between the microcontroller and the UDA1320ATS/N2 is accomplished through a serial hardware interface comprising the following pins: • L3DATA • L3MODE • L3CLOCK. Table 4 Information transfer through the microcontroller bus is organized in accordance with the L3 format, in which two different modes of operation can be distinguished; address mode and data transfer mode (see Figs 4 and 6). The address mode is required to select a device communicating via the L3 bus and to define the destination registers for the data transfer mode. Selection of data transfer BIT 1 BIT 0 TRANSFER 0 0 DATA (volume, de-emphasis, mute) 0 1 not used 1 0 STATUS (system clock frequency, data input format) 1 1 not used handbook, full pagewidth L3MODE t su(L3)A t h(L3)A t su(L3)A tCLK(L3)L tCLK(L3)H t h(L3)A L3CLCK Tcy(CLK)(L3) t su(L3)DA L3DATA t h(L3)DA BIT 7 BIT 0 MBK072 Fig.4 Timing address mode. 2000 Jan 10 8 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS tstp(L3) handbook, full pagewidth L3MODE L3CLK L3DATA address data byte #1 data byte #2 address MBK074 Fig.5 Multi-byte transfer. handbook, full pagewidth tstp(L3) tstp(L3) L3MODE tCLK(L3)L Tcy(CLK)L3 tCLK(L3)H tsu(L3)D th(L3)D L3CLCK th(L3)DA L3DATA write tsu(L3)DA BIT 0 th(L3)DA BIT 7 MBK073 Fig.6 Timing for data transfer mode. The sound feature values are stored in independent registers. The first selection of the registers is achieved by the choice of data type that is transferred (‘STATUS’ or ‘DATA’ transfer). This is performed in the address mode using bit 1 and bit 0, see Table 4,. The settings that can be controlled with ‘STATUS’ transfer are given in table 5, and 2000 Jan 10 the settings that can be controlled using ‘DATA’ transfer are given in table 6. The second selection is performed by the 2 MSBs of the data byte (bit 7 and bit 6). The other bits in the data byte (bit 5 to bit 0) is the value that is placed in the selected registers. 9 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC Table 5 UDA1320ATS Data transfer of type ‘status’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 REGISTER SELECTED 0 0 SC1 SC0 IF2 IF1 IF0 0 System Clock frequency (1 : 0); data Input Format (2 : 0) 1 0 0 0 0 0 0 0 reserved Table 6 Data transfer of type ‘data’ BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 VC5 VC4 VC3 VC2 VC1 VC0 REGISTER SELECTED Volume Control (5 : 0) 0 1 0 0 0 0 0 0 reserved 1 0 0 DE1 DE0 MT 0 0 DE-emphasis (1 : 0); MuTe 1 1 0 0 0 0 0 1 default setting 9.3 Programming the features Volume control: a 6-bit value to program the volume attenuation (VC5 to VC0), 0 to −∞ dB in steps of 1 dB. When the data transfer of type ‘STATUS’ is selected, the features SYSTEM CLOCK FREQUENCY and DATA INPUT FORMAT can be controlled. Table 9 System clock frequency: a 2-bit value to select the used external clock frequency. Table 7 SC1 System clock settings SC0 FUNCTION Volume settings VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB) 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 −1 0 0 0 0 1 1 −2 0 0 512fs : : : : : : : 0 1 384fs 1 1 1 1 0 1 −60 1 0 256fs 1 1 1 1 1 1 −∞ 1 1 not used Data input format: a 3-bit value to select the data format. De-emphasis: a 2-bit value to enable the digital de-emphasis filter. Table 8 Table 10 De-emphasis settings Data input format settings IF2 IF1 IF0 0 0 0 0 0 1 DE1 DE0 I2S bus 0 0 no de-emphasis LSB-justified, 16 bits 0 1 de-emphasis, 32 kHz 0 de-emphasis, 44.1 kHz 1 de-emphasis, 48 kHz FUNCTION 0 1 0 LSB -justified, 18 bits 1 0 1 1 LSB-justified, 20 bits 1 1 0 0 MSB-justified 1 0 1 not used 1 1 0 not used 1 1 1 not used Mute: a 1-bit value to enable the digital mute. Table 11 Mute setting MT When the data transfer of type ‘DATA’ is selected, the features VOLUME, DE-EMPHASIS and MUTE can be controlled. 2000 Jan 10 FUNCTION 10 FUNCTION 0 no muting 1 muting Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS 10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDDD digital supply voltage note 1 − 5.0 V VDDA analog supply voltage note 1 − 5.0 V Txtal(max) maximum crystal temperature − 150 °C Tstg storage temperature −65 +125 °C Tamb ambient temperature −40 +85 °C Ves electrostatic handling note 2 −3000 +3000 V note 3 −300 +300 V Notes 1. All supply connections must be made to the same power supply. 2. Equivalent to discharging a 100 pF capacitor via a 1.5 kΩ series resistor, except pin 14 which must be specified to −2500V (MIN) and +2500V (MAX). 3. Equivalent to discharging a 200 pF capacitor via a 2.5 µH series inductor. 11 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices. 12 QUALITY SPECIFICATION In accordance with “SNW-FQ-611-E”. The number of the quality specification can be found in the “Quality Reference Handbook”. The handbook can be ordered using the code 9397 750 00192. 13 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) 2000 Jan 10 PARAMETER CONDITIONS thermal resistance from junction to ambient in free air 11 VALUE UNIT 190 K/W Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS 14 DC CHARACTERISTICS VDDD = VDDA = 3.3 V; Tamb = 25 °C; RL = 5 kΩ. All voltages referenced to ground (pins 5 and 15) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT Supply VDDA DAC analog supply voltage note 1 2.7 3.3 3.6 V VDDD digital supply voltage note 1 2.7 3.3 3.6 V IDDA analog supply current operation mode − 6.5 − mA IDDD digital supply current operation mode − 3.0 − mA Digital input pins VIH HIGH-level input voltage 0.8VDDD − − V VIL LOW-level input voltage − − 0.2VDDD V ILI input leakage current − − 1 µA pF Ci input capacitance − − 10 VIH HIGH-level input voltage − − VDDD + 0.5 V VIL LOW-level input voltage −0.5 − − V DAC Vref reference voltage with respect to VSSA 0.45VDDA 0.5VDDA 0.55VDDA V Io(max) maximum output current (THD + N)/S < 0.1% RL = 5 kΩ − 0.22 − mA Rout output resistance − 0.15 2.0 Ω RL load resistance 3 − − kΩ CL load capacitance − − 50 pF note 2 Notes 1. All supply connections must be made to the same external power supply unit. 2. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent oscillations in the output operational amplifier. 2000 Jan 10 12 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS 15 AC CHARACTERISTICS 15.1 Analog VDDD = VDDA = 3.3 V; fi = 1 kHz; Tamb = 25 °C; RL = 5 kΩ. All voltages referenced to ground (pins 5 and 15) unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT DAC Vo(rms) output voltage (RMS value) ∆Vo unbalance between channels (THD + N)/S total harmonic distortion plus noise-to-signal ratio at 0 dB at −60 dB; A-weighted S/N signal-to-noise ratio code = 0; A-weighted αcs channel separation PSRR power supply ripple rejection ratio 2000 Jan 10 fripple = 1 kHz; Vripple(p-p) = 100 mV 13 − 1.0 − V − 0.1 − dB − −90 −85 dB − −38 -35 dB − 100 95 dB − 100 − dB − 50 − dB Philips Semiconductors Preliminary specification Low-cost stereo filter DAC 15.2 UDA1320ATS Digital VDDD = VDDA = 2.7 to 3.6 V; Tamb = −20 to +85 °C; RL = 5 kΩ. All voltages referenced to ground (pins 5 and 15); unless otherwise specified. SYMBOL Tsys PARAMETER system clock cycle tCWL LOW-level system clock pulse width tCWH HIGH-level system clock pulse width CONDITIONS MIN. TYP. MAX. UNIT fsys = 256fs 78 88 244 ns fsys = 384fs 52 59 162 ns fsys = 512fs 39 44 122 ns fsys < 19.2 MHz 30 − 70 %Tsys fsys ≥ 19.2 MHz 40 − 60 %Tsys fsys < 19.2 MHz 30 − 70 %Tsys fsys ≥ 19.2 MHz 40 − 60 %Tsys Serial input data timing (see Fig.7) Tcy(CLK)(bit) bit clock period 300 − − ns tCLKH(bit) bit clock HIGH time 100 − − ns tCLKL(bit) bit clock LOW time 100 − − ns tr rise time − − 20 ns tf fall time − − 20 ns tsu(i)(D) data input set-up time 20 − − ns th(i)(D) data input hold time 0 − − ns tsu(WS) word selection set-up time 20 − − ns th(WS) word selection hold time 10 − − ns Microcontroller interface timing (see Figs 4 and 6) Tcy(CLK)(L3) L3CLK 500 − − ns tCLK(L3)H L3CLK HIGH period 250 − − ns tCLK(L3)L L3CLK LOW period 250 − − ns tsu(L3)A L3MODE set-up time addressing mode 190 − − ns th(L3)A L3MODE hold time addressing mode 190 − − ns tsu(L3)D L3MODE set-up time data transfer mode 190 − − ns th(L3)D L3MODE hold time data transfer mode 190 − − ns tsu(L3)DA L3DATA set-up time data transfer and addressing mode 190 − − ns th(L3)DA L3DATA hold time data transfer and addressing mode 30 − − ns tstp(L3) L3MODE halt time 190 − − ns 2000 Jan 10 14 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS handbook, full pagewidth WS th(WS) tCLKH(bit) tr tsu(WS) tf BCLK tCLKH(bit) tsu(i)(D) Tcy(CLK)(bit) th(i)(D) DATAI MBK075 Fig.7 Serial interface timing. 16 APPLICATION INFORMATION analog supply voltage handbook, full pagewidth digital supply voltage R2 1Ω C1 R3 1Ω 100 µF (16 V) system clock R1 SYSCLK 47 Ω C5 C6 100 nF (63 V) VSSA 100 nF (63 V) VSSD 15 VDDA 13 5 VDDD 4 6 14 BCK WS DATAI APPSEL VO(L) 47 µF (16 V) 1 2 7 VO(R) APPL2 APPL3 100 Ω left output R5 10 kΩ C3 47 µF (16 V) 16 APPL0 R4 3 UDA1320A APPL1 C2 R6 100 Ω right output R7 10 kΩ 11 10 9 12 8 VREF(DAC) C7 100 nF (63 V) C4 47 µF (16 V) MGM818 Fig.8 Application schematic. 2000 Jan 10 15 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS 17 PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm D SOT369-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 1 8 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 1.5 0.15 0.00 1.4 1.2 0.25 0.32 0.20 0.25 0.13 5.30 5.10 4.5 4.3 0.65 6.6 6.2 1.0 0.75 0.45 0.65 0.45 0.2 0.13 0.1 0.48 0.18 10 0o Note 1. Plastic or metal protrusions of 0.20 mm maximum per side are not included. OUTLINE VERSION SOT369-1 2000 Jan 10 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 95-02-04 99-12-27 MO-152 16 o Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 18 SOLDERING 18.1 Introduction to soldering surface mount packages • For packages with leads on two sides and a pitch (e): This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. There is no soldering method that is ideal for all surface mount IC packages. Wave soldering is not always suitable for surface mount ICs, or for printed-circuit boards with high population densities. In these situations reflow soldering is often used. 18.2 The footprint must incorporate solder thieves at the downstream end. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical dwell time is 4 seconds at 250 °C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Typical reflow peak temperatures range from 215 to 250 °C. The top-surface temperature of the packages should preferable be kept below 230 °C. 18.3 18.4 Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: 2000 Jan 10 Manual soldering 17 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC 18.5 UDA1320ATS Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE REFLOW(1) WAVE BGA, LFBGA, SQFP, TFBGA not suitable suitable(2) HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not PLCC(3), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO suitable suitable suitable not recommended(3)(4) suitable not recommended(5) suitable Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 19 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 20 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 2000 Jan 10 18 Philips Semiconductors Preliminary specification Low-cost stereo filter DAC UDA1320ATS NOTES 2000 Jan 10 19 Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 545002/25/02/pp20 Date of release: 2000 Jan 10 Document order number: 9397 750 06675