NEC UPC1851B

DATA SHEET
BIPOLAR ANALOG INTEGRATED CIRCUIT
µPC1851B
I2C BUS-COMPATIBLE US MTS PROCESSING LSI
The µPC1851B is an integrated circuit for US MTS (Multiplexed Television Sound) system with the addition of
the I2C bus interface. All functions required for US MTS system are incorporated on a single chip.
The µPC1851B allows users to switch modes, control volume and tone, and adjust the separation circuit
through the I2C bus.
FEATURES
• Stereo demodulation, SAP (Sub Audio Program) demodulation, dbx noise reduction decoding, I2C bus interface,
input selector (2 channels), surround processor (1 phase), volume and tone control circuits incorporated on a single
chip
• Mode switching, volume and tone control, and separation adjustment through the I2C bus
• Power supply: 8 V to 10 V
• On-chip input attenuator for simple interface with intermediate frequency processing IC (I2C bus control)
• Output level: 1.4 Vp-p (with L+R signals, 100 % modulation)
APPLICATION
• TV sets and VCRs for north America
ORDERING INFORMATION
Part Number
Package
µPC1851BCU
42-pin plastic SDIP (15.24 mm (600))
The µPC1851B is available only to licensees of THAT Corporation.
For information, please call: (508) 229-2500 (U.S.A), or (03) 5790-5391 (Tokyo).
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. S13417EJ2V0DS00 (2nd edition)
Date Published June 2000 N CP(K)
Printed in Japan
The mark
shows major revised points.
©
1998
µPC1851B
SYSTEM BLOCK DIAGRAM
● TV
IF processing
Tuner
C, Y, and
deflecting
signal output
DTS
interface
Chroma output
Vertical output
µ PC1851B
SCL
L
Tuning
microcontroller
MTS processing
Power amplifier
SDA
R
L
Remote
controller
receive amp.
R
L
R
Graphic equalizer
(Surround processor)
PIN photodiode
2
Data Sheet S13417EJ2V0DS00
CRT
µPC1851B
BLOCK DIAGRAM
VCC
+
10 µ F
+
10 µ F
LOT
9V
ROT
26
25
1
21
AGND
D/A
Volume Control
2.2 µ F
TLO
28
Tone Control
LTC 32
+
0.1µ F
LBC
29
33
30
Surround Block
27
Selector Block
19
TRO
2200 pF
RTC
0.1µ F
+
+
2200 pF
31
+
2.2 µ F
RBC
0.022 µ F
SUR
FOR 40
EL2
37
EL1
39
ER2 36
+
FOL 41
4.7µ F
VOL-C
ER1 38
MOL 35
MOR 34
Matrix Block
10 µ F
16 WTI**
5.1 kΩ
42
17
WRB 3.3 µ F
+
dbx Noise
Reduction Block
1µF
+
MOA
Offset
Absorption
13 STI**
Deemphasis
3 kΩ
14
1µ F
SRB 1 µ F
18 dO
+
+
1µ F
1µ F
20 VOA
+
D/A
+
Filter
Control
+
Filter
16.6 kΩ
15
+
22 µ F
VRE 2
1/2VCC
L+R
LPF
Switch
ITI*
11 SI
0.1 µ F
4.7µ F
1µ F
+
+
1 kΩ
PD1
4
3
φ D1
5
φ D2
6
10 SOT
Stereo
Demodulation
Block
SAP
Demodulation
Block
SDA 22
SCL 23
I2C Bus
Interface
68 kΩ
Input Attenuator
I2C Bus
Interface
Noise
BPF
D/A
Noise
Detector
9
+
PD2
0.1µ F
NDT
0.47µ F
DGND 24
SOA
2.2µ F
12
SDT
8
+
7
+
COM
0.1µ F
0.047µ F
Remark Use the followings for external parts.
Resistor (*): Metal film resistor (± 1 %). Unless otherwise specified; ±5 %
Capacitors (**): Tantalum capacitor (±10 %). Unless otherwise specified; ±20 %
Data Sheet S13417EJ2V0DS00
3
µPC1851B
STEREO DEMODULATION BLOCK
φ D1
φ D2
5
6
PD1 PD2
3
4
Divider
D/A
Stereo Phase
Comparator
1
4
Stereo
VCO
1
2
Pilot Discrimination
Phase Comparator
2
To I C bus Interface
From Input Attenuator
Stereo LPF
Pilot Canceler
L–R AM
Demodulator
To Switch
To L+R LPF
SAP DEMODULATION BLOCK
From Input Attenuator
SAP BPF
To Noise BPF
SOA 12
Offset Absorption
Phase Detector
Loop Filter
SAP VCO
D/A
SDT 8
SAP Detector
2
To I C bus Interface
SAP LPF
10
SOT
4
Data Sheet S13417EJ2V0DS00
µPC1851B
dbx NOISE REDUCTION BLOCK
From Switch
LPF
fH Trap
408-Hz LPF
2 fH Trap
Wide-band RMS
Filter
Spectral RMS Filter
Variable
Emphasis
D/A
Spectral
RMS
D/A
Timing Current
2.19-kHz LPF
Wide-band
RMS
Offset
Absorption
18
dO
Wide-band VCA
13
15
SRB STI
14
ITI
17
16
Offset
Absorption
To Matrix Block
20
WRB WTI
VOA
SELECTOR BLOCK
ER1 ER2
EL1 EL2
38 36
39 37
From Matrix Block
(L-channel signal)
From Matrix Block
(R-channel signal)
Note2
40 kΩ 40 kΩ
To Surround Block
Switch Note1
40 kΩ
–
Switch (Monaural/Stereo)
+
Note2
40 kΩ
To Surround Block
Notes 1. Switch (TV signal/External input 1/External input 2).
2. The input gain 0 dB/6 dB can be selected by the command of the I2C bus (refer to 4.3 (5) Input gain).
Data Sheet S13417EJ2V0DS00
5
µPC1851B
SURROUND BLOCK
To Tone Control Block
From Selector Block
(L-channel)
–
–
Phase Shifter
+
From Selector Block
(R-channel)
To Tone Control Block
27
SUR
6
Data Sheet S13417EJ2V0DS00
µPC1851B
PIN CONFIGURATION (Top View)
42-pin plastic SDIP (15.24 mm (600))
• µPC1851BCU
Power Supply (9 V)
1
VCC
MOA
42
Monaural Offset Absorption
Vcc Filter
2
VRE
FOL
41
L-channel Fixed Output
Pilot Discrimination Filter 1
3
PD1
FOR
40
R-channel Fixed Output
Pilot Discrimination Filter 2
4
PD2
EL1
39
External L-channel Input 1
Phase Comparator Filter 1
5
φ D1
ER1
38
External R-channel Input 1
Phase Comparator Filter 2
6
φ D2
EL2
37
External L-channel Input 2
Composite Signal Input
7
COM
ER2
36
External R-channel Input 2
SAP Discrimination Filter
8
SDT
MOL
35
L-channel Matrix Output
Noise Detector Filter
9
NDT
MOR
34
R-channel Matrix Output
SAP Single Output
10
SOT
LBC
33
L-channel Capacity of Low Frequency Band Width
SAP Single Input
11
SI
LTC
32
L-channel Capacity of High Frequency Band Width
SAP Offset Absorption
12
SOA
TLO
31
L-channel Offset Absorption
Spectral RMS Timing
13
STI
RBC
30
R-channel Capacity of Low Frequency Band Width
Spectral RMS Offset Absorption
14
SRB
RTC
29
R-channel Capacity of High Frequency Band Width
Timing Current Setting
15
ITI
TRO
28
R-channel Offset Absorption
Wide-band RMS Timing
16
WTI
SUR
27
Surround Timing
Wide-band RMS Offset Absorption
17
WRB
LOT
26
L-channel Output
Variable Emphasis Offset Absorption
18
dO
ROT
25
R-channel Output
Volume Control Offset Absorption
19
VOL-C
DGND
24
Digital GND (for I C bus)
VCA Offset Absorption
20
VOA
SCL
23
SCL (for I C bus)
Analog GND
21
AGND
SDA
22
SDA (for I C bus)
1
2
Data Sheet S13417EJ2V0DS00
2
2
2
7
µPC1851B
CONTENTS
1.
PIN EQUIVALENT CIRCUITS ............................................................................................ 9
2.
BLOCK FUNCTIONS ........................................................................................................ 18
3.
4.
2.1
Stereo Demodulation Block ................................................................................... 18
2.2
SAP Demodulation Block ...................................................................................... 19
2.3
dbx Noise Reduction Block ................................................................................... 20
2.4
Matrix Block ............................................................................................................ 21
2.5
Selector Block ........................................................................................................ 21
I2C BUS INTERFACE ....................................................................................................... 22
3.1
Data Transfer ......................................................................................................... 23
3.2
Data Transfer Format ............................................................................................ 24
I2C BUS COMMANDS ...................................................................................................... 27
4.1
Subaddress List ..................................................................................................... 27
4.2
Setting Procedure .................................................................................................. 29
4.3
Explanation of Write Register ................................................................................ 31
4.4
Explanation of Read Register ............................................................................... 38
5.
MODE MATRIX ................................................................................................................. 40
6.
SELECTOR TABLE .......................................................................................................... 41
7.
USAGE CAUTIONS .......................................................................................................... 42
7.1
Caution on Shock Noise Reduction ...................................................................... 42
7.2
Supply Voltage ....................................................................................................... 42
7.3
Impedance of Input and Output Pins .................................................................... 42
7.4
Drive Capability of Output Pins ............................................................................. 42
7.5
Caution on External Components ......................................................................... 43
7.6
Change of Electrical Characteristics by External Components ........................... 43
8.
ELECTRICAL SPECIFICATIONS .................................................................................... 44
9.
TEST CIRCUIT .................................................................................................................. 56
10. PACKAGE DRAWINGS ................................................................................................... 58
11. RECOMMENDED SOLDERING CONDITIONS .............................................................. 59
8
Data Sheet S13417EJ2V0DS00
µPC1851B
1. PIN EQUIVALENT CIRCUITS
(1/9)
Pin No.
Pin Name
1
Power Supply (9 V)
2
1
2
VCC Filter
Symbol
Internal Equivalent Circuit
VCC
VCC
VRE
10 kΩ
10 kΩ
5 kΩ
20 kΩ
20 kΩ
20 kΩ
10 kΩ
2
10 kΩ
20 kΩ
5 kΩ
GND
3
Pilot Discrimination Filter 1
VCC
PD1
3
15 kΩ
15 kΩ
5 kΩ
1
VCC
2
4
Pilot Discrimination Filter 2
PD2
VCC
4
Data Sheet S13417EJ2V0DS00
15 kΩ
15 kΩ
5 kΩ
9
µPC1851B
(2/9)
Pin No.
5
Pin Name
Phase Comparator Filter 1
Symbol
Internal Equivalent Circuit
φD1
VCC
5
15 kΩ
5 kΩ
5 kΩ
1
VCC
2
6
Phase Comparator Filter 2
φD2
VCC
15 kΩ
6
7
Composite Signal Input
5 kΩ
5 kΩ
COM
VCC
1
VCC
2
80 kΩ
7
3 kΩ
17 kΩ
5 kΩ
5 kΩ
GND
8
SAP Discrimination Filter
SDT
8
VCC
20 kΩ
10 kΩ
20 kΩ
20 kΩ
10 kΩ
GND
10
Data Sheet S13417EJ2V0DS00
µPC1851B
(3/9)
Pin No.
9
Pin Name
Noise Detector Filter
Symbol
Internal Equivalent Circuit
NDT
9
VCC
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
20 kΩ
GND
10
SAP Single Output
SOT
VCC
2 kΩ
200 Ω
10
2 kΩ
GND
Data Sheet S13417EJ2V0DS00
11
µPC1851B
(4/9)
Pin No.
11
Pin Name
SAP Single Input
Symbol
Internal Equivalent Circuit
1
VCC
2
SI
VCC
10 kΩ
80 kΩ
5 kΩ
10 kΩ
5 pF
11
5 kΩ
GND
12
SAP Offset Absorption
SOA
VCC
10 kΩ
10 kΩ
5 pF
50 kΩ
3 kΩ
2.3 kΩ
10 kΩ
GND
12
13
Spectral RMS Timing
STI
VCC
5 kΩ
600 Ω
5 kΩ
5 kΩ
5 kΩ
13
5 kΩ
GND
12
Data Sheet S13417EJ2V0DS00
µPC1851B
(5/9)
Pin No.
14
Pin Name
Symbol
Spectral RMS Offset Absorption
Internal Equivalent Circuit
SRB
VCC
5 kΩ
5 kΩ
5 kΩ
3 kΩ
3 kΩ
14
3 kΩ
5 kΩ
GND
15
Timing Current Setting
VCC
ITI
10 kΩ
10 kΩ
5 kΩ
20 pF
10
kΩ
10 kΩ
10 kΩ
10 kΩ
15
30 kΩ
GND
16
Wide-band RMS Timing
WTI
Same as pin 13
17
Wide-band RMS Offset Absorption
WRB
Same as pin 14
18
Variable Emphasis Offset
Absorption
dO
VCC
20 kΩ
10 kΩ
10 kΩ
20 kΩ
50 kΩ
18
3 kΩ
6 pF
10 kΩ
GND
Data Sheet S13417EJ2V0DS00
13
µPC1851B
(6/9)
Pin No.
19
Pin Name
Volume Control Offset Absorption
Symbol
Internal Equivalent Circuit
VOL-C
VCC
10 kΩ
10 kΩ
5 kΩ
5 pF
5 kΩ
5 kΩ
5 kΩ
25 kΩ
20 kΩ
10 kΩ
10 kΩ
10 kΩ
GND
19
20
VCA Offset Absorption
21
Analog GND
22
SDA (for I2C bus) Note
VOA
Same as pin 12
AGND
SDA
VCC
10 kΩ
10 kΩ
10 kΩ
50 kΩ 5 kΩ
22
30 kΩ
30 kΩ
GND
23
SCL (for I2C bus) Note
SCL
VCC
10 kΩ
10 kΩ
10 kΩ
5 kΩ
23
30 kΩ
30 kΩ
GND
24
Digital GND (for I2C bus)
DGND
Note A protection diode on the VCC side is deleted not so as to pull the voltage of I2C bus line down to 0 V while
the power supply is off (VCC = 0 V).
14
Data Sheet S13417EJ2V0DS00
µPC1851B
(7/9)
Pin No.
25
Pin Name
R-channel Output
Symbol
Internal Equivalent Circuit
ROT
VCC
1 kΩ
10 kΩ
200 Ω
25
200Ω
5 kΩ
1 kΩ
5 kΩ
GND
26
L-channel Output
LOT
27
Surround Timing
SUR
Same as pin 25
VCC
27
2 kΩ
24 kΩ
20 kΩ
40 kΩ
20 kΩ
GND
28
R-channel Offset Absorption
VCC
TRO
35 kΩ 5 kΩ
35 kΩ 5 kΩ
28
40 kΩ
10 kΩ
10 kΩ
GND
Data Sheet S13417EJ2V0DS00
15
µPC1851B
(8/9)
Pin No.
29
Pin Name
R-channel Capacity of High
Frequency Band Width
Symbol
Internal Equivalent Circuit
VCC
RTC
36 kΩ 5 kΩ
36 kΩ 5 kΩ
40 kΩ
29
10 kΩ
10 kΩ
GND
30
R-channel Capacity of Low
Frequency Band Width
RBC
VCC
5 kΩ
1 kΩ
30
5 kΩ
5.3 kΩ
3 kΩ
2.5 kΩ
GND
16
31
L-channel Offset Absorption
TLO
Same as 28
32
L-channel Capacity of High
Frequency Band Width
LTC
Same as 29
33
L-channel Capacity of Low
Frequency Band Width
LBC
Same as 30
34
R-channel Matrix Output
MOR
Same as 25
35
L-channel Matrix Output
MOL
Data Sheet S13417EJ2V0DS00
µPC1851B
(9/9)
Pin No.
36
Pin Name
External R-channel Input 2
Symbol
Internal Equivalent Circuit
ER2
10 kΩ
37
External L-channel Input 2
10 kΩ
EL2
15 pF
40 kΩ
38
External R-channel Input 1
ER1
36
40 kΩ
10 kΩ
39
External L-channel Input 1
EL1
I2C Bus
40
R-channel Fixed Output
FOR
41
L-channel Fixed Output
FOL
42
Monaural Offset Absorption
MOA
Same as pin 25
Same as pin 18
Data Sheet S13417EJ2V0DS00
17
µPC1851B
2. BLOCK FUNCTIONS
2.1 Stereo Demodulation Block
(1) Stereo LPF
This filter eliminates signals in the vicinity of 5 fH to 6 fH, such as SAP (Sub Audio Program) (5 fH) and telemetry
signals (6.5 fH) . The µPC1851B’s internal L–R demodulator, which uses a double-balanced circuit, demodulates
L–R signals by multiplication of the L–R signal with the signal at the L–R carrier frequency (2 fH). The L–R signal
tends to receive interference from the 6 fH signal because a square waveform is used as the switching carrier in this
method. To eliminate this interference, the µPC1851B incorporates traps at 5 fH and 6 fH. The filter response is
adjusted by setting the FILTER SETTING bits (Write register, subaddress 02H, bits D0 to D5).
(2) Stereo Phase Comparator
The 8 fH signal generated at the Stereo VCO is divided by 8 (4 × 2) and then multiplied by the pilot signal passed
through the stereo LPF. The two signals differ from each other by 90 degrees in terms of phase.
The resistor and capacitor connected to the φD1 and φD2 pins form a filter that smoothes the phase error signal
output from the Stereo Phase Comparator, converting the error signal to the DC voltage. When the voltage difference
between φD1 and φD2 pins becomes 0 V (strictly speaking, not 0 V by the internal offset voltage), the VCO runs at
8 fH .
The lag/lead filter externally connected to the pins φD1 and φD2 determines the capture range.
(3) Stereo VCO
The Stereo VCO runs at 8 fH with the internal capacitor. The frequency is adjusted by setting the STEREO VCO
SETTING bits (Write register, subaddress 01H, bits D0 to D5).
(4) Divider (Flip-flop)
Produces two separate fH signals: the inphase fH signal, and the fH signal differing by 90 degrees from the input
pilot signal by dividing the 8 fH frequency from the Stereo VCO by 8 (4 × 2).
(5) Pilot Discrimination Phase Comparator (Level detector)
Multiplies the pilot signal from the COM pin with the inphase fH signal from the divider. The resulting signal is
smoothed by passing it through the external filter connected to the PD1 and PD2 pins and converted into DC
voltage that is used to determine whether or not a stereo pilot is present (Read register, bit D6).
(6) Pilot Canceler
The fH signal from the divider is added to the stereo signal matrix depending on the level of the input pilot signal
to cancel the pilot signal.
(7) L+R LPF
This LPF which has traps at fH and 24 kHz, allows only the monaural signal to pass through. The filter response
is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
(8) De-emphasis
The 75-µs de-emphasis filter is for the monaural signal. The response is adjusted by setting the FILTER SETTING
bit (Write register, subaddress 02H, bits D0 to D5).
(9) L–R AM Demodulator
Demodulates the L–R AM-DSB modulated signal by multiplying with the 2-fH signal which is synchronized to the
pilot signal. The 2-fH square wave is used as the switching carrier.
18
Data Sheet S13417EJ2V0DS00
µPC1851B
2.2 SAP Demodulation Block
(1) SAP BPF
Picks up the SAP signal by the 50-kHz and 102-kHz traps and a response peak at 5 fH. The filter response is
adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
(2) Noise BPF
. 180 kHz), and distinguishes noise from
The µPC1851B monitors signals picked up by the noise BPF (fO =
.
signals. By this method, the µPC1851B prevents faulty SAP detection in a weak electric field. The filter response is
adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
(3) Noise Detector
Performs full-wave rectification of noise from noise BPF, changes it to the DC voltage, and inputs it to the
comparator. When the noise level exceeds the reference level, the Noise detection bit (Read register, bit D4) turns
“1”.
The sensitivity and time constant of the circuit are adjusted by setting the values of the resistor and capacitor
connected to the NDT pin.
(4) SAP Detector
Detects the signal from the SAP BPF and smoothes it through the SDT pin and inputs it to the comparator. When
it detects the SAP signal, the SAP broadcast (Broadcast status) (Read register, bit D5) turns “1”.
(5) SAP Demodulator
The SAP demodulator consists of a phase detector, a loop filter and an SAP VCO (PLL detection circuit).
The SAP VCO oscillates at 10 fH, and performs phase comparison between the signal divided by 2 of the SAP
VCO frequency and the SAP signal to make the PLL. The SAP VCO oscillating frequency is adjusted by setting the
SAP VCO SETTING bit (Write register, subaddress 05H, bits D0 to D5).
(6) SAP LPF
Eliminates the SAP carrier and high-frequency buzz. The filter consists of a 2nd-order LPF and fH trap filter. The
filter response is adjusted by setting the FILTER SETTING bit (Write register, subaddress 02H, bits D0 to D5).
Data Sheet S13417EJ2V0DS00
19
µPC1851B
2.3 dbx Noise Reduction Block
All the filters required for TV-dbx Noise Reduction are incorporated. These filter responses are adjusted by
setting all the FILTER SETTING bits (Write register, subaddress 02H, bits D0 to D5).
(1) LPF
This LPF has traps at fH and 24 kHz each. The fH trap filter minimizes interference by the fH signal which is not
synchronized with the pilot signal (for example, leakage of the synchronous idle and buzz from the video signal).
(2) 408-Hz LPF
This filter is a de-emphasis filter. Its transfer function is as follows:
1+j
T(f) =
1+j
f
5.23k
f
408
(3) Variable Emphasis
It is also called the spectral VCA. It is controlled by the spectral RMS. The transfer function is as follows:
1+j
S
–1
(f, b) =
1+j
f
20.1k
f
20.1k
x
x
1 + 51b
b+1
1 + 51
b+1
where “b” is the variable transferred from the spectral RMS for controlling.
(4) Wide-band VCA
A VCA whose operating frequency range is mainly low to mid frequencies and controlled by the wide-band RMS.
The transfer function is as follows:
W –1 (a) = a
where “a” is the variable transferred from the wide-band RMS for controlling.
(5) 2.19-kHz LPF
This filter is a de-emphasis filter. Its transfer function is as follows:
1+j
T(f) =
1+j
f
62.5k
f
2.19k
(6) Spectral RMS Filter
A filter that limits the band width of the signal input to the RMS which controls the variable emphasis. The
transfer function is as follows:
f
f
)2
j
7.66k
3.92k
x
f
f
f
1+j
+ (j
)2
1+j
7.31k
7.66k
3.92k
(j
T (f) =
20
Data Sheet S13417EJ2V0DS00
µPC1851B
(7) Wide-band RMS Filter
A filter that limits the band width of the signal input to the wide-band RMS which controls the wide-band VCA.
The transfer function is as follows:
1
T(f) =
1+j
f
2.09k
(8) Spectral RMS
Detects the RMS value of the signal passed through the spectral RMS filter, and converts the signal to the DC
voltage. The release time is set by adjusting the current IT of the µPC1851B and the capacitance of the external
capacitor connected to the STI pin. The current IT is adjusted by adjusting the current from the ITI pin.
(9) Wide-band RMS
Detects the RMS value of the signal passed through the wide-band RMS filter, and converts the signal to the DC
voltage. The release time is set by adjusting the current IT of the µPC1851B and the capacitance of the external
capacitor connected to the WTI pin. The current IT is adjusted by adjusting the current from the ITI pin.
2.4 Matrix Block
(1) Matrix
Adds L+R signal and L–R signal to output L signal, and substracts L+R signal from L–R signal to output R signal.
(2) Mode Selector
The matrix block selects the signal from the monaural signal, Stereo signal, SAP signal by the User Mode.
2.5 Selector Block
It selects the signal from the TV signal (signal with the audio multiple signal processed in the µPC1851B) and
external input (signal input from EL1, EL2, ER1 and ER2 pins), and outputs it to the surround processor block
(surround, tone control, and volume control block).
It also selects the gain of the selection signal (0 dB/6 dB) as well as switches the stereo/monaural output (by the
I2C bus).
Data Sheet S13417EJ2V0DS00
21
µPC1851B
3. I2C BUS INTERFACE
The µPC1851B uses a 2-wire serial bus developed by Philips. The serial clock line (SCL) and serial data line
(SDA) employ the 2-wire configuration as shown in Figure 3-1.
The µPC1851B contains an I2C bus interface circuit, eleven (8-bit) read/write registers, and one read-only register.
Serial Clock Line (SCL)
The master CPU outputs a serial clock to achieve data synchronicity. The µPC1851B receives serial data based
on this clock. The input level is CMOS-compatible. The clock frequency is from 0 to 100 kHz.
Serial Data Line (SDA)
The master CPU outputs data synchronously with the serial clock. The µPC1851B receives this data based on
the serial clock. The input level is CMOS-compatible
Figure 3-1. Internal Equivalent Circuit of Interface Pins
RP
RP
SCL
SDA
µ PC1851B
For SCL and SDA pins, a protection diode on the VCC side is deleted not so as to pull the voltage of I2C bus line
down to 0 V while the power supply is off (VCC = 0 V).
22
Data Sheet S13417EJ2V0DS00
µPC1851B
3.1 Data Transfer
(1) Start condition
The start condition is created when SDA changes from high to low while SCL is high, as shown in Figure 3-2.
When the µPC1851B receives this information, it captures data sent in synchronization with the clock.
(2) Stop condition
The stop condition is created when SDA changes from low to high while SCL is high, as shown in Figure 3-2.
When the µPC1851B receives this information, it stops receiving or outputting data.
Figure 3-2. Data Transfer Start/Stop Condition
3.5 V
SDA
1.5 V
4.7 µ s
MIN.
4.0 µ s
MIN.
3.5 V
SCL
1.5 V
Stop
Start
(3) Data transfer
When transferring data, be sure to switch data only when SCL is low, as shown in Figure 3-3. When SCL is high,
the data must not be changed.
Figure 3-3. Data Transfer
SDA
Note 1
Note 2
SCL
Note 3
Notes
Note 4
1. Data hold time: 300 ns MIN.
2. Data setup time: 250 ns MIN.
3. Interval when data must not be changed.
4. Interval when data can be changed.
Data Sheet S13417EJ2V0DS00
23
µPC1851B
3.2 Data Transfer Format
An example of data transfer in the write mode is shown in Figure 3-4.
Figure 3-4. Data Transfer Example in Write Mode
SDA
D6 D5 D4 D3 D2 D1 D0
1
SCL
Start
2
3
4
5
6
Slave address
7
Write
mode
8
D7 D6 D5 D4 D3 D2 D1 D0
9
1
Read/ Acknowwrite ledge
2
3
4
5
6
7
8
Subaddress
D7 D6 D5 D4 D3 D2 D1 D0
9
1
2
Acknowledge
3
4
5
Data
6
7
8
9
Acknow- Stop
ledge
Data consists of 8-bit units. This 8-bit data must always be followed by an acknowledge bit. Data transfer must
be done on an MSB-first basis.
The first byte after a start condition specifies the slave address. The slave address consists of 7 bits.
Table 3-1 shows the slave addresses of the µPC1851B. These slave addresses are registered by Philips.
Table 3-1. Slave Addresses of µPC1851B
Slave address
D6
D5
D4
D3
D2
D1
D0
Read/Write
Write
1
0
1
1
0
0
0
0
Read
1
0
1
1
0
0
0
1
Mode
The bit following the slave address is the read/write bit specifying the direction of the data to be transferred.
During the read operation, data is transferred from the µPC1851B to the master CPU. During the write operation,
data is transferred from the master CPU to the µPC1851B. “0” and “1” are written to the READ/WRITE bit during the
Write and Read modes, respectively.
The byte following the slave address is the subaddress of the µPC1851B in the write mode.
The µPC1851B has eleven subaddresses, SA0 to SAA, which are made up of 8 bits. Following the subaddress
byte is the data to be set to the subaddress.
24
Data Sheet S13417EJ2V0DS00
µPC1851B
(1) 1-byte data transfer
The format for 1-byte data transfer is the following:
Start
Write Acknow
Acknow
Subaddress
mode -ledge
-ledge
Slave
address
Data
Acknow Stop
-ledge
(2) Continuous data transfer
The format when transferring multiple (7) bytes of data at one time by using the automatic increment function is
the following:
Start
Slave
address
Write Acknow
Acknow
Subaddress
mode -ledge
-ledge
Data1
Acknow
-ledge
Data2
Acknow
-ledge
Data7
Acknow
Stop
-ledge
The master CPU transfers “00H” as subaddress SA0 following the start condition and slave address. After the
subaddress SA0, the master CPU transfers the SA0 data, and continues with SA1, SA2,..., SAA data without transferring
stop conditions in between. Finally, the stop condition is transferred and the transfer is completed.
(3) Data read
The µPC1851B has one read register. The contents of this register can be read by the master CPU.
The format when data is read is the following:
Start
Slave
address
Read
Acknow
-ledge
Data
Nonacknow Stop
-ledge
(4) Acknowledge
In the case of the I2C bus, an acknowledge bit is added to the data as the 9th bit to determine whether data
transfer was successful. The master CPU determines the success or failure of data transfer based on whether this
acknowledge bit is a logical low or high.
If the acknowledge interval is a logical low, this indicates that data transfer was successful. If it is a logical high,
this indicates that data transfer was unsuccessful or that the slave side forcibly released the bus.
Data Sheet S13417EJ2V0DS00
25
µPC1851B
(5) Automatic increment
The µPC1851B has the automatic increment function.
The automatic increment is applied to the subaddresses 00H to 05H of the write register.
The user can set ON/OFF the automatic increment of the subaddresses 06H to 0AH (refer to 4.1 Subaddress
List).
Automatic increment ON:
The subaddress is automatically increased. Setting the slave address and
subaddress once enables the data of the next subaddress to be transferred
without actually setting it.
Automatic increment OFF:
The subaddress is fixed. The data of the fixed subaddress can be set time after
time.
The increment of the subaddresses 06H to 0AH is individually controlled by each automatic increment ON/OFF
bit.
For example, if the automatic increment function of the subaddress 06H is set to ON and that of the subaddress
07H set to OFF, the subaddress is to be automatically increased from 06H to 07H and then fixed to 07H.
Though the automatic increment function of the subaddress 0AH is set to ON, the subaddress is not to be
increased. After setting the data of 0AH (acknowledge bit: low level), if the next data is transferred, the acknowledge
is to be in non-acknowledge state (acknowledge bit: high level) and the data transfer from the master CPU is
aborted.
26
Data Sheet S13417EJ2V0DS00
µPC1851B
4. I2C BUS COMMANDS
4.1 Subaddress List
(1) Write register (command list)
Subaddress
Bit MSB
D7
LSB
D6
D5
D4
D3
D2
00H
0
During noise
detection
Stereo/SAP
output stop
0: SAP OFF
1: Stereo,
SAP OFF
01H
0
fH monitor
ON/OFF
0: OFF 1: ON
Stereo VCO setting
02H
0
Pilot canceler
ON/OFF
Filter setting
D1
D0
Input level setting
0: ON 1: OFF
03H
0
Input gain
0: 0 dB 1: 6 dB
Low-band separation setting
04H
0
Surround
0: OFF 1: ON
High-band separation setting
05H
0
5fH monitor
ON/OFF
0: OFF 1: ON
SAP VCO setting
06H
07H
Automatic
increment
0: OFF
1: ON
0
Input select 1
00: TV signal
01: External input 1
10: External input 2
11: Setting prohibited
Automatic
increment
Input select 2 SAP1/SAP2 Stereo/SAP
0: Stereo
switchNote
switch
1: Monaural 0: SAP1
0: Stereo
1: SAP2
1: SAP
Forced
monaural
0: OFF
1: ON
Mute
0: ON
1: OFF
Volume control
0: OFF 1: ON
08H
0
Automatic
increment
0: OFF 1: ON
Balance control
09H
0
Automatic
increment
0: OFF 1: ON
Bass control
0AH
0
Automatic
increment
0: OFF 1: ON
Treble control
Data Sheet S13417EJ2V0DS00
27
µPC1851B
Note Output when SAP1 or SAP2 is selectd is as follows:
L-channel output (LOT pin)
SAP1
R-channel output (ROT pin)
SAP
SAP2
Monaural (L+R)
SAP
(2) Read register
MSB
D7
LSB
D6
D5
D4
D3
Broadcast status
Power-on reset
1: Detect
28
Stereo pilot
0: Not available
1: Available
SAP signal
0: Not available
1: Available
D2
D1
D0
1
1
Reception status
Noise detection
0: Not available
1: Available
Stereo broadcast
reception
0: Not available
1: Available
Data Sheet S13417EJ2V0DS00
SAP broadcast
reception
0: Not available
1: Available
µPC1851B
4.2 Setting Procedure
Precise adjustment of the dbx decoder is absolutely critical for optimum performance. Where possible, the adjustment
should be performed after the µPC1851B is mounted on the chassis and with the video system active.
Set the data of write register as follows before the adjustment.
Table 4-1. Default Setting of Write Register
Bit
D7
D6
D5
D4
D3
D2
D1
D0
00H
0
0
1
0
0
0
0
0
01H
0
0
1
0
0
0
0
0
02H
0
0
1
1
1
1
1
1
03H
0
0
1
0
0
0
0
0
04H
0
0
1
0
0
0
0
0
05H
0
0
1
0
0
0
0
0
06H
0
0
0
0
0
0
0
1
07H
0
1
1
1
1
1
1
1
08H
0
1
1
0
0
0
0
0
09H
0
1
1
0
0
0
0
0
0AH
0
1
1
0
0
0
0
0
Subaddress
(1) Input level setting (Write register, subaddress 00H, bits D5 to D0)
<1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<2> Input sine wave of 300 Hz, 150 mVrms to COM pin.
<3> Set bits D5 to D0 (INPUT LEVEL SETTING bits) of subaddress 00H so that the output level of FOR pin is
500 mVrms (±10 mVrms).
(2) Stereo VCO setting (Write register, subaddress 01H, bits D6 to D0)
Perform this adjustment with no signal applied.
<1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<2> Write “1” to bit D6 (fH monitor: ON) of subaddress 01H.
<3> Connect frequency counter to FOR pin, and set bits D5 to D0 (STEREO VCO SETTING bits) of subaddress
01H so that frequency counter displays 15.73 kHz (±0.1 kHz).
<4> When setting is completed, write “0” to bit D6 (fH monitor: OFF) of subaddress 01H.
Data Sheet S13417EJ2V0DS00
29
µPC1851B
(3) Filter setting (Write register, subaddress 02H, bits D6 to D0)
<1> Write “1” to bit D6 (Pilot canceler: OFF) of subaddress 02H.
<2> Input pilot signal (15.734 kHz, 30 mVrms or higher Note) to COM pin and set data of bits D5 to D0 (FILTER
SETTING bits) of subaddress 02H so that the AC output level of the FOR pin becomes as small as possible
(Decrease the set data from 63 (decimal)).
<3> When setting is completed, write “0” to bit D6 (pilot canceler: ON) of subaddress 02H.
Note Recommended 100 mVrms.
(4) Separation setting (Write register, subaddresses 03H and 04H, bits D5 to D0)
<1> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<2> Write “20H” to bits D5 to D0 (HIGH-BAND SEPARATION SETTING bits) of subaddress 04H.
<3> Input composite signal to COM pin (300 Hz, 30 % modulation, L-only, with noise reduction), and set bits D5
to D0 (LOW-BAND SEPARATION SETTING bits) of subaddress 03H so that the output level of the FOR
pin is as small as possible.
<4> Change the modulation frequency of the composite signal to 3 kHz, and set bits D5 to D0 of subaddress
04H so that the output level of the FOR pin is as small as possible.
<5> While bits D5 to D0 of subaddress 04H are set as in step <4> above, repeat the setting procedure of step
<3> for bits D5 to D0 of subaddress 03H.
(5) SAP VCO setting (Write register, subaddress 05H, bits D6 to D0)
Perform this adjustment with no signal applied.
<1> Add a 1 MΩ resistor between the SOA pin and GND.
<2> Write “1” to bit D0 (Mute: OFF) of subaddress 06H.
<3> Write “1” to bit D6 (5 fH monitor: ON) of subaddress 05H.
<4> Connect a frequency counter to the FOR pin, and set bits D5 to D0 of subaddress 05H (SAP VCO SETTING
bits) so that 78.67 kHz (±0.5 kHz) is displayed on the frequency counter.
<5> When setting is completed, write “0” to bit D6 (5 fH monitor: OFF) of subaddress 05H.
<6> Delete the 1 MΩ resistor between the SOA pin and GND.
30
Data Sheet S13417EJ2V0DS00
µPC1851B
4.3 Explanation of Write Register
(1) Stereo/SAP output stop function during noise detection
Stereo/SAP output stop can be selected with the data of bit D6 of subaddress 00H during weak electrical field
conditions (recommended noise level during circuit use is 34 mVrms (TYP.) or more).
SAP output stop
: Only SAP output is stopped.
SAP and stereo output stop
: SAP and stereo outputs are stopped, switch to monaural output.
Noise level detection is performed, when detected a noise about at 11.5 fH (180 kHz), a frequency that is sufficiently
apart from that of the high frequency signals such as the stereo, SAP, and telemetry signal. If noise is detected, “1”
is set to bit D4 of the read register (Refer to section 4.4, (4) Noise detection)
Figure 4-1. Stereo/SAP Output Stop Function During Noise Detection
D7
D6
0
During noise
detection
00H
D5
D4
D3
D2
D1
D0
Input level setting
Stereo/SAP output stop function during noise detection
0
SAP output stop
1
SAP and stereo output stop
(2) Mute
The mute function can be set ON/OFF with the data of bit D0 of subaddress 06H.
The mute on state is entered when bit D0 is set to 0 after power-on reset.
Figure 4-2. Mute
D7
06H
Automatic
increment
D6
D5
Input select 1
D4
D3
D2
D1
D0
Input select 2
SAP1/SAP2
switch
Stereo/SAP
switch
Forced monaural
ON/OFF
Mute
ON/OFF
Mute
0 Mute ON
1 Mute OFF
Caution
When switching the power ON/OFF, use the external mute (200 ms) in order to minimize shock
noise.
Data Sheet S13417EJ2V0DS00
31
µPC1851B
(3) Mode switch (L-, R-channel output (LOT, ROT pins))
The output signal for the L- and R-channel outputs (LOT, ROT pins) can be selected with bits D3 to D1 of
subaddress 06H. For the combinations of data of each output signal bit, refer to 5. MODE MATRIX.
Forced monaural ON/OFF : When set to ON, a monaural signal is forcibly output regardless of the selection
of other bits.
Stereo/SAP switch
: When forced monaural is set to OFF, performs selection of stereo or SAP.
SAP1/SAP2 switch
: When SAP output is selected with the stereo/SAP switch, performs selection
of SAP1 or SAP2.
L-Channel Output (LOT pin)
SAP1
R-Channel Output (ROT pin)
SAP output
SAP2
Monaural (L+R) output
SAP output
Figure 4-3. Mode Switch (L-, R-Channel Output (LOT, ROT pins))
D7
06H
Automatic
increment
D6
D5
Input select 1
D4
D3
D2
Input select 2
SAP1/SAP2
switch
Stereo/SAP
switch
D1
D0
Forced monaural Mute ON/OFF
ON/OFF
Forced monaural
0 Forced monaural OFF
1 Forced monaural ON
Stereo/SAP switch
0
Stereo output
1
SAP output
SAP1/SAP2 switch
32
Data Sheet S13417EJ2V0DS00
0
SAP1 output
1
SAP2 output
µPC1851B
(4) Input select
The signal to be input to the selector block in the µPC1851B can be selected by the data of bits D4 to D6 of
subaddress 06H. The selected signal is output from the LOT, ROT, FOL and FOR pins.
For the combination of bits for the signal to be selected, refer to 6. SELECTOR TABLE.
Input select 1 :
switches the TV signal (signal with the audio multiple signal processed in the µPC1851B)
and external inputs 1 and 2 (signal input from EL1, EL2, ER1 and ER2 pins).
Input select 2 :
switches the stereo signal and monaural signal.
Figure 4-4. Input Select
D7
06H
Automatic
increment
D6
D5
Input select 1
D4
D3
D2
Input select 2
SAP1/SAP2
switch
Stereo/SAP
switch
D1
Forced monaural
ON/OFF
D0
Mute
Input select 2
0
L-channel output
(LOT, FOL pins)
R-channel output
(ROT, FOR pins)
L-channel signal
R-channel signal
1 Note
Monaural (L+R) signal
Input select 1
Note
00
TV signal
01
External input 1
10
External input 2
11
Setting prohibited
When SAP2 is selected by switching SAP1/SAP2, the L+R signal and SAP signal are composite to be
output.
Data Sheet S13417EJ2V0DS00
33
µPC1851B
(5) Input gain
The gain of the signal to be input to the selector block in the µPC1851B can be selected by the data of bit D6 of
subaddress 03H.
Figure 4-5. Input Gain
03H
D7
D6
0
Input gain
D5
D4
D3
D2
D1
D0
Low-band separation setting
Input gain
0
0 dB
1
6 dB
(6) Surround function
The surround function ON/OFF can be selected by the data of bit D6 of subaddress 04H.
Figure 4-6. Surround Function
04H
D7
D6
0
Surround
D5
D4
D3
D2
High-band separation setting
Surround function
34
0
Surround OFF
1
Surround ON
Data Sheet S13417EJ2V0DS00
D1
D0
µPC1851B
(7) Volume, Balance control
The volume and balance of the output (LOT and ROT pins) can be controlled at 64 levels by the data of bits D0
to D5 of subaddresses 07H and 08H.
The volume attenuation is 80 dB or higher.
Figure 4-7. Volume, Balance Control
• Volume control
07H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Volume control
Volume control
Data
Attenuation
volume
D5 - D0
111111
Flat (0 dB)
|
|
000000
Low
• Balance control
08H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Balance control
Balance control
Data
Data Sheet S13417EJ2V0DS00
D5 - D0
Attenuation
volume
111111
L-ch Low, R-ch Flat
|
|
100000
TYP.
|
|
000000
L-ch Flat, R-ch Low
35
µPC1851B
(8) Bass, Treble control
The bass and treble sound quality of the output (LOT and ROT pins) can be controlled at 64 levels by the data
of the bits D0 to D5 of subaddresses 09H and 0AH.
The bass control amount of the low frequency band width boost/cut is ±11 dB TYP. at 100 Hz.
The treble control amount of the high frequency band width boost/cut is ±13 dB TYP. at 10 kHz.
Figure 4-8. Bass, Treble control
• Bass control
09H
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Bass control
Bass control
Data
Gain
D5 - D0
111111
Boost
|
|
100000
0 dB
|
|
000000
Cut
• Treble control
0AH
D7
D6
0
Automatic
increment
D5
D4
D3
D2
D1
D0
Treble control
Treble control
Data
Gain
D5 - D0
36
Data Sheet S13417EJ2V0DS00
111111
Boost
|
|
100000
0 dB
|
|
000000
Cut
µPC1851B
(9) Automatic increment function
The automatic increment function ON/OFF can be selected by the data of bit D7 of subaddress 06H and that of
bit D6 of subaddresses 07H to 0AH. For the details of the automatic increment function, refer to 3.2 (5) Automatic
increment.
Figure 4-9. Automatic Increment Function
D7
06H
Automatic
increment
D6
D5
Input select 1
D4
D3
D2
Input select 2
SAP1/SAP2
switch
Stereo/SAP
switch
D1
Forced monaural
ON/OFF
D0
Mute
Automatic increment function
0
Automatic increment function OFF
1
Automatic increment function ON
Caution After power-on reset, be sure to set the data.
Data Sheet S13417EJ2V0DS00
37
µPC1851B
4.4 Explanation of Read Register
(1) Power-on reset detection
Whether a power-on reset was detected is detected with bit D7 of the read register.
Figure 4-10. Power-On Reset Detection
D7
D6
D5
D4
D3
Stereo
broadcast
D1
D0
1
1
Reception status
Broadcast status
Power-on
reset
D2
Noise
detection
SAP
broadcast
Stereo
broadcast
reception
SAP
broadcast
reception
Power-on reset detection
1
Power-on reset detection
(2) Stereo, SAP broadcast (broadcast status) detection
Whether SAP or stereo broadcast from a broadcasting station is being broadcast is detected with bits D5 and D6
of the read register.
When a SAP signal (5 fH) or stereo pilot signal is detected, the register data becomes “1”.
Figure 4-11. Stereo, SAP Broadcast (Broadcast Status) Detection
D7
D6
D5
D4
D3
reset
Stereo
broadcast
SAP
broadcast
D1
D0
1
1
Reception status
Broadcast status
Power-on
D2
Noise
detection
Stereo
broadcast
reception
SAP
broadcast
reception
SAP broadcast
0
No SAP broadcast
1
SAP broadcast (SAP signal detected)
Stereo broadcast
38
0
No Stereo broadcast
1
Stereo broadcast (stereo pilot signal detected)
Data Sheet S13417EJ2V0DS00
µPC1851B
(3) Stereo, SAP broadcast reception (reception status) detection
Whether SAP or stereo broadcast is being received and the µPC1851B outputs the audio signal can be detected
with bits D2 and D3 of the read register. The register data become “1” only if the SAP signal (5 fH) is detected when
the SAP broadcast reception is selected, or if the stereo pilot signal is detected when the stereo broadcast reception
is selected.
Figure 4-12. Stereo, SAP Broadcast Reception (Reception Status) Detection
D7
D6
D5
D4
D3
Stereo
broadcast
D1
D0
1
1
Reception status
Broadcast status
Power-on
reset
D2
SAP
broadcast
Noise
detection
Stereo
broadcast
reception
SAP
broadcast
reception
SAP broadcast reception
0
No outputing SAP broadcast
1
Outputing SAP broadcast
Stereo broadcast reception
0
No outputing stereo broadcast
1
Outputing stereo broadcast
(4) Noise detection
Noise can be detected with bit D4 of the read register. It is monitored in the vicinity of the 11.5 fH (180 kHz) signal
level.
During noise detection, the operation of the SAP demodulator block and the stereo demodulation block is interrupted
(Refer to section 4.3 (1) Stereo/SAP output stop function during noise detection).
Figure 4-13. Noise Detection
D7
D6
D5
D4
reset
Stereo
broadcast
SAP
broadcast
D2
D1
D0
1
1
Reception status
Broadcast status
Power-on
D3
Noise
detection
Stereo
broadcast
reception
SAP
broadcast
reception
Noise detection
0
No noise
1
Noise
Data Sheet S13417EJ2V0DS00
39
µPC1851B
5. MODE MATRIX
Mute OFF (Write register, subaddress 06H, bit D0 : “1”)
(1) Read register, bit D4: 0
Broadcast
Write Register
mode
Forced
monaural
ON/OFF
Stereo
/SAP
switch
SAP1
/SAP2
switch
Subaddress
06H
Output
Stereo
/SAP
output
stop
L-ch
output
(LOT )
Bit D2
Bit D3
Bit D6
Monaural
–
–
–
–
Stereo
0
–
–
–
L+R
L
R
1
0
0
–
1
0
1
–
–
0
0
–
1
0
–
(2)
–
Read register, bit D4:
Broadcast
Forced
monaural
ON/OFF
Stereo
/SAP
switch
–
Bit D5
Bit D3
Bit D2
0
0
0
0
1
0
1
0
1
0
0
1
SAP
0
L
R
L+R
1
1
1
0
0
1
SAP
L+R
0
1
SAP1
/SAP2
switch
Output
Stereo
/SAP
output
stop
L-ch
outputl
(LOT)
Read Register
R-ch
output
(ROT)
Broadcast status
Reception status
Stereo
pilot
SAP
signal
Stereo
SAP
broadcast broadcast
reception reception
Bit D6
Bit D5
Bit D3
Bit D2
0
0
0
0
1
0
1
0
Subaddress
00H
Bit D2
Bit D3
Bit D6
Monaural
–
–
–
–
Stereo
0
–
–
0
1
0
SAP
Bit D1
0
Bit D6
L+R
–
Subaddress
06H
Monaural+SAP
Stereo
SAP
broadcast broadcast
reception reception
SAP
Write Register
mode
Reception status
SAP
signal
0
L+R
L+R
1
1
Broadcast status
Stereo
pilot
L+R
1
Stereo+SAP
R-ch
output
(ROT)
Subaddress
00H
Bit D1
Monaural+SAP
Read Register
0
L+R
L
R
1
L+R
0
0
0
L+R
0
0
0
0
1
0
1
0
1
1
0
1
Stereo+SAP
0
0
–
1
0
0
1
L
R
L+R
0
0
0
1
1
0
1
Remarks 1. When the µPC1851B recognizes a weak electric field, bit D4 of the read register becomes “1”.
2. —: Don’t care.
40
Data Sheet S13417EJ2V0DS00
µPC1851B
6. SELECTOR TABLE
Input signal:
TV signal (signal with the audio multiple signal processed in the µPC1851B)
L-channel, R-channel
External input 1 (signal input from EL1, ER1 pins)
L-channel, R-channel
External input 2 (signal input from EL2, ER2 pins)
L-channel, R-channel
Write Register
Mute ON/OFF
Input select 1
Output
Input select 2
Subaddress : 06H
Bit : D0
Bits : D6, D5
Bit : D4
0
––
–
1
00
0
L-channel output
R-channel output
(LOT, FOL pins)
(ROT, FOR pins)
Mute
TV signal (L)
TV signal (R)
01
External input 1 (L)
External input 1 (R)
10
External input 2 (L)
External input 2 (R)
11
00
Setting prohibited (no signal, unconnected)
1
TV signal
1
2
1
2
1
2
(L+R)
01
External input 1
(L+R)
10
External input 2
11
Setting prohibited (no signal, unconnected)
(L+R)
Remark – : Don’t care
Data Sheet S13417EJ2V0DS00
41
µPC1851B
7. USAGE CAUTIONS
7.1 Caution on Shock Noise Reduction
When switching the power ON/OFF, use the external mute (approx. 200 ms) in order to minimize shock noise
(Refer to section 4.3 (2) Mute).
7.2 Supply Voltage
Pass data through the I2C bus only after stabilizing the supply voltage of the entire application system.
7.3 Impedance of Input and Output Pins
Table 7-1. Impedance of Input and Output Pins
Input pin
Output pin
Symbol
Description
Impedance
Symbol
Description
Impedance
COM
Composite signal input
80 kΩ
SOT
SAP single input
360 Ω
SI
SAP single input
ROT
R-channel output
15 Ω
EL1, EL2
External L-channel input
LOT
L-channel output
ER1, ER2
External R-channel input
MOR
R-channel matrix output
MOL
L-channel matrix output
FOR
R-channel fixed output
FOL
L-channel fixed output
7.4 Drive Capability of Output Pins
Table 7-2. Drive Capability of Output Pins
Pin symbol
Pin description
Output pin-GND Connection Resistance
Drive capability
SOT
SAP single output
10 kΩ
3-kΩ load or less
ROT
R-channel output
LOT
L-channel output
MOR
R-channel matrix output
MOL
L-channel matrix output
FOR
R-channel fixed output
FOL
L-channel fixed output
Remark
700-Ω load or less
If the load capacitance of the output pins (SOT, ROT, LOT, MOR, MOL, FOR, FOL pins) exceeds
100 pF, parasitic oscillation may occur. In this case, connect a resistor between the output pins
and the load capacitance. Bear in mind that the load capacitance is changed by wiring pattern on
the printed circuit board.
42
Data Sheet S13417EJ2V0DS00
µPC1851B
7.5 Caution on External Components
According to the license contract with THAT Corporation, use the following for external components.
With regard to the use of other external components, please contact to THAT corporation.
Table 7-3. External Components
Pin symbol
Pin description
External component
ITI
Timing current setting
Metal film resistor (±1 %)
STI
Spectral RMS timing
Tantalum capacitor (±10 %)
WTI
Wide-band RMS timing
7.6 Change of Electrical Characteristics by External Components
(1) SAP sensitivity can be lowered by inserting a resistor between the SDT pin and GND.
(2) Noise sensitivity can be changed by changing the value of the resistor between the NDT pin and GND.
(3) The capture range can be changed by changing the recommended 1 µF value of the capacitor between the
φD1 and φD2 pins.
Reducing the capacitor value increases the capture range, and increasing it reduces the capture range.
However, too small a capacitor value may cause the distortion rate to become worse during stereo output,
or may cause malfunction. In this case, please contact NEC.
Data Sheet S13417EJ2V0DS00
43
µPC1851B
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (unless otherwise specified, TA = 25 °C)
Parameter
Symbol
Conditions
Ratings
Unit
Power supply voltage
VCC
VCC pin
11.0
V
I2C bus input pin voltage
Vcont
SDA, SCL pins
VCC
V
COM pin
VCC
V
700
mW
–20 to +75
°C
–40 to +125
°C
Composite signal input voltage
Vin
Package power dissipation
PD
Operating ambient temperature
TA
Storage temperature
Tstg
VCC = 9 V
Caution Exposure to Absolute Maximum Rating for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
Recommended Operating Conditions (unless otherwise specified, TA = 25 ˚C)
Parameter
Power supply voltage
I2C bus input pin voltage (High level)
2
I C bus input pin voltage (Low level)
Symbol
VCC
Vcont(H)
Conditions
MIN.
TYP.
MAX.
Unit
VCC pin
8.0
9.0
10.0
V
SDA, SCL pins
3.5
–
5.0
V
0
–
1.5
V
Vcont(L)
Input impedance
Rin
COM, SI, EL1, EL2, ER1, ER2 pins
60
–
95
kΩ
Output load impedance 1
RL1
LOT, ROT, MOL, MOR, FOL, FOR pins,
AC load impedance at 100 % modulation
2.0
–
–
kΩ
Output load impedance 2
RL2
SOT pin, AC load impedance at 100 %
modulation
10.0
–
–
kΩ
Output load impedance 3
RL3
LOT, ROT, MOL, MOR, FOL, FOR pins,
DC load impedance at 100 % modulation
5.0
–
–
kΩ
Output load impedance 4
RL4
SOT pin, DC load impedance at 100 %
modulation
25.0
–
–
kΩ
Composite signal input voltage
Vin
COM pin
L+R signal, 100 % modulation
–
0.424
–
Vp-p
L–R signal, 100 % modulation
–
0.848
–
Vp-p
Pilot signal
–
0.0848
–
Vp-p
SAP signal
–
0.254
–
Vp-p
External input signal voltage
Vext
EL1, EL2, ER1, ER2 pins
–
1.4
5.6
Vp-p
Clock frequency
fSCL
SCL pin
–
–
100
kHz
44
Data Sheet S13417EJ2V0DS00
µPC1851B
Electrical Characteristics
(unless otherwise specified, TA = 25 °C, RH ≤ 70 %, VCC = 9.0 V, adding 30 kHz LPF to output pins)
(1/3)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
No signal
–
57
75
mA
15.734 kHz, sine wave
11
16
21
mVrms
Input: COM pin, Output: FOL, FOR pins
Supply current
Stereo detection input sensitivity
ICC
STSENCE
Stereo detection hysteresis
STHY
Only stereo pilot signal input
5.0
5.7
10
dB
Stereo detection capture range
STCCL
Vin = 30 mVrms
–5.5
–4.0
–2.5
%
STCCH
Only stereo pilot signal input
+2.5
+4.0
+5.5
%
SAPSENCE
f = 78.67 kHz, 0% modulation
17
23
30
mVrms
Only SAP carrier input
3.3
4.8
6.3
dB
NOSENCE
Input sine wave
f: Noise BPF peak
20
30
40
mVrms
Noise detection hysteresis
NOHY
Input sine wave
f: Noise BPF peak
1
2
3
dB
Monaural total output voltage
VOMO
300 Hz, 100% modulation,
Pre-emphasis: ON
480
500
520
mVrm
Stereo total output voltage
VOST
300 Hz, 100 % modulation
450
500
550
mVrms
Noise reduction: ON
400
500
600
mVrms
SAP detection input sensitivity
SAP detection hysteresis
Noise detection input sensitivity
SAP total output voltage
SAPHY
VOSAP1
Difference between monaural L and R
output voltage
VOLR
300 Hz, 100% modulation
–0.5
–
+0.5
dB
Monaural total frequency characteristics 1
VOMO1
1 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Pre-emphasis: ON
–0.5
–
+0.5
dB
Monaural total frequency characteristics 2
VOMO2
3 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Pre-emphasis: ON
–0.5
–
+0.5
dB
Monaural total frequency characteristics 3
VOMO3
8 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Pre-emphasis: ON
–0.8
–
+0.8
dB
Monaural total frequency characteristics 4
VOMO4
12 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Pre-emphasis: ON
–5.5
–3.0
–1.5
dB
Stereo total frequency characteristics 1
VOST1
1 kHz, 30% modulation, (f = 300 Hz: 0 dB)
–0.5
–
+0.5
dB
Noise reduction: ON
Stereo total frequency characteristics 2
VOST2
3 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Noise reduction: ON
–0.5
–
+0.5
dB
Stereo total frequency characteristics 3
VOST3
8 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Noise reduction: ON
–1.0
–
+1.0
dB
Stereo total frequency characteristics 4
VOST4
12 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Noise reduction: ON
–8.0
–5.0
–2.0
dB
SAP total frequency characteristics 1
VOSAP11
1 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Noise reduction: ON
–1.2
+0.3
+1.2
dB
SAP total frequency characteristics 2
VOSAP12
3 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Noise reduction: ON
–1.2
0.0
+1.2
dB
SAP total frequency characteristics 3
VOSAP13
8 kHz, 30% modulation, (f = 300 Hz: 0 dB)
Noise reduction: ON
–4.0
–1.0
+1.0
dB
27
32
–
dB
Stereo channel separation 1
Sep1
300 Hz, 30% modulation
Data Sheet S13417EJ2V0DS00
45
µPC1851B
(2/3)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Stereo channel separation 2
Sep2
1 kHz, 30% modulation
23
30
–
dB
Stereo channel separation 3
Sep3
3 kHz, 30% modulation
27
35
–
dB
Stereo channel separation 4
Sep4
5 kHz, 30 % modulation
23
30
–
dB
Stereo channel separation 5
Sep5
8 kHz, 30 % modulation
–
25
–
dB
Monaural total harmonic distortion
THDMO
1 kHz, 100% modulation
Pre-emphasis: ON
–
0.1
0.5
%
Stereo total harmonic distortion 1
THDST1
1 kHz, 100% modulation
Noise reduction: ON
–
0.3
1.5
%
Stereo total harmonic distortion 2
THDST2
8 kHz, 30% modulation
Noise reduction: ON
–
0.8
1.8
%
SAP total harmonic distortion
THDSAP
1 kHz, 100% modulation
Noise reduction: ON
–
0.5
2.0
%
Crosstalk 1 (SAP → Stereo)
CT1
SAP : 1 kHz, 100 % modulation
Stereo : Pilot signal only, 0 % modulation
Filter: 1 kHz BPF
User mode: Stereo
–
–
–65
dB
Crosstalk 2 (Stereo → SAP)
CT2
Stereo : 1 kHz, 100 % modulation,
SAP : Carrier only, 0 % modulation
Filter: 1 kHz BPF
User mode: SAP1
–
–
–65
dB
Monaural total S/N
S/NMO
300 Hz, 100% modulation
Pre-emphasis: ON
65
68
–
dB
Stereo total S/N
S/NST
300 Hz, 100 % modulation
60
65
–
dB
SAP total S/N
S/NSAP
Noise reduction: ON
70
80
–
dB
TV signal : 1 kHz, 100 % modulation
External input : 1 kHz, 500 mVrms
80
–
–
dB
Current provided to STI and WTI pins
7.1
7.5
7.9
µA
Input: External input pins, output: LOT, ROT pins
Total muting level
Timing current
Mute
IT
Inter-mode DC offset 1
VDOF1
Mute → Monaural
–50
–
+50
mV
Inter-mode DC offset 2
VDOF2
Mute → Stereo
–50
–
+50
mV
Inter-mode DC offset 3
VDOF3
Mute → SAP1
–50
–
+50
mV
Inter-mode DC offset 4
VDOF4
Mute → External input
–50
–
+50
mV
Surround output characteristics 1
VSR1L
External L-channel input : 100 Hz, 150 mVrms
Surround : ON, LOT pin
–7.5
–4.5
0.0
dB
Surround output characteristics 2
VSR2L
External L-channel input : 1 kHz, 150 mVrms
Surround : ON, LOT pin
4.0
5.6
7.0
dB
Surround output characteristics 3
VSR3L
External L-channel input : 10 kHz, 150 mVrms
Surround : ON, LOT pin
4.5
–
8.0
dB
Surround output characteristics 4
VSR4R
External L-channel input : 1 kHz, 150 mVrms
Surround : ON, ROT pin
–1.5
–
+1.5
dB
46
Data Sheet S13417EJ2V0DS00
µPC1851B
(3/3)
Parameter
Symbol
Conditions
Low frequency band width boost control
VBB
100 Hz,
Low frequency band width cut control
VBC
External input = 150 mVrms
High frequency band width boost control
VTB
10 kHz,
High frequency band width cut control
VTC
External input = 150 mVrms
Subaddress
Data
MIN.
TYP.
MAX.
Unit
09H
3FH
9
11
13
dB
00H
–13
–11
–9
dB
3FH
10
13
16
dB
00H
–16
–13
–10
dB
3FH
–1.0
0.0
+1.0
dB
20H
–20
–17.5
–14
dB
00H
–
–
–80
dB
3FH
–
–
–60
dB
30H
–14
–10
–6
dB
0AH
Volume attenuation 1
ATTVL1
1 kHz,
Volume attenuation 2
ATTVL2
External input = 500 mVrms
Volume attenuation 3
ATTVL3
Balance attenuation L-ch 1
ATTBL1
1 kHz,
Balance attenuation L-ch 2
ATTBL2
External input = 500 mVrms
Balance attenuation L-ch 3
ATTBL3
20H
–1.0
0.0
+1.0
dB
Balance attenuation L-ch 4
ATTBL4
00H
–1.0
0.0
+1.0
dB
Balance attenuation R-ch 1
ATTBR1
3FH
–1.0
0.0
+1.0
dB
Balance attenuation R-ch 2
ATTBR2
20H
–1.0
0.0
+1.0
dB
Balance attenuation R-ch 3
ATTBR3
10H
–14
–10
–6
dB
Balance attenuation R-ch 4
ATTBR4
00H
–
–
–60
dB
3FH
–1.5
0.0
+1.5
dB
1 kHz,
External input = 500 mVrms
07H
08H
Difference between monaural L and R
output voltage 1
(in case of external input)
VOLR1
07H
Difference between monaural L and R
output voltage 2
(in case of external input)
VOLR2
20H
–2.0
0.0
+2.0
dB
Difference between monaural L and R
VOLR3
10H
–3.0
0.0
+3.0
dB
3FH
–
–
–80
dB
–
–80
–70
dB
output voltage 3
(in case of external input)
Crosstalk 3
TV signal → External input
CT3
TV signal: 1 kHz,
100 % modulation
Crosstalk 4
L-ch → R-ch
CT4
External input:
1 kHz, 500 mVrms
Total harmonic distortion
(in case of external input)
THDEXT
07H
1 kHz,
External input = 500 mVrms
07H
3FH
–
0.1
0.5
%
Maximum input voltage of external input
VIEM
1 kHz,
Total harmonic
distortion rate: 1 %
(External input)
07H
3FH
1.7
2.1
–
Vrms
Output noise
(in case of external input)
NO
No signal, Rg = 600 Ω,
Filter: DIN/AUDIO
07H
3FH
–
50
150
µVrms
Data Sheet S13417EJ2V0DS00
47
µPC1851B
Test Condition Parameters for Electrical Characteristics
(Unless otherwise specified, TA = 25 ˚C, RH ≤ 70 %, VCC = 9 V, adding 30 kHz LPF to output pins)
(1/8)
Parameter
Supply current
Stereo detection input
sensitivity
Symbol
ICC
STSENCE
Test Conditions
ICC : Current sent to VCC pin when there is no signal
STSENCE : Input signal level of COM pin (input signal: 15.734 kHz)
When read register D6 changes from 0 to 1
Stereo detection hysteresis
STHY
STHY =20 log (STSENCE ÷ V)
STSENCE: Stereo detection input sensitivity
V: Input signal level of COM pin (Input signal: 15.734 kHz)
Read register D6 is first set to 1, then input signal level is gradually
lowered until D6 is changed to 0
Stereo detection
capture range
STCCL
STCCL = ∆f ÷ 15.734 kHz
∆f: Difference between f and 15.734 kHz
f: Input signal (14.5 kHz, 30 mVrms) to COM pin.
Gradually raise frequency and measure frequency
User Mode Note
Monaural
Stereo
when read register D6 becomes 1.
STCCH
SAP detection input
sensitivity
SAP detection hysteresis
Noise detection input
sensitivity
SAPSENCE
STCCH = ∆f ÷ 15.734 kHz
∆f: Difference between f and 15.734 kHz
f: Input signal (17.0 kHz, 30 mVrms) to COM pin.
Gradually lower frequency and measure frequency
when read register D6 becomes 1.
SAPSENCE : Input signal level of COM pin (input signal: 78.67 kHz)
When read register D5 changes from 0 to 1
SAPHY
SAPHY =20 log (SAPSENCE ÷ V)
SAPSENCE: SAP detection input sensitivity
V: Input signal level of COM pin (Input signal: 78.67 kHz)
When read register D5 is first set to 1, input signal level is gradually
lowered until D5 becomes 0.
NOSENCE
NOSENCE: Input signal level of COM pin
Read register D4: Apply 6-V DC voltage to SDT pin to change it to 0
Read register D4: Input signal (160 kHz, 10 mVrms) to COM pin.
Raise the frequency until the DC voltage of the NDT pin reaches
the maximum level, and then, while maintaining the frequency
level, gradually raise the input signal level until D4 becomes 1.
Noise detection hysteresis
NOHY
NOHY = 20 log (NOSENCE ÷ V)
NOSENCE: Noise detection input sensitivity
V: Input signal level of NDT pin
COM pin: Signal (160 kHz, 10 mVrms) input
After read register D4 is set to 1, raise the frequency until the DC
voltage of the NDT pin reaches the maximum level, and then,
while maintaining the frequency level, gradually lower the input
signal level until D4 becomes 0.
Monaural total output voltage
VOMO
VOMO : Output voltage of FOL and FOR pins
COM pin: Monaural signal (300 Hz, 100 % modulation) input
Stereo total output voltage
VOST
L-channel
VOST : Output voltage of FOL pin
COM pin: Stereo signal (L-only, 300 Hz, 100 % modulation) input
R-channel
VOST : Output voltage of FOR pin
COM pin: Stereo signal (R-only, 300 Hz, 100 % modulation) input
Note For details about the User Mode, refer to 5. MODE MATRIX.
48
Data Sheet S13417EJ2V0DS00
SAP
SAP
Monaural
Stereo
µPC1851B
(2/8)
Parameter
SAP total output voltage
Symbol
VOSAP1
Test Conditions
VOSAP1 : Output voltage of FOL and FOR pins
COM pin: SAP signal (300 Hz, 100 % modulation) input
User Mode Note
SAP1
Difference between monaural
L and R output voltage
VOLR
VOLR = 20 log (V L ÷ V R)
VL: Output voltage of FOL pin
COM pin: Monaural signal (300 Hz, 100 % modulation) input
VR: Output voltage of FOR pin
COM pin: Monaural signal (300 Hz, 100 % modulation) input
Monaural
Monaural total frequency
characteristics 1
VOMO1
VOMO1 = 20 log {V(1k) ÷ V(300)}
V(1k): Output voltage of FOL pin
COM pin: Monaural signal (1 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Monaural signal (300 Hz, 30 % modulation) input
Monaural
Monaural total frequency
characteristics 2
VOMO2
VOMO2 = 20 log {V(3k) ÷ V(300)}
V(3k): Output voltage of FOL pin
COM pin: Monaural signal (3 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Monaural signal (300 Hz, 30 % modulation) input
Monaural total frequency
characteristics 3
VOMO3
VOMO3 = 20 log {V(8k) ÷ V(300)}
V(8k): Output voltage of FOL pin
COM pin: Monaural signal (8 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Monaural signal (300 Hz, 30 % modulation) input
Monaural total frequency
characteristics 4
VOMO4
VOMO4 = 20 log {V(12k) ÷ V(300)}
V(12k): Output voltage of FOL pin
COM pin: Monaural signal (12 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Monaural signal (300 Hz, 30 % modulation) input
Stereo total frequency
characteristics 1
VOST1
VOST1 = 20 log {V(1k) ÷ V(300)}
V(1k): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input
Stereo total frequency
characteristics 2
VOST2
VOST2 = 20 log {V(3k) ÷ V(300)}
V(3k): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input
Stereo total frequency
characteristics 3
VOST3
VOST3 = 20 log {V(8k) ÷ V(300)}
V(8k): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input
Stereo total frequency
characteristics 4
VOST4
VOST4 = 20 log {V(12k) ÷ V(300)}
V(12k): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 12 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input
Stereo
Note For details about the User Mode, refer to 5. MODE MATRIX.
Data Sheet S13417EJ2V0DS00
49
µPC1851B
(3/8)
Parameter
Symbol
Test Conditions
SAP total frequency
characteristics 1
VOSAP11
VOSAP11 = 20 log {V(1k) ÷ V(300)}
V(1k): Output voltage of FOL pin
COM pin: SAP signal (1 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: SAP signal (300 Hz, 30 % modulation) input
SAP total frequency
characteristics 2
VOSAP12
VOSAP12 = 20 log {V(3k) ÷ V(300)}
V(3k): Output voltage of FOL pin
COM pin: SAP signal (3 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: SAP signal (300 Hz, 30 % modulation) input
SAP total frequency
characteristics 3
VOSAP13
VOSAP13 = 20 log {V(8k) ÷ V(300)}
V(8k): Output voltage of FOL pin
COM pin: SAP signal (8 kHz, 30 % modulation) input
V(300): Output voltage of FOL pin
COM pin: SAP signal (300 Hz, 30 % modulation) input
Stereo channel
Sep1
separation 1
L-channel
Sep1 = 20 log (VL ÷ VR)
VL: Output voltage of FOL pin
COM pin: Stereo signal (L-only, 300 Hz, 30% modulation) input
VR: Output voltage of FOR pin
COM pin: Stereo signal (L-only, 300 Hz, 30 % modulation) input
R-channel
Sep1 = 20 log (VR ÷ VL)
VR: Output voltage of FOR pin
COM pin: Stereo signal (R-only, 300 Hz, 30 % modulation) input
VL: Output voltage of FOL pin
COM pin: Stereo signal (R-only, 300 Hz, 30 % modulation) input
Stereo channel
separation 2
Sep2
L-channel
Sep2 = 20 log (VL ÷ VR)
VL: Output voltage of FOL pin
COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input
VR: Output voltage of FOR pin
COM pin: Stereo signal (L-only, 1 kHz, 30 % modulation) input
R-channel
Sep2 = 20 log (VR ÷ VL)
VR: Output voltage of FOR pin
COM pin: Stereo signal (R-only, 1 kHz, 30 % modulation) input
VL: Output voltage of FOL pin
COM pin: Stereo signal (R-only, 1 kHz, 30 % modulation) input
Stereo channel
separation 3
Sep3
L-channel
Sep3 = 20 log (VL ÷ VR)
VL: Output voltage of FOL pin
COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input
VR: Output voltage of FOR pin
COM pin: Stereo signal (L-only, 3 kHz, 30 % modulation) input
R-channel
Sep3 = 20 log (VR ÷ VL)
VR: Output voltage of FOR pin
COM pin: Stereo signal (R-only, 3 kHz, 30 % modulation) input
VL: Output voltage of FOL pin
COM pin: Stereo signal (R-only, 3 kHz, 30 % modulation) input
Note For details about the User Mode, refer to 5. MODE MATRIX.
50
Data Sheet S13417EJ2V0DS00
User Mode Note
SAP1
Stereo
µPC1851B
(4/8)
Parameter
Stereo channel separation 4
Symbol
Sep4
Test Conditions
L-channel
Sep4 = 20 log (VL ÷ VR)
VL: Output voltage of FOL pin
COM pin: Stereo signal (L-only, 5 kHz, 30 % modulation) input
VR: Output voltage of FOR pin
COM pin: Stereo signal (L-only, 5 kHz, 30 % modulation) input
User Mode Note
Stereo
R-channel
Sep4 = 20 log (VR ÷ VL)
VR: Output voltage of FOR pin
COM pin: Stereo signal (R-only, 5 kHz, 30 % modulation) input
VL: Output voltage of FOL pin
COM pin: Stereo signal (R-only, 5 kHz, 30 % modulation) input
Stereo channel separation 5
Sep5
L-channel
Sep5 = 20 log (VL ÷ VR)
VL: Output voltage of FOL pin
COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input
VR: Output voltage of FOR pin
COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input
R-channel
Sep5 = 20 log (VR ÷ VL)
VR: Output voltage of FOR pin
COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input
VL: Output voltage of FOL pin
COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input
Monaural total harmonic
distortion
THDMO
THDMO : Distortion rate of FOL and FOR pins
COM pin: Monaural signal (1 kHz, 100 % modulation) input
Stereo total harmonic
THDST1
L-channel
THDST1 : Distortion rate of FOL pin
COM pin: Stereo signal (L-only, 1 kHz, 100 % modulation) input
distortion 1
Monaural
Stereo
R-channel
THDST1 : Distortion rate of FOR pin
COM pin: Stereo signal (R-only, 1 kHz, 100 % modulation) input
Stereo total harmonic
distortion 2
THDST2
L-channel
THDST2 : Distortion rate of FOL pin
COM pin: Stereo signal (L-only, 8 kHz, 30 % modulation) input
R-channel
THDST2 : Distortion rate of FOR pin
COM pin: Stereo signal (R-only, 8 kHz, 30 % modulation) input
SAP total harmonic
THDSAP
distortion
THDSAP : Distortion rate of FOL and FOR pins
COM pin: SAP signal (1 kHz, 100 % modulation) input
SAP1
Crosstalk 1 (SAP→Stereo)
CT1
CT1 = 20 log (VCT1 ÷ 500 mV)
VCT1: Measure output voltage of FOL or FOR pins after BPF (1 kHz)
SAP: 1 kHz, 100 % modulation
Stereo: Pilot signal only, 0 % modulation
Stereo
Crosstalk 2 (Stereo→SAP)
CT2
CT2 = 20 log (VCT2 ÷ 500 mV)
VCT2: Measure output voltage of FOL or FOR pins after BPF (1 kHz)
Stereo: 1 kHz, 100 % modulation
SAP: Carrier only, 0 % modulation
SAP1
Note For details about the User Mode, refer to 5. MODE MATRIX.
Data Sheet S13417EJ2V0DS00
51
µPC1851B
(5/8)
Parameter
Monaural total S/N
Symbol
S/NMO
Test Conditions
L-channel
S/NMO = 20 log (VOMOL ÷ VL)
VOMOL : Output voltage of FOL pin after LPF (30 kHz)
COM pin: Monaural signal (300 Hz, 100 % modulation) input
VL: Output voltage of FOL pin (no signal)
User Mode Note
Monaural
R-channel
S/NMO = 20 log (VOMOR ÷ VR)
VOMOR: Output voltage of FOR pin after LPF (30 kHz)
COM pin: Monaural signal (300 Hz, 100 % modulation) input
VR: Output voltage of FOR pin (no signal)
Stereo total S/N
S/NST
L-channel
S/NST = 20 log (VOSTL ÷ VL)
VOSTL : Output voltage of FOL pin after LPF (30 kHz)
COM pin: Stereo signal (L-only, 300 Hz, 100 % modulation) input
VL: Output voltage of FOL pin
Stereo
COM pin: Pilot signal input
R-channel
S/NST = 20 log (VOSTR ÷ VR)
VOSTR : Output voltage of FOR pin after LPF (30 kHz)
COM pin: Stereo signal (R-only, 300 Hz, 100 % modulation) input
VR: Output voltage of FOR pin
COM pin: Pilot signal input
SAP total S/N
S/NSAP
L-channel
S/NSAP = 20 log (VOSAP1L ÷ VL)
VOSAP1L : Output voltage of FOL pin after LPF (30 kHz)
COM pin: SAP signal (300 Hz, 100 % modulation) input
VL: Output voltage of FOL pin
COM pin: SAP carrier (0 % modulation) input
SAP1
R-channel
S/NSAP = 20 log (VOSAP1R ÷ VR)
VOSAP1R : Output voltage of FOR pin after LPF (30 kHz)
COM pin: SAP signal (300 Hz, 100 % modulation) input
VR: Output voltage of FOR pin
COM pin: SAP carrier (0 % modulation) input
Total muting level
Timing current
Inter-mode DC offset 1
Mute
Mute = 20 log (VOMOL ÷ VM)
VOMOL : Output voltage of LOT pin
COM pin: Monaural signal (1 kHz, 100 % modulation) input
VM : Output voltage of LOT pin
Write register 06H, D0: 0
COM pin: Monaural signal (1 kHz, 100 % modulation) input
IT
IT : Current that flows from VCC to STI, WTI pins
STI, WTI pins : 6 V DC is applied.
VDOF1
VDOF1 = VMONO – VMute
VMONO : DC voltage at LOT and ROT pins
User mode : Monaural
NDT pin: 6 V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Note For details about the User Mode, refer to 5. MODE MATRIX.
52
Data Sheet S13417EJ2V0DS00
Monaural
mute
Mute
to
Monaural
µPC1851B
(6/8)
Parameter
Symbol
Test Conditions
User Mode Note
Inter-mode DC offset 2
VDOF2
VDOF2 = VST – VMute
VST : DC voltage at LOT and ROT pins
User mode : Stereo
NDT pin: 6 V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Mute
to
Stereo
Inter-mode DC offset 3
VDOF3
VDOF3 = VSAP – VMute
VSAP : DC voltage at LOT and ROT pins
User mode : SAP1
NDT pin: 6 V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Mute
to
SAP1
Inter-mode DC offset 4
VDOF4
VDOF4 = VMONO – VMute
VMONO : DC voltage at LOT and ROT pins
User mode : External input
NDT pin: 6 V DC is applied.
VMute : DC voltage at LOT and ROT pins
User mode : Mute (write register 06H, D1: 0)
NDT pin: 6 V DC is applied.
Mute
to
External
input
Surround output
characteristics 1
VSR1L
VSR1L = 20 log (V L1 ÷ VEL)
VL1: Output voltage of LOT pin
VEL: Input voltage of EL1, EL2 pins (100 Hz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Surround output
characteristics 2
VSR2L
VSR2L : 20 log (V L2 ÷ VEL)
VL2: Output voltage of LOT pin
VEL: Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
Surround output
VSR3L
VSR3L : 20 log (V L3 ÷ VEL)
VL3: Output voltage of LOT pin
VEL: Input voltage of EL1, EL2 pins (10 kHz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
VSR4R
VSR4R : 20 log (VR ÷ VEL)
VR: Output voltage of ROT pin
VEL: Input voltage of EL1, EL2 pins (1 kHz, 150 mVrms)
ER1, ER2 pins: No signal
Surround: ON (Subaddress 04H, Bit D6: 1)
characteristics 3
Surround output
characteristics 4
External input 1
External input 2
Note For details about the User Mode, refer to 5. MODE MATRIX.
Data Sheet S13417EJ2V0DS00
53
µPC1851B
(7/8)
Parameter
Symbol
Test Conditions
Sub-
Data
User Mode
3FH
External
input 1,
External
input 2
address
Low frequency band
width boost control
VBB
Low frequency band
width cut control
VBC
High frequency band
width boost control
VTB
High frequency band
width cut control
VTC
Volume attenuation 1
ATTVL1
Volume attenuation 2
ATTVL2
Volume attenuation 3
ATTVL3
Balance attenuation L-ch 1
ATTBL1
Balance attenuation L-ch 2
ATTBL2
Balance attenuation L-ch 3
ATTBL3
Balance attenuation L-ch 4
ATTBL4
Balance attenuation R-ch 1
ATTBR1
Balance attenuation R-ch 2
ATTBR2
Balance attenuation R-ch 3
ATTBR3
Balance attenuation R-ch 4
ATTBR4
Difference between
monaural L and R
output voltage 1
(in case of external input)
VOLR1
Difference between
monaural L and R
output voltage 2
(in case of external input)
VOLR2
Difference between
monaural L and R
output voltage 3
(in case of external input)
VOLR3
Bass response = 20 log (VOUT ÷ VIN)
VIN: Input signal level (sine wave: 100 Hz,
150 mVrms) of external input 1 (EL1, ER1 pins)
or external input 2 (EL2, ER2 pins)
VOUT: Output signal level of LOT, ROT pins
09H
Treble response = 20 log (VOUT ÷ VIN)
VIN: Input signal level (sine wave: 10 kHz,
150 mVrms) of external input 1 (EL1, ER1 pins)
or external input 2 (EL2, ER2 pins)
VOUT: Output signal level of LOT, ROT pins
0AH
Volume attenuation = 20 log (VOUT ÷ VIN)
VIN: Input signal level (sine wave: 1 kHz,
500 mVrms) of external input 1 (EL1, ER1 pins)
or external input 2 (EL2, ER2 pins)
VOUT: Output signal level of LOT, ROT pins
07H
3FH
00H
3FH
20H
External
input 1,
External
input 2
00H
Balance attenuation = 20 log (VOUT ÷ VIN)
VIN: Input signal level (sine wave: 1 kHz,
500 mVrms) of external input 1 (EL1 pin)
or external input 2 (EL2 pin)
VOUT: Output signal level of LOT pin
08H
Balance attenuation = 20 log (VOUT ÷ VIN)
VIN: Input signal level (sine wave: 1 kHz,
500 mVrms) of external input 1 (ER1 pin)
or external input 2 (ER2 pin)
VOUT: Output signal level of ROT pin
08H
Error between channels
= 20 log (VROUT ÷ VRIN) – 20 log (VLOUT ÷ VLIN)
External input 1
VROUT: Output signal level of ROT pin
VRIN: Input signal level of ER1 pin
(sine wave: 1 kHz, 500 mVrms)
VLOUT: Output signal level of LOT pin
VLIN: Input signal level of EL1 pin
(sine wave: 1 kHz, 500 mVrms)
External input 2
VROUT: Output signal level of ROT pin
VRIN: Input signal level of ER2 pin
(sine wave: 1 kHz, 500 mVrms)
VLOUT: Output signal level of LOT pin
VLIN: Input signal level of EL2 pin
(sine wave: 1 kHz, 500 mVrms)
07H
Note For details about the User Mode, refer to 5. MODE MATRIX.
54
00H
Data Sheet S13417EJ2V0DS00
3FH
30H
20H
External
input 1,
External
input 2
00H
3FH
20H
10H
External
input 1,
External
input 2
00H
3FH
20H
10H
External
input 1,
External
input 2
Note
µPC1851B
(8/8)
Parameter
Symbol
Test Conditions
Sub-
Data
User Mode
Note
address
Crosstalk 3
TV signal
→ External input
CT3
CT3 = 20 log (VEXT ÷ VTV)
VEXT: Output voltage of LOT or ROT pin when the
input select 1 is set to the external input 1 or 2
(the data of bits D6 and D5 of subaddress 06H are
“01” or “10”).
VTV: Output voltage ROT or LOT pin when the
input select 1 is set to the TV signal (the data of
bits D6 and D5 of subaddress 06H are “00”).
COM pin: Monaural, stereo or SAP signal
(1 kHz, 100 % modulation) input
External input 1 (EL1, ER1 pins), external input 2
(EL2, ER2 pins): No input
Measure the values of the external inputs 1 and 2
individually.
07H
3FH
External
input 1,
External
input 2,
Stereo,
SAP,
Monaural
Crosstalk 4
L-ch → R-ch
CT4
CT4 = 20 log (VEXTR ÷ VEXTL)
VEXTR: Output voltage of ROT pin when the input
select 1 is set to the external input 1 or 2
(the data of bits D6 and D5 of subaddress 06H are
“01” or “10”).
VEXTL: Output voltage LOT pin when the input
select 1 is set to the external input 1 or 2 (the data
of bits D6 and D5 of subaddress 06H are “01” or
“10”).
EL1, EL2 pins: External input signal (1 kHz,
500 mVrms) input
ER1, ER2 pins: No input
Measure the values of the external inputs 1 and 2
individually.
07H
3FH
External
input 1,
External
input 2
Total harmonic distortion
(in case of external input)
THDEXT
THDEXT: Total harmonic distortion rate of LOT,
ROT pins
External input 1 (EL1, ER1 pins), external input 2
(EL2, ER2 pins): External input signal (1 kHz,
500 mVrms) input
07H
3FH
External
input 1,
External
input 2
Maximum input voltage of
external input
VIEM
VIEM: Maximum input voltage level
External input 1 (EL1, ER1 pins), external input 2
(EL2, ER2 pins): External input signal (1 kHz)
input when the total harmonic distortion rate of
LOT and ROT pins becomes 1 %.
07H
3FH
External
input 1,
External
input 2
Output noise
(in case of external input)
NO
NO: Output noise of LOT, ROT pins through
DIN/AUDIO
External input 1 (EL1, ER1 pins), external input 2
(EL2, ER2 pins): No input (grounded through the
resistor (Rg = 600 Ω))
07H
3FH
External
input 1,
External
input 2
Note For details about the User Mode, refer to 5. MODE MATRIX.
Data Sheet S13417EJ2V0DS00
55
A
L-channel fixed output
B
R-channel fixed output
C
External L-channel input 1
D
External R-channel input 1
E
External L-channel input 2
F
External R-channel input 2
G
L-channel Matrix output
H
R-channel Matrix output
I
L-channel output
J
R-channel output
K
fH monitor
Data Sheet S13417EJ2V0DS00
L
Composite signal input
9. TEST CIRCUIT
56
Test Points
FOL
FOR
A
B
LPRS520-35 (88PJ)
AGND
C
D
E
F
G
H
I
J
JP
DGND
VDD
Connector
for cable
0.1 µ F
FOL
FOR
EL1 ER1 EL2 ER2 MOL MOR LOT ROT
µ PC78M05AHF
AGND
0.1 µ F
DVDD
(+5 V)
Microcontroller DGND
peripheral block SDA
SCL
VCC
DGND
SDA
Microcontroller/PC
change-over switch
µ PC1851B peripheral block
FHM
VCC
K
SCL
COM
DVDD DGND
(+5 V)
SCL
SDA
EEPROMTM block
L
DVDD DGND
(+5 V) SDA(P)
SDA
SCL(P)
SCL
IN(P)
PC
connector
Interface block
Overall surface analog GND
COM
µPC1851B
Overall surface digital GND
µPC1851B
µPC1851B Peripheral Block
10 kΩ
–
+
FHM
µPC842C (1/2)
10 kΩ
6.8 kΩ
1 MΩ
+
Note
4
6
1 2 3
3 kΩ
91 kΩ
+
10 µF
10 µ F
+
–
+
30 kΩ 10 µF
µPC842C (1/2)
µ PC1851B
VCC
22 µF
3
1 kΩ
4
1 µF
+
+
2.2 µ F
COM
VRE
2
0.1 µF
4.7 µF
VCC
1
+
5
6
+
7
0.047 µ F
8
0.47 µ F
+
9
0.1 µF
10
68 kΩ
0.1 µF
1 µF
1 µF
+
3.3 µ F
**
3 kΩ
16.6 kΩ
*
10 µF
**
+ 5.1 kΩ
11
+
12
+
13
14
15
+
16
17
1 µF
+
4.7 µ F
+
1 µF
+
18
19
20
AGND
21
MOA
FOL
PD1
FOR
PD2
EL1
φ D1
ER1
φ D2
EL2
COM
ER2
SDT
MOL
NDT
MOR
SOT
LBC
SI
LTC
SOA
TLO
STI
RBC
SRB
RTC
ITI
TRO
WTI
SUR
WRB
LOT
dO
VOL-C
ROT
DGND
VOA
SCL
AGND
SDA
+
1µ F
+
2.2 µ F
42
41
+
40
+
2.2 µ F
+
2.2 µ F
+
2.2 µ F
+
2.2 µ F
+
2.2 µ F
+
2.2 µ F
+
0.1 µ F
39
38
37
36
35
34
33
2.2 µ F
FOL
FOR
EL1
ER1
EL2
ER2
MOL
MOR
2200 pF
32
+
2.2 µ F
+
0.1 µ F
31
30
2200 pF
29
+
28
2.2 µ F
0.022 µ F
27
+
10 µ F
+
10 µ F
26
25
24
23
22
LOT
ROT
DGND
SCL
SDA
Note Filter: 126XGS-7990Z, TOKO
Remark Use the followings for external parts.
Resistor (*): Metal film resistor (±1 %). Unless otherwise specified; ±5 %
Capacitors (**): Tantalum capacitor (±10 %). Unless otherwise specified, ±20 %
Data Sheet S13417EJ2V0DS00
57
µPC1851B
10. PACKAGE DRAWINGS
42-PIN PLASTIC SDIP (15.24mm(600))
42
22
1
21
A
K
J
L
I
F
D
C
N
R
M
M
H
B
G
NOTES
1. Each lead centerline is located within 0.17 mm of
its true position (T.P.) at maximum material condition.
2. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
A
39.13 MAX.
B
C
1.78 MAX.
1.778 (T.P.)
D
F
0.50±0.10
0.85 MIN.
G
H
3.2±0.3
0.51 MIN.
I
4.31 MAX.
J
5.72 MAX.
K
15.24 (T.P.)
L
13.2
M
0.25 +0.10
−0.05
N
0.17
R
0∼15°
P42C-70-600B-2
58
Data Sheet S13417EJ2V0DS00
µPC1851B
11. RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For more details, refer to our document ”Semiconductor Device Mounting Technology Manual” (C10535E).
µPC1851BCU: 42-pin plastic SDIP (15.24 mm (600))
Process
Conditions
Wave soldering (only to leads)
Solder temperature: 260 °C or below,
Flow time: 10 seconds or less
Partial heating method
Pin temperature: 300 °C or below,
Heat time: 3 seconds or less (per each lead)
Caution The wave soldering process must be applied only to leads, and the make sure that
the package body does not get jet soldered.
Data Sheet S13417EJ2V0DS00
59
µPC1851B
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specifications as defined by Philips.
EEPROM is a trademark of NEC Corporation.
• The information in this document is current as of May, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
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• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
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parties arising from the use of these circuits, software and information.
• While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
• NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
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and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4