DATA SHEET MOS INTEGRATED CIRCUIT µPD16721 384-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES) DESCRIPTION The µPD16721 is a source driver for TFT-LCDs capable of dealing with displays with 256-gray scales. Data input is based on digital input configured as 8 bits by 6 dots (2 pixels), which can realize a full-color display of 16,777,216 colors by output of 256 values γ -corrected by an internal D/A converter and 8-by-2 external power modules. Because the output dynamic range is as large as VSS2 + 0.2 V to VDD2 – 0.2 V, level inversion operation of the LCD’s common electrode is rendered unnecessary. Also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driver is equipped with a built-in 8-bit D/A converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. The maximum clock frequency is 70 MHz when driving at 3.0 V. FEATURES ★ ★ ★ ★ ★ ★ • CMOS level input • 384 outputs • Input of 8 bits (gray scale data) by 6 dots • Capable of outputting 256 values by means of 8-by-2 external power modules (16 units) and a D/A converter • Logic power supply voltage (VDD1): 2.5 to 3.4 V • Driver power supply voltage (VDD2): 13.0 ± 0.5 V or 15.0 ± 0.5 V (switchable, VSEL) • High-speed data transfer: fCLK. = 70 MHz MAX. (internal data transfer speed when operating at VDD1 = 3.0 V) = 55 MHz MAX. (internal data transfer speed when operating at VDD1 = 2.5 V) • Output dynamic range: VSS2 + 0.2 V to VDD2 – 0.2 V • Apply for dot-line inversion, n-line inversion and column line inversion • Output voltage polarity inversion function (POL) • Output inversion function (POL21/22) • Output reset control is possible (MODE) • Slew-rate control is possible (SRC) • Output resistance control is possible (ORC) • Single bank arrangement is possible (Loaded with slim TCP) ORDERING INFORMATION Part Number Package µPD16721N-xxx TCP (TAB package) Remark The TCP’s external shape is customized. To order the required shape, so please contact one of our sales representatives. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14791EJ1V0DS00 (1st edition) Date Published February 2002 NS CP (K) Printed in Japan The mark ! shows major revised points. © 2000 µPD16721 ★ 1. BLOCK DIAGRAM STHR R,/L CLK STB MODE STHL VDD1 VSS1 64-bit bidirectional shift register C1 C2 C63 C64 D00 to D07 D10 to D17 D20 to D27 D30 to D37 D40 to D47 D50 to D57 POL21 POL22 Data register Latch POL VDD2 Level shifter VSS2 D/A converter V0 to V15 VSEL SRC ORC Voltage follower output Input TEST S1 S2 S3 S384 Remark /xxx indicates active low signal. 2. RELATIONSHIP BETWEEN OUTPUT CIRCUIT AND D/A CONVERTER S1 V7 Multiplexer 8-bit D/A converter 8 ····· V8 S383 8 ····· V0 S2 V15 POL 2 DataSheet S14791EJ1V0DS S384 µPD16721 3. PIN CONFIGURATION (µPD16721N-xxx) (Copper Foil Surface, Face-up) STHL D57 D56 : D51 D50 D47 D46 : D41 D40 D37 D36 : D31 D30 SRC ORC VSEL VDD1 R,/L V15 V14 V13 V12 V11 V10 V9 V8 VDD2 VSS2 V7 V6 V5 V4 V3 V2 V1 V0 VSS1 MODE TEST CLK STB POL POL22 POL21 D27 D26 : D21 D20 D17 D16 : D11 D10 D07 D06 : D01 D00 STHR S384 S383 S382 Copper Foil Surface S3 S2 S1 Remark This figure does not specify the TCP package. DataSheet S14791EJ1V0DS 3 µPD16721 4. PIN FUNCTIONS (1/2) Pin Symbol Pin Name I/O Description S1 to S384 Driver O The D/A converted 256-gray-scale analog voltage is output. D00 to D07 Port 1 display data I The display data is input with a width of 48 bits, viz., the gray scale data D10 to D17 (8 bits) by 6 dots (2 pixels). D20 to D27 DX0: LSB, DX7: MSB D30 to D37 Port 2 display data I Shift direction control I D40 to D47 D50 to D57 R,/L The shift direction control pin of shift register. The shift directions of the shift registers are as follows. R,/L = H (right shift): STHR input, S1→S384, STHL output R,/L = L (left shift) : STHL input, S384→S1, STHR output STHR Right shift start pulse I/O This is the start pulse input/output pin when connected in cascade. Loading of display data starts when a high level is read at the rising edge of CLK. At the rising edge of the 64th clock after the start pulse input, the start STHL Left shift start pulse I/O pulse output reaches the high level, thus becoming the start pulse of the next-level driver. For right shift, STHR is input and STHL is output. For left shift, STHL is input and STHR is output. CLK Shift clock I The shift clock input pin of shift register. The display data is loaded into the data register at the rising edge. If 66 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch I The contents of the data register are transferred to the latch circuit at the rising edge. In addition, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. SRC Slew-rate control I SRC = H: High-slew-rate mode (large current consumption) SRC = L: Low-slew-rate mode (small current consumption) SRC is pulled up to the VDD1 in the LSI. ORC Output resistance control I ORC = H: Low output resistance mode ORC = L: High output resistance mode ORC is pulled up to the VDD1 in the LSI. POL Polarity input I POL = L: The S2n−1 output uses V0 to V7 as the reference supply. The S2n output uses V8 to V15 as the reference supply. POL = H: The S2n−1 output uses V8 to V15 as the reference supply. The S2n output uses V0 to V7 as the reference supply. S2n−1 indicates the odd output and S2n indicates the even output. Input of the POL signal is allowed the setup time (tPOL–STB) with respect to STB’s rising edge. When it switches such as POL = H→L or L→H, all output pins are output reset during STB = H. When it does not switch, all output pins become Hi-Z during STB = H. Refer to 7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND OUTPUT WAVEFORM for details. 4 DataSheet S14791EJ1V0DS µPD16721 (2/2) Pin Symbol MODE Pin Name Output reset control I/O I Description MODE = H or open: Output reset MODE = L: No output reset MODE is pulled up to the VDD1 in the LSI. POL21, Data inversion I POL22 Select of inversion or no inversion for input data. POL21: Data inversion or no inversion of Port1. POL22: Data inversion or no inversion of Port2 POL21/22 = H: Data are inverted in the LSI. POL21/22 = L: Data are not inverted in the LSI. VSEL Driver voltage select I The driver voltage can be switched by controlling the stationary bias current of the output amplifier via VSEL. VSEL = H: VDD2 = 13.0 V (large bias current) VSEL = L or open: VDD2 = 15.0 V (small bias current) LPC is pulled down to the VSS1 in the LSI. V0 to V15 γ -corrected power supplies − Input the γ -corrected power supplies from outside by using operational amplifier. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. Make sure to maintain the following relationships. VDD2–0.2 V ≥ V0 > V1 > V2 > ....... > V6 > V7 ≥ 0.5 VDD2 + 0.5 V ★ 0.5 VDD2–0.5 V ≥ V8 > V9 > V10 > ....... V14 > V15 ≥ VSS2 + 0.2 V TEST Test I Normally, set the TEST pin to high level or leave open. This pin is pulled up to VDD1 in the LSI. ★ VDD1 Logic power supply − 2.5 to 3.4 V VDD2 Driver power supply − 13.0 ± 0.5 V or 15.0 ± 0.5 V VSS1 Logic ground − Grounding VSS2 Driver ground − Grounding Cautions 1. The power start sequence must be VDD1, logic input, and VDD2 & V0 to V15 in that order. Reverse this sequence to shut down. 2. To stabilize the supply voltage, please be sure to insert a 0.47 µF bypass capacitor between VDD1 to VSS1 and VDD2 to VSS2. Furthermore, for increased precision of the D/A converter, insertion of a bypass capacitor of about 0.1 µF is also advised between the γ-corrected power supply terminals (V0, V1, V2,....., V15) and VSS2. DataSheet S14791EJ1V0DS 5 µPD16721 5. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT VOLTAGE VALUE The µPD16721 incorporates a 8-bit D/A converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the LCD’s counter electrode voltage. The D/A converter consists of ladder resistors and switches. The ladder resistors (r0 to r253) are designed so that the ratio of LCD panel (γ -compensated voltages to V0’ to V255’ and V0” to V255” is almost equivalent as shown in Figure 5-2 and 5-3. For the 2 sets of eight γ -compensated power supplies, V0 to V7 and V8 to V15, respectively, input gray scale voltages of the same polarity with respect to the 0.5 VDD2. Figure 5-1 shows the relationship between the driving voltages such as liquid-crystal driving voltages VDD2, VSS2 and 0.5 VDD2, and γ -corrected voltages V0 to V15 and the input data. Be sure to maintain the voltage relationships below. ★ VDD2–0.2 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 ≥ 0.5 VDD2+0.5 V 0.5 VDD2–0.5 V ≥ V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 ≥ 0.5 VSS2+0.2 V Also, V6 to V7 and V8 to V9 are left open in the LSI. Be sure to input the gray scale level power supply at a constant level to the all pins, as V0 to V15. Figures 5-2 and 5-3 show the relationship between the input data and the output voltage and the resistance values of the resistor strings. Figure 5-1. Relationship between Input Data and γ -corrected Power Supplies VDD2 0.2 V V0 V1 V2 V3 V4 V5 V6 V7 0.5 V 0.5 VDD2 0.5 V V8 V9 V10 V11 V12 V13 V14 V15 0.2 V VSS2 00 01 20 40 80 C0 F0 FF Input Data (HEX) 6 DataSheet S14791EJ1V0DS µPD16721 ★ Figure 5-2. Relationship between Input Data and Output Voltage (1/4) VDD2–0.2 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 ≥ 0.5 VDD2 + 0.5 V, POL21/22 = L V255’ V0 r253 V254’ r252 V253’ r251 r244 V245’ r243 V1 V244’ r242 V243’ r241 r32 V33’ r31 V32’ V5 r30 V31’ r29 r3 V 4’ r2 V3’ r1 V2’ r0 V6 V1’ V7 V0’ Input data DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output voltage V0' V1' V2' V7 V6 V6+(V5-V6) X V3' V4' V5' V6' V7' V8' V9' V10' V11' V12' V13' V14' V15' V16' V17' V18' V19' V20' V21' V22' V23' V24' V25' V26' V27' V28' V29' V30' V31' V32' V33' V34' V35' V36' V37' V38' V39' V40' V41' V42' V43' V44' V45' V46' V47' V48' V49' V50' V51' V52' V53' V54' V55' V56' V57' V58' V59' V60' V61' V62' V63' V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V6+(V5-V6) X V5 V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X V5+(V4-V5) X DataSheet S14791EJ1V0DS 86 / 2206 172 258 344 430 514 598 680 762 842 920 998 1074 1148 1222 1294 1364 1432 1500 1566 1630 1694 1756 1816 1876 1934 1990 2046 2100 2154 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 2206 52 102 152 200 248 294 340 386 430 474 518 560 602 644 684 724 764 804 842 880 918 956 992 1028 1064 1100 1134 1168 1202 1236 1270 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 rn (Ω) r0 r1 86 86 86 86 86 84 84 82 82 80 78 78 76 74 74 72 70 68 68 66 64 64 62 60 60 58 56 56 54 54 52 52 50 50 48 48 46 46 46 44 44 44 42 42 42 40 40 40 40 38 38 38 38 36 36 36 36 34 34 34 34 34 34 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 r26 r27 r28 r29 r30 r31 r32 r33 r34 r35 r36 r37 r38 r39 r40 r41 r42 r43 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 r54 r55 r56 r57 r58 r59 r60 r61 r62 7 µPD16721 ★ Figure 5-2. Relationship between Input Data and Output Voltage (2/4) VDD2–0.2 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 ≥ 0.5 VDD2 + 0.5 V, POL21/22 = L V255’ V0 r253 V254’ r252 V253’ r251 r244 V245’ r243 V1 V244’ r242 V243’ r241 r32 V33’ r31 V32’ V5 r30 V31’ r29 r3 V4’ r2 V3’ r1 V2’ r0 V6 V1’ V7 V0’ 8 Input data 40H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 1 0 0 0 0 0 0 41H 0 1 0 0 0 0 0 1 42H 43H 44H 45H 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 46H 47H 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 1 48H 49H 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 1 4AH 0 1 0 0 1 0 1 0 4BH 4CH 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 0 4DH 4EH 0 0 1 1 0 0 0 0 1 1 1 1 0 1 1 0 4FH 50H 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 51H 52H 53H 54H 55H 56H 57H 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output voltage V64' V65' V66' V67' V68' V69' V70' V71' V72' V73' V74' V75' V76' V77' V78' V79' V80' V81' V82' V83' V84' V85' V86' V87' V88' V89' V90' V91' V92' V93' V94' V95' V96' V97' V98' V99' V100' V101' V102' V103' V104' V105' V106' V107' V108' V109' V110' V111' V112' V113' V114' V115' V116' V117' V118' V119' V120' V121' V122' V123' V124' V125' V126' V127' DataSheet S14791EJ1V0DS V4 rn (Ω) r63 32 32 32 32 32 32 32 30 30 30 30 30 30 30 30 30 30 28 28 28 28 28 28 28 28 28 28 28 28 28 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 V4+(V3-V4) X 32 / 1772 r64 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 64 96 128 160 / / / / 1772 1772 1772 1772 r65 r66 r67 r68 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 192 224 254 284 314 / / / / / 1772 1772 1772 1772 1772 r69 r70 r71 r72 r73 V4+(V3-V4) X V4+(V3-V4) X 344 374 / / 1772 1772 r74 r75 V4+(V3-V4) X V4+(V3-V4) X 404 434 / / 1772 1772 r76 r77 V4+(V3-V4) X V4+(V3-V4) X 464 494 / / 1772 1772 r78 r79 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 524 552 580 / / / 1772 1772 1772 r80 r81 r82 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 608 636 664 692 720 748 / / / / / / 1772 1772 1772 1772 1772 1772 r83 r84 r85 r86 r87 r88 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 776 804 832 860 888 / / / / / 1772 1772 1772 1772 1772 r89 r90 r91 r92 r93 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 914 940 966 992 1018 / / / / / 1772 1772 1772 1772 1772 r94 r95 r96 r97 r98 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 1044 1070 1096 1122 1148 / / / / / 1772 1772 1772 1772 1772 r99 r100 r101 r102 r103 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 1174 1200 1226 1252 1278 / / / / / 1772 1772 1772 1772 1772 r104 r105 r106 r107 r108 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 1304 1330 1356 1382 / / / / 1772 1772 1772 1772 r109 r110 r111 r112 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 1408 1434 1460 1486 1512 / / / / / 1772 1772 1772 1772 1772 r113 r114 r115 r116 r117 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 1538 1564 1590 1616 1642 / / / / / 1772 1772 1772 1772 1772 r118 r119 r120 r121 r122 V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X V4+(V3-V4) X 1668 1694 1720 1746 / / / / 1772 1772 1772 1772 r123 r124 r125 r126 µPD16721 ★ Figure 5-2. Relationship between Input Data and Output Voltage (3/4) VDD2–0.2 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 ≥ 0.5 VDD2 + 0.5 V, POL21/22 = L V255’ V0 r253 V254’ r252 V253’ r251 r244 V245’ r243 V1 V244’ r242 V243’ r241 r32 V33’ r31 V32’ V5 r30 V31’ r29 r3 V4 ’ r2 V3’ r1 V2’ r0 V6 V1’ V7 V0’ Input data 80H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 0 0 0 0 0 0 0 81H 1 0 0 0 0 0 0 1 82H 83H 84H 85H 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 86H 87H 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 88H 89H 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 8AH 1 0 0 0 1 0 1 0 8BH 8CH 1 1 0 0 0 0 0 0 1 1 0 1 1 0 1 0 8DH 8EH 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 0 8FH 90H 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 91H 92H 93H 94H 95H 96H 97H 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output voltage V128' V129' V130' V131' V132' V133' V134' V135' V136' V137' V138' V139' V140' V141' V142' V143' V144' V145' V146' V147' V148' V149' V150' V151' V152' V153' V154' V155' V156' V157' V158' V159' V160' V161' V162' V163' V164' V165' V166' V167' V168' V169' V170' V171' V172' V173' V174' V175' V176' V177' V178' V179' V180' V181' V182' V183' V184' V185' V186' V187' V188' V189' V190' V191' DataSheet S14791EJ1V0DS V3 rn (Ω) r127 26 24 26 24 24 24 24 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 28 28 28 28 28 28 28 28 28 28 28 28 28 28 30 30 30 30 30 30 30 V3+(V2-V3) X 26 / 1710 r128 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 50 76 100 124 / / / / 1710 1710 1710 1710 r129 r130 r131 r132 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 148 172 198 224 250 / / / / / 1710 1710 1710 1710 1710 r133 r134 r135 r136 r137 V3+(V2-V3) X V3+(V2-V3) X 276 302 / / 1710 1710 r138 r139 V3+(V2-V3) X V3+(V2-V3) X 328 354 / / 1710 1710 r140 r141 V3+(V2-V3) X V3+(V2-V3) X 380 406 / / 1710 1710 r142 r143 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 432 458 484 / / / 1710 1710 1710 r144 r145 r146 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 510 536 562 588 614 640 / / / / / / 1710 1710 1710 1710 1710 1710 r147 r148 r149 r150 r151 r152 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 666 692 718 744 770 / / / / / 1710 1710 1710 1710 1710 r153 r154 r155 r156 r157 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 796 822 848 874 900 / / / / / 1710 1710 1710 1710 1710 r158 r159 r160 r161 r162 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 926 952 978 1004 1030 / / / / / 1710 1710 1710 1710 1710 r163 r164 r165 r166 r167 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 1056 1082 1108 1136 1164 / / / / / 1710 1710 1710 1710 1710 r168 r169 r170 r171 r172 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 1192 1220 1248 1276 / / / / 1710 1710 1710 1710 r173 r174 r175 r176 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 1304 1332 1360 1388 1416 / / / / / 1710 1710 1710 1710 1710 r177 r178 r179 r180 r181 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 1444 1472 1500 1530 1560 / / / / / 1710 1710 1710 1710 1710 r182 r183 r184 r185 r186 V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X V3+(V2-V3) X 1590 1620 1650 1680 / / / / 1710 1710 1710 1710 r187 r188 r189 r190 9 µPD16721 ★ Figure 5-2. Relationship between Input Data and Output Voltage (4/4) VDD2–0.2 V ≥ V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 ≥ 0.5 VDD2 + 0.5 V, POL21/22 = L V255’ V0 r253 V254’ r252 V253’ r251 r244 V245’ r243 V1 V244’ r242 V243’ r241 r32 V33’ r31 V32’ V5 r30 V31’ r29 r3 V4’ r2 V3’ r1 V2’ r0 V6 V1’ V7 V0’ 10 Input data C0H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 0 0 0 0 0 0 C1H 1 1 0 0 0 0 0 1 C2H C3H C4H C5H 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 C6H C7H 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 C8H C9H 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 CAH 1 1 0 0 1 0 1 0 CBH CCH 1 1 1 1 0 0 0 0 1 1 0 1 1 0 1 0 CDH CEH 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 CFH D0H 1 1 1 1 0 0 0 1 1 0 1 0 1 0 1 0 D1H D2H D3H D4H D5H D6H D7H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 D8H D9H DAH DBH DCH DDH DEH DFH E0H E1H E2H E3H E4H E5H E6H E7H E8H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 E9H EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output voltage V192' V193' V194' V195' V196' V197' V198' V199' V200' V201' V202' V203' V204' V205' V206' V207' V208' V209' V210' V211' V212' V213' V214' V215' V216' V217' V218' V219' V220' V221' V222' V223' V224' V225' V226' V227' V228' V229' V230' V231' V232' V233' V234' V235' V236' V237' V238' V239' V240' V241' V242' V243' V244' V245' V246' V247' V248' V249' V250' V251' V252' V253' V254' V255' DataSheet S14791EJ1V0DS V2 rn (Ω) r191 30 30 30 32 32 32 32 32 32 32 34 34 34 34 34 34 36 36 36 36 36 38 38 38 38 40 40 40 42 42 42 44 44 44 46 46 48 48 50 50 52 52 54 56 56 58 60 62 64 66 68 70 72 76 80 82 86 92 98 104 112 120 132 V2+(V1-V2) X 30 / 1966 r192 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 60 90 122 154 / / / / 1966 1966 1966 1966 r193 r194 r195 r196 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 186 218 250 282 314 / / / / / 1966 1966 1966 1966 1966 r197 r198 r199 r200 r201 V2+(V1-V2) X V2+(V1-V2) X 348 382 / / 1966 1966 r202 r203 V2+(V1-V2) X V2+(V1-V2) X 416 450 / / 1966 1966 r204 r205 V2+(V1-V2) X V2+(V1-V2) X 484 518 / / 1966 1966 r206 r207 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 554 590 626 / / / 1966 1966 1966 r208 r209 r210 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 662 698 736 774 812 850 / / / / / / 1966 1966 1966 1966 1966 1966 r211 r212 r213 r214 r215 r216 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 890 930 970 1012 1054 / / / / / 1966 1966 1966 1966 1966 r217 r218 r219 r220 r221 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 1096 1140 1184 1228 1274 / / / / / 1966 1966 1966 1966 1966 r222 r223 r224 r225 r226 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 1320 1368 1416 1466 1516 / / / / / 1966 1966 1966 1966 1966 r227 r228 r229 r230 r231 V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X V2+(V1-V2) X 1568 1620 1674 1730 1786 / / / / / 1966 1966 1966 1966 1966 r232 r233 r234 r235 r236 V2+(V1-V2) X V2+(V1-V2) X V1 V1+(V0-V1) X 1844 1904 / / 1966 1966 64 / 1322 r237 r238 r239 r240 V1+(V0-V1) X V1+(V0-V1) X V1+(V0-V1) X V1+(V0-V1) X V1+(V0-V1) X 130 198 268 340 416 / / / / / 1322 1322 1322 1322 1322 r241 r242 r243 r244 r245 V1+(V0-V1) X V1+(V0-V1) X V1+(V0-V1) X V1+(V0-V1) X V1+(V0-V1) X 496 578 664 756 854 / / / / / 1322 1322 1322 1322 1322 r246 r247 r248 r249 r250 V1+(V0-V1) X V1+(V0-V1) X V1+(V0-V1) X V0 958 1070 1190 / / / 1322 1322 1322 r251 r252 r253 TOTAL 10280 µPD16721 ★ Figure 5-3. Relationship between Input Data and Output Voltage (1/4) 0.5 VDD2−0.5 V ≥ V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 ≥ VSS2+0.2 V, POL21/22 = L Input data 00H 01H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 V0" V1" V8 02H 03H 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 V10+(V9-V10) X V10+(V9-V10) X 2120 2034 / / 2206 2206 r1 r2 V2’’ 04H 05H 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 V10+(V9-V10) X V10+(V9-V10) X 1948 1862 / / 2206 2206 r3 r4 V3’’ 06H 07H 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 V2" V3" V4" V5" V6" V10+(V9-V10) X V10+(V9-V10) X 1776 1692 / / 2206 2206 r5 r6 V4’’ 08H 09H 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0AH 0BH 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1608 1526 1444 / / / 2206 2206 2206 r7 r8 r9 V5’’ 0CH 0DH 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 V10+(V9-V10) X V9" V10+(V9-V10) X V10" V10+(V9-V10) X V11" V10+(V9-V10) X V12" V10+(V9-V10) X 1364 1286 / / 2206 2206 r10 r11 0EH 0FH 10H 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 1 0 0 1 0 V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X 1208 1132 1058 984 / / / / 2206 2206 2206 2206 r12 r13 r14 r15 V32’’ 11H 12H 13H 14H 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 V33’’ 15H 16H 0 0 0 0 0 0 1 1 0 0 1 1 0 1 1 0 17H 18H 0 0 0 0 0 0 1 1 0 1 1 0 1 0 1 0 V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X 912 842 774 706 640 576 512 450 / / / / / / / / 2206 2206 2206 2206 2206 2206 2206 2206 r16 r17 r18 r19 r20 r21 r22 r23 19H 1AH 1BH 1CH 1DH 1EH 1FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 V13" V14" V15" V16" V17" V18" V19" V20" V21" V22" V23" V24" V25" V26" V27" V28" V10+(V9-V10) X V10+(V9-V10) X 390 330 / / 2206 2206 r24 r25 V10+(V9-V10) X 272 / 2206 r26 216 160 106 52 / / / / 2206 2206 2206 2206 20H 21H 22H 23H 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10+(V9-V10) X V10 V11+(V10-V11) X V11+(V10-V11) X 1252 1202 / / 1304 1304 r27 r28 r29 r30 r31 r32 r33 V11+(V10-V11) X 1152 / 1304 r34 24H 25H 26H 27H 28H 29H 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1104 1056 1010 964 918 874 / / / / / / 1304 1304 1304 1304 1304 1304 r35 r36 r37 r38 r39 r40 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V11+(V10-V11) X V11+(V10-V11) X V11+(V10-V11) X V39" V11+(V10-V11) X V40" V11+(V10-V11) X V41" V11+(V10-V11) X V42" V11+(V10-V11) X V43" V11+(V10-V11) X V44" V11+(V10-V11) X V45" V11+(V10-V11) X V46" V11+(V10-V11) X V47" V11+(V10-V11) X V48" V11+(V10-V11) X V49" V11+(V10-V11) X V50" V11+(V10-V11) X V51" V11+(V10-V11) X V52" V11+(V10-V11) X V53" V11+(V10-V11) X V54" V11+(V10-V11) X V55" V11+(V10-V11) X V56" V11+(V10-V11) X V57" V11+(V10-V11) X V58" V11+(V10-V11) X V59" V11+(V10-V11) X V60" V11+(V10-V11) X V61" V11+(V10-V11) X 830 786 744 / / / 1304 1304 1304 r41 r42 r43 702 660 620 580 540 500 462 424 386 348 / / / / / / / / / / 1304 1304 1304 1304 1304 1304 1304 1304 1304 1304 r44 r45 r46 r47 r48 r49 r50 r51 r52 r53 312 276 240 204 170 136 102 / / / / / / / 1304 1304 1304 1304 1304 1304 1304 r54 r55 r56 r57 r58 r59 r60 V62" V11+(V10-V11) X V63" V11+(V10-V11) X 68 34 / / 1304 1304 r61 r62 V8 V0’’ V9 V1’’ r0 r1 r2 r3 r4 r29 V31’’ r30 V10 r31 r32 r241 V243’’ r242 V244’’ V14 r243 V245’’ r244 r252 V254’’ V15 r253 V255’’ Output voltage V7" V8" V29" V30" V31" V32" V33" V34" V35" V36" V37" V38" V9 DataSheet S14791EJ1V0DS rn (Ω) r0 86 86 86 86 86 84 84 82 82 80 78 78 76 74 74 72 70 68 68 66 64 64 62 60 60 58 56 56 54 54 52 52 50 50 48 48 46 46 46 44 44 44 42 42 42 40 40 40 40 38 38 38 38 36 36 36 36 34 34 34 34 34 34 11 µPD16721 ★ Figure 5-3. Relationship between Input Data and Output Voltage (2/4) 0.5 VDD2−0.5 V ≥ V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 ≥ VSS2+0.2 V, POL21/22 = L Input data 40H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 0 1 0 0 0 0 0 0 41H 0 1 0 0 0 0 0 1 42H 43H 44H 45H 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 V3’’ 46H 47H 0 0 1 1 0 0 0 0 0 0 1 1 1 1 0 1 V4’’ 48H 49H 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 1 V5’’ 4AH 0 1 0 0 1 0 1 0 4BH 4CH 0 0 1 1 0 0 0 0 1 1 0 1 1 0 1 0 4DH 4EH 0 0 1 1 0 0 0 0 1 1 1 1 0 1 1 0 4FH 50H 0 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 51H 52H 53H 54H 55H 56H 57H 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 58H 59H 5AH 5BH 5CH 5DH 5EH 5FH 60H 61H 62H 63H 64H 65H 66H 67H 68H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 69H 6AH 6BH 6CH 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7CH 7DH 7EH 7FH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0’’ V8 V9 V1’’ r0 V2’’ r1 r2 r3 r4 r29 V31’’ r30 V32’’ V10 r31 V33’’ r32 r241 V243’’ r242 V244’’ V14 r243 V245’’ r244 r252 V254’’ V15 r253 V255’’ 12 Output voltage V64" V65" V66" V67" V68" V69" V70" V71" V72" V73" V74" V75" V76" V77" V78" V79" V80" V81" V82" V83" V84" V85" V86" V87" V88" V89" V90" V91" V92" V93" V94" V95" V96" V97" V98" V99" V100" V101" V102" V103" V104" V105" V106" V107" V108" V109" V110" V111" V112" V113" V114" V115" V116" V117" V118" V119" V120" V121" V122" V123" V124" V125" V126" V127" V11 rn (Ω) r63 32 32 32 32 32 32 32 30 30 30 30 30 30 30 30 30 30 28 28 28 28 28 28 28 28 28 28 28 28 28 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 V12+(V11-V12) X 1740 / 1772 r64 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 1708 1676 1644 1612 / / / / 1772 1772 1772 1772 r65 r66 r67 r68 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 1580 1548 1518 1488 1458 / / / / / 1772 1772 1772 1772 1772 r69 r70 r71 r72 r73 V12+(V11-V12) X V12+(V11-V12) X 1428 / 1398 / 1772 1772 r74 r75 V12+(V11-V12) X V12+(V11-V12) X 1368 / 1338 / 1772 1772 r76 r77 V12+(V11-V12) X V12+(V11-V12) X 1308 / 1278 / 1772 1772 r78 r79 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 1248 / 1220 / 1192 / 1772 1772 1772 r80 r81 r82 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 1164 1136 1108 1080 1052 1024 / / / / / / 1772 1772 1772 1772 1772 1772 r83 r84 r85 r86 r87 r88 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 996 968 940 912 884 / / / / / 1772 1772 1772 1772 1772 r89 r90 r91 r92 r93 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 858 832 806 780 754 / / / / / 1772 1772 1772 1772 1772 r94 r95 r96 r97 r98 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 728 702 676 650 624 / / / / / 1772 1772 1772 1772 1772 r99 r100 r101 r102 r103 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 598 572 546 520 494 / / / / / 1772 1772 1772 1772 1772 r104 r105 r106 r107 r108 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 468 442 416 390 / / / / 1772 1772 1772 1772 r109 r110 r111 r112 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 364 338 312 286 260 / / / / / 1772 1772 1772 1772 1772 r113 r114 r115 r116 r117 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 234 208 182 156 130 / / / / / 1772 1772 1772 1772 1772 r118 r119 r120 r121 r122 V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X V12+(V11-V12) X 104 78 52 26 / / / / 1772 1772 1772 1772 r123 r124 r125 r126 DataSheet S14791EJ1V0DS µPD16721 ★ Figure 5-3. Relationship between Input Data and Output Voltage (3/4) 0.5 VDD2−0.5 V ≥ V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 ≥ VSS2+0.2 V, POL21/22 = L Input data 80H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 0 0 0 0 0 0 0 81H 1 0 0 0 0 0 0 1 82H 83H 84H 85H 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 1 0 1 V3’’ 86H 87H 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 1 V4’’ 88H 89H 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 1 8AH 1 0 0 0 1 0 1 0 8BH 8CH 1 1 0 0 0 0 0 0 1 1 0 1 1 0 1 0 8DH 8EH 1 1 0 0 0 0 0 0 1 1 1 1 0 1 1 0 8FH 90H 1 1 0 0 0 0 0 1 1 0 1 0 1 0 1 0 91H 92H 93H 94H 95H 96H 97H 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 98H 99H 9AH 9BH 9CH 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H A8H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A9H AAH ABH ACH ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0’’ V8 V9 V1’’ r0 V2’’ r1 r2 r3 V5’’ r4 r29 V31’’ r30 V32’’ V10 r31 V33’’ r32 r241 V243’’ r242 V244’’ V14 r243 V245’’ r244 r252 V254’’ V15 r253 V255’’ Output voltage V128" V129" V130" V131" V132" V133" V134" V135" V136" V137" V138" V139" V140" V141" V142" V143" V144" V145" V146" V147" V148" V149" V150" V151" V152" V153" V154" V155" V156" V157" V158" V159" V160" V161" V162" V163" V164" V165" V166" V167" V168" V169" V170" V171" V172" V173" V174" V175" V176" V177" V178" V179" V180" V181" V182" V183" V184" V185" V186" V187" V188" V189" V190" V191" V12 rn (Ω) r127 26 24 26 24 24 24 24 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 26 28 28 28 28 28 28 28 28 28 28 28 28 28 28 30 30 30 30 30 30 30 V13+(V12-V13) X 1684 / 1710 r128 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 1660 1634 1610 1586 / / / / 1710 1710 1710 1710 r129 r130 r131 r132 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 1562 1538 1512 1486 1460 / / / / / 1710 1710 1710 1710 1710 r133 r134 r135 r136 r137 V13+(V12-V13) X V13+(V12-V13) X 1434 1408 / / 1710 1710 r138 r139 V13+(V12-V13) X V13+(V12-V13) X 1382 1356 / / 1710 1710 r140 r141 V13+(V12-V13) X V13+(V12-V13) X 1330 1304 / / 1710 1710 r142 r143 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 1278 1252 1226 / / / 1710 1710 1710 r144 r145 r146 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 1200 1174 1148 1122 1096 1070 / / / / / / 1710 1710 1710 1710 1710 1710 r147 r148 r149 r150 r151 r152 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 1044 1018 992 966 940 / / / / / 1710 1710 1710 1710 1710 r153 r154 r155 r156 r157 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 914 888 862 836 810 / / / / / 1710 1710 1710 1710 1710 r158 r159 r160 r161 r162 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 784 758 732 706 680 / / / / / 1710 1710 1710 1710 1710 r163 r164 r165 r166 r167 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 654 628 602 574 546 / / / / / 1710 1710 1710 1710 1710 r168 r169 r170 r171 r172 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 518 490 462 434 / / / / 1710 1710 1710 1710 r173 r174 r175 r176 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 406 378 350 322 294 / / / / / 1710 1710 1710 1710 1710 r177 r178 r179 r180 r181 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 266 238 210 180 150 / / / / / 1710 1710 1710 1710 1710 r182 r183 r184 r185 r186 V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X V13+(V12-V13) X 120 90 60 30 / / / / 1710 1710 1710 1710 r187 r188 r189 r190 DataSheet S14791EJ1V0DS 13 µPD16721 ★ Figure 5-3. Relationship between Input Data and Output Voltage (4/4) 0.5 VDD2−0.5 V ≥ V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 ≥ VSS2+0.2 V, POL21/22 = L Input data C0H DX7 DX6 DX5 DX4 DX3 DX2 DX1 DX0 1 1 0 0 0 0 0 0 C1H 1 1 0 0 0 0 0 1 V1’’ C2H C3H 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 1 V2’’ C4H C5H 1 1 1 1 0 0 0 0 0 0 1 1 0 0 0 1 V3’’ C6H C7H 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 1 C8H C9H 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 1 CAH CBH 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 CCH CDH 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 CEH CFH D0H 1 1 1 1 1 1 0 0 0 0 0 1 1 1 0 1 1 0 1 1 0 0 1 0 D1H D2H D3H D4H 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 D5H D6H 1 1 1 1 0 0 1 1 0 0 1 1 0 1 1 0 D7H D8H 1 1 1 1 0 0 1 1 0 1 1 0 1 0 1 0 D9H DAH DBH DCH DDH DEH DFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 E0H E1H E2H E3H 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 E4H E5H E6H E7H E8H E9H 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 EAH EBH ECH EDH EEH EFH F0H F1H F2H F3H F4H F5H F6H F7H F8H F9H FAH FBH FCH FDH FEH FFH 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0’’ V8 V9 r0 r1 r2 V4’’ r3 V5’’ r4 r29 V31’’ r30 V32’’ V10 r31 V33’’ r32 r241 V243’’ r242 V244’’ V14 r243 V245’’ r244 r252 V254’’ V15 r253 V255’’ 14 Output voltage rn (Ω) r191 30 30 30 32 32 32 32 32 32 32 34 34 34 34 34 34 36 36 36 36 36 38 38 38 38 40 40 40 42 42 42 44 44 44 46 46 48 48 50 50 52 52 54 56 56 58 60 62 64 66 68 70 72 76 80 82 86 92 98 104 112 120 132 V192" V193" V13 V14+(V13-V14) X 1936 / 1966 r192 V194" V195" V196" V197" V198" V14+(V13-V14) X V14+(V13-V14) X 1906 1876 / / 1966 1966 r193 r194 V14+(V13-V14) X V14+(V13-V14) X 1844 1812 / / 1966 1966 r195 r196 V14+(V13-V14) X V14+(V13-V14) X 1780 1748 / / 1966 1966 r197 r198 V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X 1716 1684 1652 / / / 1966 1966 1966 r199 r200 r201 V14+(V13-V14) X V14+(V13-V14) X 1618 1584 / / 1966 1966 r202 r203 V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X 1550 1516 1482 1448 / / / / 1966 1966 1966 1966 r204 r205 r206 r207 V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X 1412 1376 1340 1304 1268 1230 1192 1154 / / / / / / / / 1966 1966 1966 1966 1966 1966 1966 1966 r208 r209 r210 r211 r212 r213 r214 r215 V14+(V13-V14) X V14+(V13-V14) X 1116 1076 / / 1966 1966 r216 r217 V14+(V13-V14) X 1036 / 1966 r218 V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X 996 954 912 870 826 782 738 / / / / / / / 1966 1966 1966 1966 1966 1966 1966 r219 r220 r221 r222 r223 r224 r225 V14+(V13-V14) X 692 / 1966 r226 V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X 646 598 550 500 450 398 / / / / / / 1966 1966 1966 1966 1966 1966 r227 r228 r229 r230 r231 r232 V234" V235" V236" V237" V238" V239" V240" V241" V242" V243" V244" V245" V246" V247" V248" V249" V250" V251" V252" V253" V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X 346 292 236 / / / 1966 1966 1966 r233 r234 r235 V14+(V13-V14) X V14+(V13-V14) X V14+(V13-V14) X V14 V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X 180 122 62 / / / 1966 1966 1966 1258 1192 1124 1054 982 906 / / / / / / 1322 1322 1322 1322 1322 1322 r236 r237 r238 r239 r240 r241 r242 r243 r244 r245 V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X V15+(V14-V15) X 826 744 658 566 468 364 252 / / / / / / / 1322 1322 1322 1322 1322 1322 1322 r246 r247 r248 r249 r250 r251 r252 V254" V255" V15+(V14-V15) X V15 132 / 1322 r253 TOTAL V199" V200" V201" V202" V203" V204" V205" V206" V207" V208" V209" V210" V211" V212" V213" V214" V215" V216" V217" V218" V219" V220" V221" V222" V223" V224" V225" V226" V227" V228" V229" V230" V231" V232" V233" DataSheet S14791EJ1V0DS 10280 µPD16721 6. RELATIONSHIP BETWEEN INPUT DATA AND OUTPUT PIN Data format: 8 bits x 2 RGBs (6 dots) Input width: 48 bits (2-pixel data) (1) R,/L = H (Right shift) Output S1 S2 S3 S4 … S383 S384 Data D00 to D07 D10 to D17 D20 to D27 D30 to D37 … D40 to D47 D50 to D57 (2) R,/L = L (Left shift) Output S1 S2 S3 S4 … S383 S384 Data D00 to D07 D10 to D17 D20 to D27 D30 to D37 … D40 to D47 D50 to D57 POL S2n–1 Note Note S2n L V0 to V7 V8 to V15 H V8 to V15 V0 to V7 Note S2n–1 (Odd output), S2n (Even output), n = 1, 2, ..., 192. DataSheet S14791EJ1V0DS 15 µPD16721 7. RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND OUTPUT WAVEFORM When the MODE pin is high level or left open and STB is high level, all outputs are reset (shorted) and the grayscale voltage is output to LCD in synchronization with the falling edge of STB. When the MODE pin is low level and STB is high level, all outputs became Hi-Z and the gray-scale voltage is output to the LCD in synchronization with the falling edge of STB. Also, setting the SRC pin to high level allows the bias current value of the output amplifier to rise temporarily, and setting the ORC pin to high level allows the output resistance value of the amplifier to lower temporarily. For the timing and the processing of STB, SRC, or ORC during a high-level period, We recommend a thorough evaluation of the LCD panel specifications in advance. (1) When MODE is high level or left open STB High-slew-rate period SRC Low-slew-rate period ORC High output resistance period Low output resistance period POL S2n–1 Voltage selected form V0 to V7 ★ Voltage selected form V0 to V7 Voltage selected form V8 to V15 S2n Voltage selected form V8 to V15 Hi-Z 16 Voltage selected form V8 to V15 Voltage selected form V0 to V7 Hi-Z DataSheet S14791EJ1V0DS Hi-Z µPD16721 (2) When MODE is low level STB High-slew-rate period SRC Low-slew-rate period ORC High output resistance period Low output resistance period POL S2n–1 Voltage selected form V0 to V7 ★ Voltage selected form V8 to V15 Voltage selected form V0 to V7 S2n Voltage selected form V8 to V15 Hi-Z Voltage selected form V0 to V7 Hi-Z DataSheet S14791EJ1V0DS Voltage selected form V8 to V15 Hi-Z 17 µPD16721 8. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (TA = 25°°C, VSS1 = VSS2 = 0 V) Parameter Symbol Ratings Unit –0.5 to +4.0 V Logic part supply voltage VDD1 Driver part supply voltage VDD2 –0.5 to +17.0 V Logic part input voltage VI1 –0.5 to VDD1 + 0.5 V Driver part input voltage VI2 –0.5 to VDD2 + 0.5 V Logic part output voltage VO1 –0.5 to VDD1 + 0.5 V Driver part output voltage VO2 –0.5 to VDD2 + 0.5 V Operating ambient temperature TA –10 to +75 °C Storage temperature Tstg –55 to +125 °C Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Recommended Operating Range (TA = –10 to +75°C, VSS1 = VSS2 = 0 V) Parameter Symbol ★ Logic part supply voltage VDD1 ★ Driver part supply voltage VDD2 High-level input voltage VIH Low-level input voltage VIL ★ γ -corrected voltage Driver part output voltage ★ Clock frequency 18 Condition MIN. TYP. 2.5 MAX. Unit 3.4 V V VSEL = H 12.5 13.0 13.5 VSEL = L or open 14.5 15.0 15.5 0.7 VDD1 VDD1 V 0 0.3 VDD1 V V0 to V7 0.5 VDD2+0.5 VDD2−0.2 V V8 to V15 0.2 0.5 VDD2−0.5 V 0.2 VDD2−0.2 V 2.5 V ≤ VDD1 ≤ 3.0 V 55 MHz 3.0 V ≤ VDD1 ≤ 3.4 V 70 MHz VO fCLK DataSheet S14791EJ1V0DS µPD16721 ★ Electrical Characteristics (TA = –10 to +75°C, VDD1 = 2.5 to 3.4 V, VDD2 = 12.5 to 15.5 V, VSS1 = VSS2 = 0 V) Parameter ★ Symbol Condition MIN. Input leakage current IIL High-level output voltage VOH STHR (STHL), IOH = 0 mA Low-level output voltage VOL STHR (STHL), IOL = 0 mA γ -corrected power supply static Iγ VDD2 = 15.0 V V0, V8 340 V0 to V7 = V8 to V15 = V7, V15 −1020 current consumption TYP. MAX. Unit ±1.0 µA VDD1−0.1 V 0.1 V 681 1020 mA −681 −340 mA −0.40 mA ±10 ±20 mV ±5 ±10 mV ±7 ±15 mV ±10 ±20 mV 7.0 V ★ ★ Driver output current Output voltage deviation IVOH VX = 12 V, VOUT = 11 V IVOL VX = 1 V, VOUT = 2 V ∆VO TA = 25°C Note Note 0.65 mA VSS2 + 1.0 V to VDD2 − 1.0 V ★ Output swing voltage difference ∆VP-P1 deviation ∆VP-P2 VDD1 = 3.3 V VOUT = VDD2 = 15.0 V 7.0 to 8.0 V TA = 25°C VOUT = Note 4.0 to 11.0 V ∆VP-P3 VOUT = 1.0 to 14.0 V ★ Logic part dynamic current Note Note IDD1 VDD1 1.3 10 mA IDD2 VDD2, with no load 12 30 mA consumption ★ Driver part dynamic current consumption Note VX refers to the output voltage of analog output pins S1 to S384. VOUT refers to the voltage applied to analog output pins S1 to S384. Cautions 1. fSTB = 64 kHz, fCLK = 54 MHz 2. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 3. Refers to the current consumption per driver when cascades are connected under the assumption of SXGA single-sided mounting (10 units). DataSheet S14791EJ1V0DS 19 µPD16721 ★ Switching Characteristics (TA = −10 to +75°°C, VDD1 = 2.5 to 3.4 V, VDD2 = 12.5 to 15.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Start pulse delay time ★ tPLH1 Driver output delay time tPLH2 tPLH3 tPHL2 tPHL3 Input capacitance Condition MIN. TYP. CL = 15 pF Note Unit 12 ns 5 µs 10 µs 5 µs 10 µs 5 10 pF 10 15 pF CL = 100 pF, RL = 10 kΩ Note Note Note CI1 MAX. logic input, except STHR (STHL), TA = 25°C CI2 STHR (STHL), TA = 25°C Note tPLH2, tPHL2 refer to the arrival time from falling edge of STB to target voltage ±10% tPLH3, tPHL3 refer to the arrival time from falling edge of STB to target voltage ±0.02 V (condition: VO = 3.0 V ↔12.0 V) ★ Test Condition The measurement point RL2 RL1 RL3 RL4 RL5 RLn = 2 kΩ Output CLn = 20 pF CL1 20 CL2 CL3 CL4 DataSheet S14791EJ1V0DS CL5 µPD16721 ★ Timing Requirements (TA = −10 to +75°C, VDD1 = 2.5 to 3.4 V, VSS1 = 0 V, tr = tf = 5.0 ns) Parameter ★ Clock pulse width ★ Clock pulse high period Clock pulse low period Symbol Condition MIN. 2.5 V ≤ VDD1 ≤ 3.0 V 18 3.0 V ≤ VDD1 ≤ 3.4 V 14 PW CLK (H) 2.5 V ≤ VDD1 ≤ 3.0 V 6 3.0 V ≤ VDD1 ≤ 3.4 V 4 PW CLK TYP. MAX. Unit ns ns PW CLK (L) 4 ns Data setup time tSETUP1 0 ns Data hold time tHOLD1 4 ns Start pulse setup time tSETUP2 0 ns Start pulse hold time tHOLD2 4 ns POL21/22 setup time tSETUP3 0 ns POL21/22 hold time tHOLD3 4 ns PW STB 1.0 µs ★ STB pulse width Last data timing tLDT 2 CLK CLK-STB time tCLK-STB CLK ↑→ STB↑ 4 ns STB-CLK time tSTB-CLK STB ↑→ CLK↑ 4 ns Time between STB and start pulse tSTB-STH STB ↑→ STHR (STHL) ↑ 2 CLK POL-STB time tPOL-STB POL ↑ or ↓→ STB ↑ 4 ns STB-POL time tSTB-POL STB ↓→ POL ↓ or ↑ 4 ns STB-SRC time t STB-SRC STB ↑ → SRC ↑ 0 ns STB-ORC time tSTB-ORC STB ↓→ ORC ↑ 0 ns ★ Remark Unless otherwise specified, the input level is defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1. DataSheet S14791EJ1V0DS 21 64 65 66 641 tCLK-STB tHOLD2 VDD1 90 % 642 10 % tSTB-CLK VSS1 VDD1 STHR (1st Dr.) VSS1 tSETUP1 Dn0 to Dn7 tf INVALID D1 to D6 tHOLD1 D7 to D12 tSETUP3 tSTB-STH D373 to D378 D379 to D384 D385 to D390 VDD1 D3835 to D3840 INVALID D1 to D6 D7 to D12 VSS1 tHOLD3 VDD1 POL21/22 INVALID INVALID VSS1 tPLH1 DataSheet S14791EJ1V0DS VDD1 STHL (1st Dr.) VSS1 tLDT PWSTB VDD1 STB VSS1 tSTB-SRC tSTB-ORC VDD1 SRC, ORC VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 tPLH2 Sn (Vx) µPD16721 tPHL2 tPHL3 Switching Characteristic Waveform 3 tr 2 ★ (1) R,/L= H, MODE = H or open tSETUP2 2 1 Unless otherwise specified, VIH, VIL are defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1 (Numbers clock and display data 1 CLK PWCLK(H) are example when in SXGA). 22 PWCLK(L) PWCLK 3 64 65 66 641 tCLK-STB 10 % tSTB-CLK VSS1 VDD1 STHR (1st Dr.) VSS1 tSETUP1 Dn0 to Dn7 tf VDD1 90 % 642 tHOLD2 tr 2 INVALID D1 to D6 tHOLD1 D7 to D12 tSETUP3 tSTB-STH D373 to D378 D379 to D384 D385 to D390 VDD1 D3835 to D3840 INVALID D1 to D6 D7 to D12 VSS1 tHOLD3 VDD1 POL21/22 INVALID INVALID VSS1 tPLH1 DataSheet S14791EJ1V0DS VDD1 STHL (1st Dr.) VSS1 tLDT PWSTB VDD1 STB VSS1 tSTB-SRC tSTB-ORC VDD1 SRC, ORC VSS1 tPOL-STB tSTB-POL VDD1 POL VSS1 tPLH3 Hi-Z tPLH2 Sn (Vx) tPHL3 23 µPD16721 tPHL2 Unless otherwise specified, VIH, VIL are defined to be VIH = 0.7 VDD1, VIL = 0.3 VDD1 (Numbers clock and display data tSETUP2 2 1 ★ (2) R,/L= H, MODE = L 1 CLK PWCLK(H) are example when in SXGA). PWCLK(L) PWCLK µPD16721 9. RECOMMENDED MOUNTING CONDITIONS The following conditions must be met for mounting conditions of the µPD16721. For more details, refer to the Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case other mounting process is used, or in case the mounting is done under different conditions. µPD16721N-xxx: TCP (TAB Package) Mounting Condition Thermocompression Mounting Method Condition Soldering Heating tool 300 to 350°C, heating for 2 to 3 sec, pressure 100g (per ACF Temporaly bonding 70 to 100°C, pressure 3 to 8 kg/cm2, time 3 to 5 (Adhesive Conductive sec. Real bonding 165 to 180°C, pressure 25 to 45 kg/cm2, time 30 to Film) 40 sec (When using the anisotropy conductive film SUMIZAC1003 of solder). Sumitomo Bakelite, Ltd). Caution To find out the detailed conditions for mounting the ACF part, please contact the ACF manufacturing company. Be sure to avoid using two or more mounting methods at a time. 24 DataSheet S14791EJ1V0DS µPD16721 [MEMO] DataSheet S14791EJ1V0DS 25 µPD16721 [MEMO] 26 DataSheet S14791EJ1V0DS µPD16721 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. DataSheet S14791EJ1V0DS 27 µPD16721 Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades On NEC Semiconductor Devices (C11531E) • The information in this document is current as of February, 2002. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. • NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. 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The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above). M8E 00. 4