NEC UPD43256BGU-B12

DATA SHEET
MOS INTEGRATED CIRCUIT
μPD43256B
256K-BIT CMOS STATIC RAM
32K-WORD BY 8-BIT
Description
The μPD43256B is a high speed, low power, and 262,144 bits (32,768 words by 8 bits) CMOS static RAM.
Battery backup is available. And A and B versions are wide voltage operations.
The μPD43256B is packed in 28-pin PLASTIC DIP, 28-pin PLASTIC SOP and 28-pin PLASTIC TSOP (I) (8 x 13.4 mm).
Features
• 32,768 words by 8 bits organization
• Fast access time: 70, 85, 100, 120, 150 ns (MAX.)
• Low voltage operation (A version: VCC = 3.0 to 5.5 V, B version: VCC = 2.7 to 5.5 V)
• Low VCC data retention: 2.0 V (MIN.)
• /OE input for easy application
Part number
Access time
Operating supply Operating ambient
ns (MAX.)
μPD43256B-xxL
70, 85
voltage
temperature
At operating
At standby
At data retention
V
°C
mA (MAX.)
μA (MAX.)
μA (MAX.) Note1
4.5 to 5.5
0 to 70
45
50
3
15
2
μPD43256B-xxLL
μPD43256B-Axx
μPD43256B-Bxx Note2
85, 100
Note2
, 120
Note2
100, 120, 150
Supply current
3.0 to 5.5
2.7 to 5.5
Notes 1. TA ≤ 40 °C, VCC = 3.0 V
2. Access time: 85 ns (MAX.) (VCC = 4.5 to 5.5 V)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. M10770EJEV0DS00 (14th edition)
Date Published June 2006 NS CP (K)
Printed in Japan
1990, 1993, 1994
μPD43256B
Ordering Information
Part number
(1/2)
Package
Access time
ns (MAX.)
μPD43256BCZ-70L
28-pin PLASTIC DIP
70
μPD43256BCZ-85L
(15.24 mm (600))
85
μPD43256BCZ-70LL
70
μPD43256BCZ-85LL
85
μPD43256BGU-70L
28-pin PLASTIC SOP
70
μPD43256BGU-85L
(11.43 mm (450))
85
μPD43256BGU-70LL
70
μPD43256BGU-85LL
85
μPD43256BGU-A85
85
μPD43256BGU-A10
100
μPD43256BGU-A12
120
μPD43256BGU-B10
100
μPD43256BGU-B12
120
μPD43256BGW-70LL-9JL
28-pin PLASTIC TSOP (I)
70
μPD43256BGW-85LL-9JL
(8x13.4) (Normal bent)
85
μPD43256BGW-A85-9JL
85
μPD43256BGW-A10-9JL
100
μPD43256BGW-A12-9JL
120
μPD43256BGW-B10-9JL
100
μPD43256BGW-B12-9JL
120
μPD43256BGW-B15-9JL
150
μPD43256BGW-70LL-9KL
28-pin PLASTIC TSOP (I)
70
μPD43256BGW-85LL-9KL
(8x13.4) (Reverse bent)
85
μPD43256BGW-A85-9KL
85
μPD43256BGW-A10-9KL
100
μPD43256BGW-A12-9KL
120
μPD43256BGW-B10-9KL
100
μPD43256BGW-B12-9KL
120
μPD43256BGW-B15-9KL
150
2
Data Sheet M10770EJEV0DS
Operating supply Operating ambient
voltage
temperature
V
°C
4.5 to 5.5
0 to 70
Remark
L version
LL version
L version
LL version
3.0 to 5.5
A version
2.7 to 5.5
B version
4.5 to 5.5
LL version
3.0 to 5.5
A version
2.7 to 5.5
B version
4.5 to 5.5
LL version
3.0 to 5.5
A version
2.7 to 5.5
B version
μPD43256B
(2/2)
Part number
Package
Access time
Operating supply Operating ambient
ns (MAX.)
μPD43256BGU-70L-A
28-pin PLASTIC SOP
70
μPD43256BGU-85L-A
(11.43 mm (450))
85
μPD43256BGU-70LL-A
70
μPD43256BGU-85LL-A
85
μPD43256BGU-A85-A
85
μPD43256BGU-A10-A
100
μPD43256BGU-A12-A
120
μPD43256BGU-B10-A
100
μPD43256BGU-B12-A
120
μPD43256BGW-70LL-9JL-A
28-pin PLASTIC TSOP (I)
70
μPD43256BGW-85LL-9JL-A
(8x13.4) (Normal bent)
85
μPD43256BGW-A85-9JL-A
85
μPD43256BGW-A10-9JL-A
100
μPD43256BGW-A12-9JL-A
120
μPD43256BGW-B10-9JL-A
100
μPD43256BGW-B12-9JL-A
120
μPD43256BGW-B15-9JL-A
150
μPD43256BGW-70LL-9KL-A 28-pin PLASTIC TSOP (I)
70
μPD43256BGW-85LL-9KL-A (8x13.4) (Reverse bent)
85
μPD43256BGW-A85-9KL-A
85
μPD43256BGW-A10-9KL-A
100
μPD43256BGW-A12-9KL-A
120
μPD43256BGW-B10-9KL-A
100
μPD43256BGW-B12-9KL-A
120
μPD43256BGW-B15-9KL-A
150
Remark
voltage
temperature
V
°C
4.5 to 5.5
0 to 70
Remark
L version
LL version
3.0 to 5.5
A version
2.7 to 5.5
B version
4.5 to 5.5
LL version
3.0 to 5.5
A version
2.7 to 5.5
B version
4.5 to 5.5
LL version
3.0 to 5.5
A version
2.7 to 5.5
B version
Products with -A at the end of the part number are lead-free products.
Data Sheet M10770EJEV0DS
3
μPD43256B
Pin Configurations (Marking Side)
/xxx indicates active low signal.
28-pin PLASTIC DIP (15.24 mm (600))
[ μPD43256BCZ-xxL ]
[ μPD43256BCZ-xxLL ]
A14
1
28
VCC
A12
2
27
/WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
/OE
A2
8
21
A10
A1
9
20
/CS
A0
10
19
I/O8
I/O1
11
18
I/O7
I/O2
12
17
I/O6
I/O3
13
16
I/O5
GND
14
15
I/O4
A0 - A14
: Address inputs
I/O1 - I/O8
: Data inputs / outputs
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
VCC
: Power supply
GND
: Ground
Remark Refer to Package Drawings for the 1-pin index mark.
4
Data Sheet M10770EJEV0DS
μPD43256B
28-pin PLASTIC SOP (11.43 mm (450))
[ μPD43256BGU-xxL ]
[ μPD43256BGU-xxLL ]
[ μPD43256BGU-Axx ]
[ μPD43256BGU-Bxx ]
[ μPD43256BGU-xxL-A ]
[ μPD43256BGU-xxLL-A ]
[ μPD43256BGU-Axx-A ]
[ μPD43256BGU-Bxx-A ]
A14
1
28
VCC
A12
2
27
/WE
A7
3
26
A13
A6
4
25
A8
A5
5
24
A9
A4
6
23
A11
A3
7
22
/OE
A2
8
21
A10
A1
9
20
/CS
A0
10
19
I/O8
I/O1
11
18
I/O7
I/O2
12
17
I/O6
I/O3
13
16
I/O5
GND
14
15
I/O4
A0 - A14
: Address inputs
I/O1 - I/O8
: Data inputs / outputs
/CS
: Chip Select
/WE
: Write Enable
/OE
: Output Enable
VCC
: Power supply
GND
: Ground
Remark Refer to Package Drawings for the 1-pin index mark.
Data Sheet M10770EJEV0DS
5
μPD43256B
28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
[ μPD43256BGW-xxLL-9JL ]
[ μPD43256BGW-Axx-9JL ]
[ μPD43256BGW-Bxx-9JL ]
[ μPD43256BGW-xxLL-9JL-A ]
[ μPD43256BGW-Axx-9JL-A ]
[ μPD43256BGW-Bxx-9JL-A ]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
/OE
A11
A9
A8
A13
/WE
VCC
A14
A12
A7
A6
A5
A4
A3
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
[ μPD43256BGW-xxLL-9KL ]
[ μPD43256BGW-Axx-9KL ]
[ μPD43256BGW-Bxx-9KL ]
[ μPD43256BGW-xxLL-9KL-A ]
[ μPD43256BGW-Axx-9KL-A ]
[ μPD43256BGW-Bxx-9KL-A ]
A10
/CS
I/O8
I/O7
I/O6
I/O5
I/O4
GND
I/O3
I/O2
I/O1
A0
A1
A2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A0 - A14
:
Address inputs
/OE
: Output Enable
I/O1 - I/O8
:
Data inputs / outputs
VCC
: Power supply
/CS
:
Chip Select
GND :
/WE
:
Write Enable
Ground
Remark Refer to Package Drawings for the 1-pin index mark.
6
Data Sheet M10770EJEV0DS
/OE
A11
A9
A8
A13
/WE
VCC
A14
A12
A7
A6
A5
A4
A3
μPD43256B
Block Diagram
A0
Address
buffer
A14
Row
decoder
I/O1
Input data
controller
I/O8
Memory cell array
262,144 bits
Sense amplifier /
Switching circuit
Column decoder
Output data
controller
Address buffer
/CS
/OE
/WE
VCC
GND
Truth Table
/CS
/OE
/WE
Mode
I/O
Supply current
H
×
×
Not selected
High impedance
ISB
L
H
H
Output disable
L
×
L
Write
DIN
L
L
H
Read
DOUT
ICCA
Remark × : VIH or VIL
Data Sheet M10770EJEV0DS
7
μPD43256B
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
Supply voltage
Condition
Rating
VCC
–0.5
–0.5
Note
Note
Unit
to +7.0
V
to VCC + 0.5
V
Input / Output voltage
VT
Operating ambient temperature
TA
0 to 70
°C
Storage temperature
Tstg
–55 to +125
°C
Note –3.0 V (MIN.) (Pulse width : 50 ns)
Caution Exposing the device to stress above those listed in Absolute Maximum Rating could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter
Symbol Condition
μPD43256B-xxL
μPD43256B-Axx
μPD43256B-Bxx
Unit
μPD43256B-xxLL
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Supply voltage
VCC
4.5
5.5
3.0
5.5
2.7
5.5
V
High level input voltage
VIH
2.2
VCC+0.5
2.2
VCC+0.5
2.2
VCC+0.5
V
+0.5
V
70
°C
MAX.
Unit
Low level input voltage
VIL
–0.3
Operating ambient temperature
TA
0
Note
+0.8
70
–0.3
Note
+0.5
0
70
–0.3
0
Note
Note –3.0 V (MIN.) (Pulse width: 50 ns)
Capacitance (TA = 25 °C, f = 1 MHz)
Parameter
Symbol
Test conditions
MIN.
TYP.
Input capacitance
CIN
VIN = 0 V
5
pF
Input / Output capacitance
CI/O
VI/O = 0 V
8
pF
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These parameters are periodically sampled and not 100% tested.
8
Data Sheet M10770EJEV0DS
μPD43256B
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (1/2)
Parameter
Symbol
Test condition
μPD43256B-xxL
MIN.
TYP.
μPD43256B-xxLL
MAX.
MIN.
TYP.
Unit
MAX.
Input leakage current
ILI
VIN = 0 V to VCC
–1.0
+1.0
–1.0
+1.0
μA
I/O leakage current
ILO
VI/O = 0 V to VCC, /OE = VIH or
–1.0
+1.0
–1.0
+1.0
μA
mA
/CS = VIH or /WE = VIL
Operating supply current
ICCA1
/CS = VIL, Minimum cycle time, II/O = 0 mA
45
45
ICCA2
/CS = VIL, II/O = 0 mA
10
10
ICCA3
/CS ≤ 0.2 V, Cycle = 1 MHz,
10
10
3
3
mA
15
μA
II/O = 0 mA, VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
Standby supply current
High level output voltage
Low level output voltage
ISB
/CS = VIH
ISB1
/CS ≥ VCC − 0.2 V
VOH1
IOH = –1.0 mA
2.4
2.4
VOH2
IOH = –0.1 mA
VCC–0.5
VCC–0.5
VOL
IOL = 2.1 mA
1.0
50
0.4
0.5
V
0.4
V
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M10770EJEV0DS
9
μPD43256B
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted) (2/2)
Parameter
Symbol
μPD43256B-Axx
Test condition
MIN.
TYP.
μPD43256B-Bxx
MAX.
MIN.
TYP.
Unit
MAX.
Input leakage current
ILI
VIN = 0 V to VCC
–1.0
+1.0
–1.0
+1.0
μA
I/O leakage current
ILO
VI/O = 0 V to VCC, /OE = VIH or
–1.0
+1.0
–1.0
+1.0
μA
mA
/CS = VIH or /WE = VIL
Operating supply current
ICCA1
/CS = VIL,
μPD43256B-Axx
45
–
Minimum cycle time,
μPD43256B-Bxx
–
45
VCC ≤ 3.3 V
–
20
10
10
–
5
/CS ≤ 0.2 V, Cycle = 1 MHz, II/O = 0 mA,
10
10
VIL ≤ 0.2 V, VIH ≥ VCC – 0.2 V
–
5
3
3
–
2
II/O = 0 mA
ICCA2
/CS = VIL, II/O = 0 mA
VCC ≤ 3.3 V
ICCA3
Standby supply current
ISB
VCC ≤ 3.3 V
/CS = VIH
VCC ≤ 3.3 V
ISB1
/CS ≥ VCC − 0.2 V
0.5
VCC ≤ 3.3 V
High level output voltage
Low level output voltage
VOH1
0.5
15
–
0.5
10
IOH = –1.0 mA, VCC ≥ 4.5 V
2.4
2.4
IOH = –0.5 mA, VCC < 4.5 V
2.4
2.4
VCC–0.1
VCC–0.1
IOH = –0.02 mA
VOL
IOL = 2.1 mA, VCC ≥ 4.5 V
0.4
0.4
IOL = 1.0 mA, VCC < 4.5 V
0.4
0.4
IOL = 0.02 mA
0.1
0.1
Remarks 1. VIN : Input voltage
VI/O : Input / Output voltage
2. These DC characteristics are in common regardless of package types.
Data Sheet M10770EJEV0DS
μA
V
VOH2
VOL1
10
15
mA
V
μPD43256B
AC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
AC Test Conditions
[ μPD43256B-70L, μPD43256B-85L, μPD43256B-70LL, μPD43256B-85LL ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
Test points
1.5 V
1.5 V
0.8 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
Figure 1
Figure 2
(tAA, tACS, tOE, tOH)
(tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW)
+5 V
+5 V
1.8 kΩ
I/O (Output)
1.8 kΩ
I/O (Output)
990 Ω
990 Ω
100 pF
CL
5 pF
CL
Remark CL includes capacitance of the probe and jig, and stray capacitance.
[ μPD43256B-A85, μPD43256B-A10, μPD43256B-A12, μPD43256B-B10, μPD43256B-B12, μPD43256B-B15 ]
Input Waveform (Rise and Fall Time ≤ 5 ns)
2.2 V
1.5 V
Test points
1.5 V
0.5 V
Output Waveform
1.5 V
Test points
1.5 V
Output Load
AC characteristics should be measured with the following output load conditions.
tAA, tACS, tOE, tOH
tCHZ, tCLZ, tOHZ, tOLZ, tWHZ, tOW
1TTL + 100 pF
1TTL + 5 pF
Data Sheet M10770EJEV0DS
11
μPD43256B
Read Cycle (1/2)
Parameter
VCC ≥ 4.5 V
Symbol
Unit
μPD43256B-70
Condition
μPD43256B-85
μPD43256B-A85/A10/A12
μPD43256B-B10/B12/B15
MIN.
MAX.
MIN.
Read cycle time
tRC
Address access time
tAA
70
85
ns
/CS access time
tACS
70
85
ns
/OE access time
tOE
35
40
ns
Output hold from address change
tOH
10
10
ns
/CS to output in low impedance
tCLZ
10
10
ns
/OE to output in low impedance
tOLZ
5
5
ns
/CS to output in high impedance
tCHZ
30
30
ns
/OE to output in high impedance
tOHZ
30
30
ns
Note
70
MAX.
85
ns
Note
See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Read Cycle (2/2)
Parameter
VCC ≥ 3.0 V
Symbol
VCC ≥ 2.7 V
Unit
μPD43256B
μPD43256B
μPD43256B
μPD43256B
μPD43256B
μPD43256B
-A85
-A10
-A12
-B10
-B12
-B15
Condition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Read cycle time
tRC
85
100
120
100
120
150
ns
Address access
tAA
85
100
120
100
120
150
ns
/CS access time
tACS
85
100
120
100
120
150
ns
/OE access time
tOE
50
60
60
60
60
70
ns
Output hold from
tOH
10
10
10
10
10
10
ns
tCLZ
10
10
10
10
10
10
ns
tOLZ
5
5
5
5
5
5
ns
time
address change
/CS to output in
low impedance
/OE to output in
low impedance
/CS to output in
tCHZ
35
35
40
35
40
50
ns
tOHZ
35
35
40
35
40
50
ns
high impedance
/OE to output in
high impedance
Note
See the output load.
Remark These AC characteristics are in common regardless of package types.
12
Data Sheet M10770EJEV0DS
Note
μPD43256B
Read Cycle Timing Chart
tRC
Address (Input)
tAA
tOH
/CS (Input)
tCHZ
tACS
tCLZ
/OE (Input)
tOHZ
tOE
tOLZ
I/O (Output)
Remark
High impedance
Data out
In read cycle, /WE should be fixed to high level.
Data Sheet M10770EJEV0DS
13
μPD43256B
Write Cycle (1/2)
Parameter
VCC ≥ 4.5 V
Symbol
Unit
μPD43256B-70
Condition
μPD43256B-85
μPD43256B-A85/A10/A12
μPD43256B-B10/B12/B15
MIN.
MAX.
MIN.
MAX.
Write cycle time
tWC
70
85
ns
/CS to end of write
tCW
50
70
ns
Address valid to end of write
tAW
50
70
ns
Write pulse width
tWP
55
60
ns
Data valid to end of write
tDW
30
35
ns
Data hold time
tDH
0
0
ns
Address setup time
tAS
0
0
ns
Write recovery time
tWR
0
0
ns
/WE to output in high impedance
tWHZ
Output active from end of write
tOW
Note
30
30
10
ns
10
Note
ns
See the output load.
Remark These AC characteristics are in common regardless of package types and L, LL versions.
Write Cycle (2/2)
Parameter
VCC ≥ 3.0 V
Symbol
VCC ≥ 2.7 V
Unit Con-
μPD43256B
μPD43256B
μPD43256B
μPD43256B
μPD43256B
μPD43256B
-A85
-A10
-A12
-B10
-B12
-B15
dition
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Write cycle time
tWC
85
100
120
100
120
150
ns
/CS to end of write
tCW
70
70
90
70
90
100
ns
Address valid to
tAW
70
70
90
70
90
100
ns
Write pulse width
tWP
60
60
80
60
80
90
ns
Data valid to end
tDW
60
60
70
60
70
80
ns
Data hold time
tDH
0
0
0
0
0
0
ns
Address setup
tAS
0
0
0
0
0
0
ns
Write recovery
tWR
0
0
0
0
0
0
ns
/WE to output in
tWHZ
end of write
of write
30
35
40
35
40
50
ns
high impedance
Output active
tOW
10
10
10
10
from end of write
Note
See the output load.
Remark These AC characteristics are in common regardless of package types.
14
Data Sheet M10770EJEV0DS
10
10
ns
Note
μPD43256B
Write Cycle Timing Chart 1 (/WE Controlled)
tWC
Address (Input)
tCW
/CS (Input)
tAW
tAS
tWP
tWR
/WE (Input)
tOW
tWHZ
I/O (Input / Output)
tDW
High
impedance
Indefinite data out
Data in
tDH
High
impedance
Indefinite data out
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remarks 1. Write operation is done during the overlap time of a low level /CS and a low level /WE.
2. When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
3. If /CS changes to low level at the same time or after the change of /WE to low level, the I/O
pins will remain high impedance state.
Data Sheet M10770EJEV0DS
15
μPD43256B
Write Cycle Timing Chart 2 (/CS Controlled)
tWC
Address (Input)
tAS
tCW
/CS (Input)
tAW
tWP
tWR
/WE (Input)
tDW
tDH
High impedance
Data in
I/O (Input)
High
impedance
Cautions 1. /CS or /WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, therefore the input signals must not be applied to
the output.
Remark
16
Write operation is done during the overlap time of a low level /CS and a low level /WE.
Data Sheet M10770EJEV0DS
μPD43256B
Low VCC Data Retention Characteristics (TA = 0 to 70 °C)
Parameter
Symbol
μPD43256B-xxL
Test Condition
μPD43256B-xxLL
Unit
μPD43256B-Axx
μPD43256B-Bxx
MIN.
TYP.
MAX.
MIN.
5.5
2.0
TYP.
MAX.
VCCDR
/CS ≥ VCC − 0.2 V
Data retention supply current
ICCDR
VCC = 3.0 V, /CS ≥ VCC − 0.2 V
Chip deselection
tCDR
0
0
ns
tR
5
5
ms
Data retention supply voltage
2.0
0.5
20
Note1
5.5
0.5
7
V
Note2
μA
to data retention mode
Operation recovery time
Notes 1. 3 μA (TA ≤ 40 °C)
2. 2 μA (TA ≤ 40 °C), 1 μA (TA ≤ 25 °C)
Data Retention Timing Chart
tCDR
Data retention mode
tR
VCC
4.5 V
Note
/CS
VIH (MIN.)
VCCDR (MIN.)
/CS ≥ VCC – 0.2 V
VIL (MAX.)
GND
Note A version : 3.0 V, B version : 2.7 V
Remark
The other pins (Address, /OE, /WE, I/O) can be in high impedance state.
Data Sheet M10770EJEV0DS
17
μPD43256B
Package Drawings
28-PIN PLASTIC DIP (15.24 mm (600))
28
15
1
14
A
J
K
I
L
F
D
C
N
B
R
M
M
H
G
NOTES
1. Each lead centerline is located within 0.25 mm
of its true position (T.P.) at maximum material condition.
2. Item "K" to center of leads when formed parallel.
ITEM
MILLIMETERS
A
38.10 MAX.
B
2.54 MAX.
C
2.54 (T.P.)
D
0.50±0.10
F
1.2 MIN.
G
3.6±0.3
H
0.51 MIN.
I
4.31 MAX.
J
5.72 MAX.
K
L
15.24 (T.P.)
13.2
M
0.25 +0.10
−0.05
N
0.25
R
0 - 15°
P28C-100-600A1-2
18
Data Sheet M10770EJEV0DS
μPD43256B
28-PIN PLASTIC SOP (11.43 mm (450))
28
15
detail of lead end
P
1
14
A
F
H
G
I
J
S
C
D
M
N
M
L
S
B
K
E
NOTE
Each lead centerline is located within 0.12 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
18.0 +0.6
−0.05
B
1.27 MAX.
C
1.27 (T.P.)
D
0.42 +0.08
−0.07
E
0.2±0.1
F
2.95 MAX.
G
2.55±0.1
H
11.8±0.3
I
J
8.4±0.1
1.7±0.2
K
0.22±0.05
L
M
0.7±0.2
0.12
N
0.10
P
3° +7°
−3°
P28GU-50-450A-4
Data Sheet M10770EJEV0DS
19
μPD43256B
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
S
R
14
Q
15
P
A
J
I
G
S
L
B
C
H
N
S
D
M
M
K
NOTES
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
ITEM
A
MILLIMETERS
8.0±0.1
B
C
0.6 MAX.
0.55 (T.P.)
D
0.22 +0.08
−0.07
G
H
1.0
12.4±0.2
I
11.8±0.1
J
0.8±0.2
K
0.145 +0.025
−0.015
L
0.5±0.1
M
0.08
N
0.10
P
13.4±0.2
Q
0.1±0.05
R
S
3° +7°
−3°
1.2 MAX.
P28GW-55-9JL-2
20
Data Sheet M10770EJEV0DS
μPD43256B
28-PIN PLASTIC TSOP(I) (8x13.4)
1
28
detail of lead end
Q
R
14
15
S
K
N
H
D
S
L
M
M
C
B
S
G
I
J
A
P
NOTE
1. Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.
2. "A" excludes mold flash. (Includes mold flash : 8.4mm MAX.)
ITEM
A
MILLIMETERS
8.0±0.1
B
C
0.6 MAX.
0.55 (T.P.)
D
0.22 +0.08
−0.07
G
H
1.0
12.4±0.2
I
11.8±0.1
J
0.8±0.2
K
0.145 +0.025
−0.015
L
M
0.5±0.1
0.08
N
0.10
P
13.4±0.2
Q
0.1±0.05
R
3° +7°
−3°
S
1.2 MAX.
P28GW-55-9KL-2
Data Sheet M10770EJEV0DS
21
μPD43256B
Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the μPD43256B.
Types of Surface Mount Device
μPD43256BGU-xxL
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-xxLL
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-Axx
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-Bxx
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGW-xxLL-9JL
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-xxLL-9KL
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μPD43256BGW-Axx-9JL
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-Axx-9KL
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μPD43256BGW-Bxx-9JL
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-Bxx-9KL
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μPD43256BGU-xxL-A
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-xxLL-A
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-Axx-A
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGU-Bxx-A
: 28-pin PLASTIC SOP (11.43 mm (450))
μPD43256BGW-xxLL-9JL-A
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-xxLL-9KL-A : 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μPD43256BGW-Axx-9JL-A
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-Axx-9KL-A
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
μPD43256BGW-Bxx-9JL-A
: 28-pin PLASTIC TSOP (I) (8x13.4) (Normal bent)
μPD43256BGW-Bxx-9KL-A
: 28-pin PLASTIC TSOP (I) (8x13.4) (Reverse bent)
Types of Through Hole Mount Device
μPD43256BCZ-xxL
: 28-pin PLASTIC DIP (15.24 mm (600))
μPD43256BCZ-xxLL
: 28-pin PLASTIC DIP (15.24 mm (600))
Soldering process
Wave soldering (only to leads)
Soldering conditions
Solder temperature : 260 °C or below,
Flow time : 10 seconds or below
Partial heating method
Terminal temperature : 300 °C or below,
Time : 3 seconds or below (Per one lead)
Caution Do not jet molten solder on the surface of package.
22
Data Sheet M10770EJEV0DS
μPD43256B
Revision History
Edition/
Date
14th edition/
Page
Type of
This
Previous
edition
edition
p.1
p.1
Location
(Previous edition → This edition)
revision
Deletion
Description
−
Description of Version X and P has been deleted.
Jun. 2006
Data Sheet M10770EJEV0DS
23
μPD43256B
[ MEMO ]
24
Data Sheet M10770EJEV0DS
μPD43256B
[ MEMO ]
Data Sheet M10770EJEV0DS
25
μPD43256B
[ MEMO ]
26
Data Sheet M10770EJEV0DS
μPD43256B
NOTES FOR CMOS DEVICES
1
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between VIL (MAX) and
VIH (MIN).
2
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
3
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred.
Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded.
The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
4
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
5
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
6
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
Data Sheet M10770EJEV0DS
27
μPD43256B
• The information in this document is current as of June, 2006. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
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M8E 02. 11-1