ETC UPD65889

0.5µm CMOS Gate Array
CMOS-N5 Family
New
s
t
c
u
Prod
Features
The CMOS-N5 family is a channel-less type gate array that provides high speed operation with a 5-V power supply voltage.
Drastic cost reductions have been achieved compared with the conventional CMOS-6 and CMOS-8 families thanks to
higher integration by the adoption of 0.5 µm technology (2-layer wiring), and lowering the package assembly cost.
Moreover, the 3-V power supply voltage is supported for the CMOS-N5 family.
NEW
CMOS-6 Family
CMOS-N5 Family
CMOS-8 Family
[Integration]
• 3K to 120K gates (number of integrated gates)
• 2K to 86K gates (number of usable gates)
[Package]
• QFP (Fine pitch) 160 to 304 pins
• TQFP
48 to 80 pins
• LQFP
44 to 160 pins
[High-speed operation] (preliminary)
• tPD = 0.26 ns (2-input NAND (power gate), fanout = 2, standard wiring length)
• Operating frequency: 60 MHz max.
[Function blocks]
• CPU peripheral block
• RAM block (1 port/2 ports)
• Oscillation block
• CTS block
[Test design]
• Scan path test
2
Pamphlet A13629EJ5V1PF
Product Overview
Product type list
Product name
Note 1
Number of integrated gates
Number of usable gates
Note 2
Note 3
Number of pads
µPD65880
µPD65881
µPD65882
µPD65883
µPD65884
3456
5880
13952
25344
33864
2764
4704
11161
20275
27091
72
88
120
160
184
Internal gate
0.46 ns (fanout = 2, wiring length=2mm)
Power gate
0.30 ns (fanout = 2, wiring length=2mm)
Input buffer
0.33 ns (fanout = 2, wiring length=2mm)
Output buffer
1.30 ns (CL = 15 pF)
Output drive capability
IOL = 3, 6, 9, 12, 18, 24 mA
Power supply voltage
5 V ± 10 % (CMOS level)
Product name
Note 1
Number of integrated gates
Number of usable gates
Note 4
Note 3
Number of pads
µPD65885
µPD65887
µPD65889
µPD65890
µPD65893
40768
56496
76000
99528
123384
28537
39547
53200
69669
86368
244
284
324
372
412
Internal gate
0.46 ns (fanout = 2, wiring length=2mm)
Power gate
0.30 ns (fanout = 2, wiring length=2mm)
Input buffer
0.33 ns (fanout = 2, wiring length=2mm)
Output buffer
1.30 ns (CL = 15 pF)
Output drive capability
IOL = 3, 6, 9, 12, 18, 24 mA
Power supply voltage
5 V ± 10 % (CMOS level)
Notes 1. 2-input NAND conversion
2. Cell utilization rate 80 %
3. Including power supply and GND pins. The number of pins that can actually be used differs depending on the type
of package.
4. Cell utilization rate 70 %
Pamphlet A13629EJ5V1PF
3
Package list (1)
Package
QFP (FP)
TQFP
LQFP
Remark
4
Number of pins
Lead pitch (mm)
Body height (mm)
Body size (mm)
160
0.5
2.7
24 × 24
208
0.5
3.2
28 × 28
240
0.5
3.2
32 × 32
304
0.5
3.7
40 × 40
48
0.5
1.0
7×7
64
0.65
1.0
12 × 12
80
0.5
1.0
12 × 12
44
0.8
1.4
10 × 10
100
0.5
1.4
14 × 14
160
0.5
1.4
24 × 24
FP : Fine pitch
Pamphlet A13629EJ5V1PF
Package list (2)
µPD65880
µPD65881
µPD65882
µPD65883
µPD65884
160-pin QFP (FP)
–
–
–
–
–
208-pin QFP (FP)
–
–
–
–
–
240-pin QFP (FP)
–
–
–
–
–
304-pin QFP (FP)
–
–
–
–
–
Master name
48-pin TQFP
–
64-pin TQFP
–
80-pin TQFP
–
–
44-pin LQFP
–
100-pin LQFP
–
–
160-pin LQFP
–
–
–
–
µPD65885
µPD65887
µPD65889
µPD65890
µPD65893
–
–
–
Master name
160-pin QFP (FP)
208-pin QFP (FP)
240-pin QFP (FP)
–
304-pin QFP (FP)
–
–
–
48-pin TQFP
–
–
–
–
–
64-pin TQFP
–
–
–
80-pin TQFP
–
–
–
–
–
–
–
–
44-pin LQFP
–
–
100-pin LQFP
160-pin LQFP
Remark
: Released
–
–
– : Not to be supported
Blank : Under consideration
Pamphlet A13629EJ5V1PF
FP : Fine pitch
5
Development Tools
Easy interface with your EWS or PC
Users can choose the following tools to their environment.
Caution
Some functions may not be supported. Make it sure before use.
OPENCADTM V5.4 Configuration Tool
Function
NEC Tool
Function simulator
–
Interface Data
• Netlist
PWC/EDIF(2.0.0)/
VdrawTM
Schematic editor
Logic synthesis
Gate level simulator
• Test pattern
V.sim
ALBA
STANote 1
Tiara
Fault simulator Note 2
C.FGRADETM
–
®
ModelSim/Verilog-XL/NC-Verilog/
VCS
Formality ®/TuxedoTM-LEC
–
Design for test
NC-VerilogTM/VCSTM
Design Compiler
TM
Formal verifier
ModelSimTM/Verilog-XLTM/
VerilogTM HDL
–
Note 1
Commercially Available Tool Interface
• Delay information file
PrimeTime®
–
TESTACT/NEC_SCAN/
• Constraints file
NEC_BSCAN/NEC_BIST/
TM
TestCompiler /TestgenTM
FastScanTM/TetraMaxTM
TESTBUS
Floor planner
Note 3
ace_floorplan
–
galet_floorplan
Placement and Routing
Note 3
Gate EnsembleTM
Galet
Silicon EnsembleTM
Notes 1. Sign-off tool
2. Tool not supported in the HPTM version
3. Stand-alone tool
Remark Platform: SUNTM(SolarisTM)/HP(HP-UXTM)
GUI
: X11R5/MotifTM 1.2
C.FGRADE, OPENCAD, Vdraw and V.sim are trademarks of NEC Corporation.
Design Compiler is a registered trademark of Synopsys, Inc. in Japan.
PrimeTime and Formality are registered trademarks of Synopsys, Inc. in the USA.
Testgen, TetraMAX, TestCompiler and VCS are trademarks of Synopsys, Inc.
Gate Ensemble, Silicon Ensemble, NC-Verilog, Verilog, and Verilog-XL are trademarks of Cadence Design Systems, Inc.
ModelSim is a trademark of Model Technology, Inc.
Tuxedo is a trademark of Verplex System, Inc.
FastScan is a trademark of Mentor Graphics, Inc.
SUN and Solaris are trademarks of SUN Microsystems, Inc.
HP and HP-UX are trademarks of Hewlett-Packard Co.
Motif is a trademark of Open Software Foundation, Inc. (OSF).
6
Pamphlet A13629EJ5V1PF
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is current as of February, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
• No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
• NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
• Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
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agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
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"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
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The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
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(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
Pamphlet A13629EJ5V1PF
7
For further information, please contact:
NEC Corporation
NEC Building
7-1, Shiba 5-chome, Minato-ku
Tokyo 108-8001, Japan
Tel: 03-3454-1111
http://www.ic.nec.co.jp/
[North & South America]
[Europe]
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800-366-9782
Fax: 408-588-6130
800-729-9288
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http://www.nec.de/
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[Asia & Oceania]
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Fax: 250-3583
G01. 7
Document No. A13629EJ5V2PF00(5th edition)
Date Published August 2001 N CP(K)
© NEC Corporation 1998
Printed in Japan